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From: Yazen Ghannam <yazen.ghannam@amd.com>
To: "Zhuo, Qiuxu" <qiuxu.zhuo@intel.com>
Cc: "x86@kernel.org" <x86@kernel.org>,
	"Luck, Tony" <tony.luck@intel.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
	"Smita.KoralahalliChannabasappa@amd.com"
	<Smita.KoralahalliChannabasappa@amd.com>
Subject: Re: [PATCH v2 03/16] x86/mce/amd: Remove smca_banks_map
Date: Mon, 17 Feb 2025 09:17:33 -0500	[thread overview]
Message-ID: <20250217141733.GD591070@yaz-khff2.amd.com> (raw)
In-Reply-To: <CY8PR11MB713439C32E76A85C09C666BB89FB2@CY8PR11MB7134.namprd11.prod.outlook.com>

On Mon, Feb 17, 2025 at 07:57:47AM +0000, Zhuo, Qiuxu wrote:
> > From: Yazen Ghannam <yazen.ghannam@amd.com>
> > Sent: Friday, February 14, 2025 12:46 AM
> > To: x86@kernel.org; Luck, Tony <tony.luck@intel.com>
> > Cc: linux-kernel@vger.kernel.org; linux-edac@vger.kernel.org;
> > Smita.KoralahalliChannabasappa@amd.com; Yazen Ghannam
> > <yazen.ghannam@amd.com>
> > Subject: [PATCH v2 03/16] x86/mce/amd: Remove smca_banks_map
> > 
> > The MCx_MISC0[BlkPtr] field was used on legacy systems to hold a register
> > offset for the next MCx_MISC* register. In this way, an implementation-
> > specific number of registers can be discovered at runtime.
> > 
> > The MCAX/SMCA register space simplifies this by always including the
> > MCx_MISC[1-4] registers. The MCx_MISC0[BlkPtr] field is used to indicate
> > (true/false) whether any MCx_MISC[1-4] registers are present.
> > But it does not indicate which ones nor how many. Therefore, all the registers
> 
> s/nor/or     (suggested by AI 😊)
> OR
> s/does not indicate/indicates neither
> 

Hmm, okay, I think the second one.

  "But it indicates neither which ones nor how many".

I guess this falls under "Using 'nor' without a correlative pair".
https://www.learngrammar.net/a/how-to-use-nor-properly-in-a-sentence

:)

> > are accessed and their bits are checked.
> > 
> > AMD systems generally enforce a Read-as-Zero/Writes-Ignored policy for
> > unused registers. Therefore, there is no harm to read an unused register. This
> > is already done in practice for most of the MCx_MISC registers.
> > 
> > Remove the smca_banks_map variable as it is effectively redundant.
> > 
> > Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
> 
> Aside from the small nit above,
> 
>     Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> 

Thanks,
Yazen

  reply	other threads:[~2025-02-17 14:17 UTC|newest]

Thread overview: 63+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-13 16:45 [PATCH v2 00/16] AMD MCA interrupts rework Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 01/16] x86/mce: Don't remove sysfs if thresholding sysfs init fails Yazen Ghannam
2025-02-17  6:58   ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 02/16] x86/mce/amd: Remove return value for mce_threshold_create_device() Yazen Ghannam
2025-02-17  7:11   ` Zhuo, Qiuxu
2025-02-17 14:09     ` Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 03/16] x86/mce/amd: Remove smca_banks_map Yazen Ghannam
2025-02-17  7:57   ` Zhuo, Qiuxu
2025-02-17 14:17     ` Yazen Ghannam [this message]
2025-02-13 16:45 ` [PATCH v2 04/16] x86/mce/amd: Put list_head in threshold_bank Yazen Ghannam
2025-02-18  1:28   ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 05/16] x86/mce: Cleanup bank processing on init Yazen Ghannam
2025-02-13 22:32   ` Luck, Tony
2025-02-17 13:55     ` Yazen Ghannam
2025-02-18 16:40       ` Luck, Tony
2025-02-18  2:15   ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 06/16] x86/mce: Remove __mcheck_cpu_init_early() Yazen Ghannam
2025-02-18  3:00   ` Zhuo, Qiuxu
2025-02-19 15:53     ` Yazen Ghannam
2025-02-27 15:25   ` Borislav Petkov
2025-02-27 16:31     ` Yazen Ghannam
2025-02-27 19:33       ` Borislav Petkov
2025-02-27 19:59         ` Yazen Ghannam
2025-02-27 20:48           ` Borislav Petkov
2025-02-28 14:29             ` Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 07/16] x86/mce: Define BSP-only init Yazen Ghannam
2025-02-18  3:16   ` Zhuo, Qiuxu
2025-02-19 15:57     ` Yazen Ghannam
2025-02-20  1:37       ` Zhuo, Qiuxu
2025-02-20 14:36         ` Yazen Ghannam
2025-02-24 13:28           ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 08/16] x86/mce: Define BSP-only SMCA init Yazen Ghannam
2025-02-18  3:33   ` Zhuo, Qiuxu
2025-02-19 16:01     ` Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 09/16] x86/mce: Do 'UNKNOWN' vendor check early Yazen Ghannam
2025-02-18  5:31   ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 10/16] x86/mce: Separate global and per-CPU quirks Yazen Ghannam
2025-02-18  6:03   ` Zhuo, Qiuxu
2025-02-19 16:06     ` Yazen Ghannam
2025-02-20  1:27       ` Zhuo, Qiuxu
2025-02-20 14:37         ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 11/16] x86/mce: Move machine_check_poll() status checks to helper functions Yazen Ghannam
2025-02-18  6:29   ` Zhuo, Qiuxu
2025-02-13 16:46 ` [PATCH v2 12/16] x86/mce: Unify AMD THR handler with MCA Polling Yazen Ghannam
2025-02-18  6:42   ` Zhuo, Qiuxu
2025-02-19 16:07     ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 13/16] x86/mce: Unify AMD DFR " Yazen Ghannam
2025-02-18  7:37   ` Zhuo, Qiuxu
2025-02-19 16:09     ` Yazen Ghannam
2025-02-20  1:41       ` Zhuo, Qiuxu
2025-02-20 14:41         ` Yazen Ghannam
2025-02-24 13:31           ` Zhuo, Qiuxu
2025-02-13 16:46 ` [PATCH v2 14/16] x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems Yazen Ghannam
2025-02-18  8:23   ` Zhuo, Qiuxu
2025-02-19 16:16     ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 15/16] x86/mce/amd: Support SMCA Corrected Error Interrupt Yazen Ghannam
2025-02-13 22:34   ` Luck, Tony
2025-02-17 14:06     ` Yazen Ghannam
2025-02-18 13:27   ` Zhuo, Qiuxu
2025-02-19 16:19     ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 16/16] x86/mce: Handle AMD threshold interrupt storms Yazen Ghannam
2025-02-18 13:51   ` Zhuo, Qiuxu
2025-02-13 22:40 ` [PATCH v2 00/16] AMD MCA interrupts rework Luck, Tony

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