From: Simon Horman <horms@kernel.org>
To: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org,
Karol Kolacinski <karol.kolacinski@intel.com>,
Milena Olech <milena.olech@intel.com>
Subject: Re: [Intel-wired-lan] [PATCH iwl-next 2/3] ice: change SMA pins to SDP in PTP API
Date: Thu, 20 Feb 2025 13:13:35 +0000 [thread overview]
Message-ID: <20250220131335.GW1615191@kernel.org> (raw)
In-Reply-To: <20250207180254.549314-3-arkadiusz.kubalewski@intel.com>
On Fri, Feb 07, 2025 at 07:02:53PM +0100, Arkadiusz Kubalewski wrote:
> From: Karol Kolacinski <karol.kolacinski@intel.com>
>
> This change aligns E810 PTP pin control to all other products.
>
> Currently, SMA/U.FL port expanders are controlled together with SDP pins
> connected to 1588 clock. To align this, separate this control by
> exposing only SDP20..23 pins in PTP API on adapters with DPLL.
>
> Clear error for all E810 on absent NVM pin section or other errors to
> allow proper initialization on SMA E810 with NVM section.
>
> Use ARRAY_SIZE for pin array instead of internal definition.
>
> Reviewed-by: Milena Olech <milena.olech@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Reviewed-by: Simon Horman <horms@kernel.org>
WARNING: multiple messages have this Message-ID (diff)
From: Simon Horman <horms@kernel.org>
To: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org,
Karol Kolacinski <karol.kolacinski@intel.com>,
Milena Olech <milena.olech@intel.com>
Subject: Re: [PATCH iwl-next 2/3] ice: change SMA pins to SDP in PTP API
Date: Thu, 20 Feb 2025 13:13:35 +0000 [thread overview]
Message-ID: <20250220131335.GW1615191@kernel.org> (raw)
In-Reply-To: <20250207180254.549314-3-arkadiusz.kubalewski@intel.com>
On Fri, Feb 07, 2025 at 07:02:53PM +0100, Arkadiusz Kubalewski wrote:
> From: Karol Kolacinski <karol.kolacinski@intel.com>
>
> This change aligns E810 PTP pin control to all other products.
>
> Currently, SMA/U.FL port expanders are controlled together with SDP pins
> connected to 1588 clock. To align this, separate this control by
> exposing only SDP20..23 pins in PTP API on adapters with DPLL.
>
> Clear error for all E810 on absent NVM pin section or other errors to
> allow proper initialization on SMA E810 with NVM section.
>
> Use ARRAY_SIZE for pin array instead of internal definition.
>
> Reviewed-by: Milena Olech <milena.olech@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Reviewed-by: Simon Horman <horms@kernel.org>
next prev parent reply other threads:[~2025-02-20 13:13 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-07 18:02 [Intel-wired-lan] [PATCH iwl-next 0/3] ice: decouple control of SMA/U.FL/SDP pins Arkadiusz Kubalewski
2025-02-07 18:02 ` Arkadiusz Kubalewski
2025-02-07 18:02 ` [Intel-wired-lan] [PATCH iwl-next 1/3] ice: redesign dpll sma/u.fl pins control Arkadiusz Kubalewski
2025-02-07 18:02 ` Arkadiusz Kubalewski
2025-02-20 13:13 ` [Intel-wired-lan] " Simon Horman
2025-02-20 13:13 ` Simon Horman
2025-02-07 18:02 ` [Intel-wired-lan] [PATCH iwl-next 2/3] ice: change SMA pins to SDP in PTP API Arkadiusz Kubalewski
2025-02-07 18:02 ` Arkadiusz Kubalewski
2025-02-20 13:13 ` Simon Horman [this message]
2025-02-20 13:13 ` Simon Horman
2025-02-07 18:02 ` [Intel-wired-lan] [PATCH iwl-next 3/3] ice: add ice driver PTP pin documentation Arkadiusz Kubalewski
2025-02-07 18:02 ` Arkadiusz Kubalewski
2025-02-20 13:13 ` [Intel-wired-lan] " Simon Horman
2025-02-20 13:13 ` Simon Horman
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