From: Serhii Iliushyk <sil-plv@napatech.com>
To: dev@dpdk.org
Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com,
stephen@networkplumber.org
Subject: [PATCH v1 14/32] net/ntnic: add minimal reset FPGA
Date: Thu, 20 Feb 2025 23:03:38 +0100 [thread overview]
Message-ID: <20250220220406.3925597-15-sil-plv@napatech.com> (raw)
In-Reply-To: <20250220220406.3925597-1-sil-plv@napatech.com>
Define and register FPGA reset operations.
Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
.../include/ntnic_nthw_fpga_rst_nt400dxx.h | 34 +++++++
drivers/net/ntnic/meson.build | 2 +
.../nthw/core/nt400dxx/nthw_fpga_nt400dxx.c | 88 ++++++++++++++++++-
.../core/nt400dxx/reset/nthw_fpga_rst9574.c | 40 +++++++++
.../nt400dxx/reset/nthw_fpga_rst_nt400dxx.c | 33 +++++++
drivers/net/ntnic/ntnic_mod_reg.c | 30 +++++++
drivers/net/ntnic/ntnic_mod_reg.h | 21 +++++
7 files changed, 247 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt400dxx.h
create mode 100644 drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst9574.c
create mode 100644 drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c
diff --git a/drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt400dxx.h b/drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt400dxx.h
new file mode 100644
index 0000000000..2f04907ac9
--- /dev/null
+++ b/drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt400dxx.h
@@ -0,0 +1,34 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 Napatech A/S
+ */
+
+#ifndef __NTNIC_NTHW_FPGA_RST_NT400DXX_H__
+#define __NTNIC_NTHW_FPGA_RST_NT400DXX_H__
+
+#include "nthw_drv.h"
+#include "nthw_fpga_model.h"
+
+struct nthw_fpga_rst_nt400dxx {
+ int n_fpga_product_id;
+ int n_fpga_version;
+ int n_fpga_revision;
+ int n_hw_id;
+ bool mb_is_nt400d11;
+
+ nthw_field_t *p_fld_rst_sys;
+ nthw_field_t *p_fld_rst_ddr4;
+ nthw_field_t *p_fld_rst_phy_ftile;
+
+ nthw_field_t *p_fld_stat_ddr4_calib_complete;
+ nthw_field_t *p_fld_stat_phy_ftile_rst_done;
+ nthw_field_t *p_fld_stat_phy_ftile_rdy;
+
+ nthw_field_t *p_fld_latch_ddr4_calib_complete;
+ nthw_field_t *p_fld_latch_phy_ftile_rst_done;
+ nthw_field_t *p_fld_latch_phy_ftile_rdy;
+};
+
+typedef struct nthw_fpga_rst_nt400dxx nthw_fpga_rst_nt400dxx_t;
+
+#endif /* __NTHW_FPGA_RST_NT400DXX_H__ */
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index d56e85dd66..5a159f8bc6 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -45,7 +45,9 @@ sources = files(
'nthw/core/nt200a0x/nthw_fpga_nt200a0x.c',
'nthw/core/nt400dxx/nthw_fpga_nt400dxx.c',
'nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c',
+ 'nthw/core/nt400dxx/reset/nthw_fpga_rst9574.c',
'nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c',
+ 'nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c',
'nthw/core/nthw_fpga.c',
'nthw/core/nthw_gmf.c',
'nthw/core/nthw_gfg.c',
diff --git a/drivers/net/ntnic/nthw/core/nt400dxx/nthw_fpga_nt400dxx.c b/drivers/net/ntnic/nthw/core/nt400dxx/nthw_fpga_nt400dxx.c
index 3f86843ff3..0a5add60e0 100644
--- a/drivers/net/ntnic/nthw/core/nt400dxx/nthw_fpga_nt400dxx.c
+++ b/drivers/net/ntnic/nthw/core/nt400dxx/nthw_fpga_nt400dxx.c
@@ -5,13 +5,99 @@
#include "nthw_fpga.h"
#include "ntnic_mod_reg.h"
-
+#include "ntlog.h"
static int nthw_fpga_nt400dxx_init(struct fpga_info_s *p_fpga_info)
{
assert(p_fpga_info);
+ struct rst9574_ops *rst9574_ops = NULL;
+
+ const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str;
+ struct nthw_fpga_rst_nt400dxx rst;
int res = -1;
+ nthw_fpga_t *p_fpga = p_fpga_info->mp_fpga;
+ assert(p_fpga);
+
+ switch (p_fpga_info->n_fpga_prod_id) {
+ case 9574:
+ rst9574_ops = get_rst9574_ops();
+
+ if (rst9574_ops == NULL) {
+ NT_LOG(ERR, NTHW, "%s: RST 9574 NOT INCLUDED", p_adapter_id_str);
+ return -1;
+ }
+
+ res = rst9574_ops->nthw_fpga_rst9574_setup(p_fpga, &rst);
+
+ if (res) {
+ NT_LOG(ERR, NTHW,
+ "%s: %s: FPGA=%04d Failed to create reset module res=%d",
+ p_adapter_id_str, __func__, p_fpga_info->n_fpga_prod_id, res);
+ return res;
+ }
+
+ break;
+
+ default:
+ NT_LOG(ERR, NTHW, "%s: Unsupported FPGA product: %04d",
+ p_adapter_id_str, p_fpga_info->n_fpga_prod_id);
+ return -1;
+ }
+
+ struct rst_nt400dxx_ops *rst_nt400dxx_ops = get_rst_nt400dxx_ops();
+
+ if (rst_nt400dxx_ops == NULL) {
+ NT_LOG(ERR, NTHW, "RST NT400DXX NOT INCLUDED");
+ return -1;
+ }
+
+ /* reset common */
+ res = rst_nt400dxx_ops->nthw_fpga_rst_nt400dxx_init(p_fpga_info);
+
+ if (res) {
+ NT_LOG(ERR, NTHW, "%s: %s: FPGA=%04d - Failed to init common modules res=%d",
+ p_adapter_id_str, __func__, p_fpga_info->n_fpga_prod_id, res);
+ return res;
+ }
+
+ res = rst_nt400dxx_ops->nthw_fpga_rst_nt400dxx_reset(p_fpga_info);
+
+ if (res) {
+ NT_LOG(ERR, NTHW,
+ "%s: %s: FPGA=%04d - Failed to reset common modules res=%d",
+ p_adapter_id_str, __func__, p_fpga_info->n_fpga_prod_id, res);
+ return res;
+ }
+
+ /* reset specific */
+ switch (p_fpga_info->n_fpga_prod_id) {
+ case 9574:
+ if (rst9574_ops)
+ res = rst9574_ops->nthw_fpga_rst9574_init(p_fpga_info, &rst);
+
+ if (res) {
+ NT_LOG(ERR, NTHW,
+ "%s: %s: FPGA=%04d - Failed to reset 9574 modules res=%d",
+ p_adapter_id_str, __func__, p_fpga_info->n_fpga_prod_id, res);
+ return res;
+ }
+
+ break;
+
+ default:
+ NT_LOG(ERR, NTHW, "%s: Unsupported FPGA product: %04d",
+ p_adapter_id_str, p_fpga_info->n_fpga_prod_id);
+ res = -1;
+ break;
+ }
+
+ if (res) {
+ NT_LOG(ERR, NTHW, "%s: %s: loc=%u: FPGA=%04d res=%d", p_adapter_id_str,
+ __func__, __LINE__, p_fpga_info->n_fpga_prod_id, res);
+ return res;
+ }
+
return res;
}
diff --git a/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst9574.c b/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst9574.c
new file mode 100644
index 0000000000..9ab26583df
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst9574.c
@@ -0,0 +1,40 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+#include "nthw_drv.h"
+#include "nthw_register.h"
+#include "nthw_fpga.h"
+
+#include "ntnic_nthw_fpga_rst_nt400dxx.h"
+#include "ntnic_mod_reg.h"
+
+static int nthw_fpga_rst9574_setup(nthw_fpga_t *p_fpga, struct nthw_fpga_rst_nt400dxx *const p)
+{
+ assert(p_fpga);
+ assert(p);
+
+ return 0;
+};
+
+
+
+static int nthw_fpga_rst9574_init(struct fpga_info_s *p_fpga_info,
+ struct nthw_fpga_rst_nt400dxx *p_rst)
+{
+ assert(p_fpga_info);
+ assert(p_rst);
+ int res = -1;
+
+ return res;
+}
+
+static struct rst9574_ops rst9574_ops = {
+ .nthw_fpga_rst9574_init = nthw_fpga_rst9574_init,
+ .nthw_fpga_rst9574_setup = nthw_fpga_rst9574_setup,
+};
+
+void rst9574_ops_init(void)
+{
+ register_rst9574_ops(&rst9574_ops);
+}
diff --git a/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c b/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c
new file mode 100644
index 0000000000..e0e4bc0861
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c
@@ -0,0 +1,33 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "ntlog.h"
+#include "nthw_drv.h"
+#include "nthw_register.h"
+#include "nthw_fpga.h"
+#include "nthw_hif.h"
+#include "ntnic_mod_reg.h"
+
+static int nthw_fpga_rst_nt400dxx_init(struct fpga_info_s *p_fpga_info)
+{
+ assert(p_fpga_info);
+ return 0;
+}
+
+static int nthw_fpga_rst_nt400dxx_reset(struct fpga_info_s *p_fpga_info)
+{
+ assert(p_fpga_info);
+ return 0;
+}
+
+static struct rst_nt400dxx_ops rst_nt400dxx_ops = {
+ .nthw_fpga_rst_nt400dxx_init = nthw_fpga_rst_nt400dxx_init,
+ .nthw_fpga_rst_nt400dxx_reset = nthw_fpga_rst_nt400dxx_reset
+};
+
+void rst_nt400dxx_ops_init(void)
+{
+ register_rst_nt400dxx_ops(&rst_nt400dxx_ops);
+}
diff --git a/drivers/net/ntnic/ntnic_mod_reg.c b/drivers/net/ntnic/ntnic_mod_reg.c
index 598df08fb7..054b343fe7 100644
--- a/drivers/net/ntnic/ntnic_mod_reg.c
+++ b/drivers/net/ntnic/ntnic_mod_reg.c
@@ -178,6 +178,36 @@ void register_flow_backend_ops(const struct flow_backend_ops *ops)
flow_backend_ops = ops;
}
+static struct rst9574_ops *rst9574_ops;
+
+void register_rst9574_ops(struct rst9574_ops *ops)
+{
+ rst9574_ops = ops;
+}
+
+struct rst9574_ops *get_rst9574_ops(void)
+{
+ if (rst9574_ops == NULL)
+ rst9574_ops_init();
+
+ return rst9574_ops;
+}
+
+static struct rst_nt400dxx_ops *rst_nt400dxx_ops;
+
+void register_rst_nt400dxx_ops(struct rst_nt400dxx_ops *ops)
+{
+ rst_nt400dxx_ops = ops;
+}
+
+struct rst_nt400dxx_ops *get_rst_nt400dxx_ops(void)
+{
+ if (rst_nt400dxx_ops == NULL)
+ rst_nt400dxx_ops_init();
+
+ return rst_nt400dxx_ops;
+}
+
const struct flow_backend_ops *get_flow_backend_ops(void)
{
if (flow_backend_ops == NULL)
diff --git a/drivers/net/ntnic/ntnic_mod_reg.h b/drivers/net/ntnic/ntnic_mod_reg.h
index 3e84beaa62..9b3650da89 100644
--- a/drivers/net/ntnic/ntnic_mod_reg.h
+++ b/drivers/net/ntnic/ntnic_mod_reg.h
@@ -19,6 +19,7 @@
#include "nthw_drv.h"
#include "nt4ga_adapter.h"
#include "ntnic_nthw_fpga_rst_nt200a0x.h"
+#include "ntnic_nthw_fpga_rst_nt400dxx.h"
#include "ntnic_virt_queue.h"
#include "create_elements.h"
@@ -255,6 +256,26 @@ void register_rst9563_ops(struct rst9563_ops *ops);
struct rst9563_ops *get_rst9563_ops(void);
void rst9563_ops_init(void);
+struct rst9574_ops {
+ int (*nthw_fpga_rst9574_init)(struct fpga_info_s *p_fpga_info,
+ struct nthw_fpga_rst_nt400dxx *const p);
+ int (*nthw_fpga_rst9574_setup)(nthw_fpga_t *p_fpga,
+ struct nthw_fpga_rst_nt400dxx *const p);
+};
+
+void register_rst9574_ops(struct rst9574_ops *ops);
+struct rst9574_ops *get_rst9574_ops(void);
+void rst9574_ops_init(void);
+
+struct rst_nt400dxx_ops {
+ int (*nthw_fpga_rst_nt400dxx_init)(struct fpga_info_s *p_fpga_info);
+ int (*nthw_fpga_rst_nt400dxx_reset)(struct fpga_info_s *p_fpga_info);
+};
+
+void register_rst_nt400dxx_ops(struct rst_nt400dxx_ops *ops);
+struct rst_nt400dxx_ops *get_rst_nt400dxx_ops(void);
+void rst_nt400dxx_ops_init(void);
+
struct flow_backend_ops {
const struct flow_api_backend_ops *(*bin_flow_backend_init)(nthw_fpga_t *p_fpga,
void **be_dev);
--
2.45.0
next prev parent reply other threads:[~2025-02-20 22:05 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-20 22:03 [PATCH v1 00/32] add new adapter NT400D13 Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 01/32] net/ntnic: add link agx 100g Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 02/32] net/ntnic: add link state machine Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 03/32] net/ntnic: add rpf and gfg init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 04/32] net/ntnic: add agx setup for port Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 05/32] net/ntnic: add host loopback init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 06/32] net/ntnic: add line " Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 07/32] net/ntnic: add 100 gbps port init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 08/32] net/ntnic: add port post init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 09/32] net/ntnic: add nim low power API Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 10/32] net/ntnic: add link handling API Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 11/32] net/ntnic: add port init to the state machine Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 12/32] net/ntnic: add port disable API Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 13/32] net/ntnic: add minimal initialization new NIC NT400D13 Serhii Iliushyk
2025-02-20 22:03 ` Serhii Iliushyk [this message]
2025-02-20 22:03 ` [PATCH v1 15/32] net/ntnic: add FPGA modules and registers Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 16/32] net/ntnic: add setup for fpga reset Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 17/32] net/ntnic: add default reset setting for NT400D13 Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 18/32] net/ntnic: add DDR calibration to reset stage Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 19/32] net/ntnic: add PHY ftile reset Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 20/32] net/ntnic: add clock init Serhii Iliushyk
2025-03-05 17:03 ` David Marchand
2025-03-07 10:20 ` Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 21/32] net/ntnic: add nt400d13 pcm init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 22/32] net/ntnic: add HIF clock test Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 23/32] net/ntnic: add nt400d13 PRM module init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 24/32] net/ntnic: add nt400d13 PRM module reset Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 25/32] net/ntnic: add SPI v3 support for FPGA Serhii Iliushyk
2025-02-22 19:21 ` Stephen Hemminger
2025-02-20 22:03 ` [PATCH v1 26/32] net/ntnic: add i2cm init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 27/32] net/ntnic: add pca init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 28/32] net/ntnic: add pcal init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 29/32] net/ntnic: add reset PHY init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 30/32] net/ntnic: add igam module init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 31/32] net/ntnic: init IGAM and config PLL for FPGA Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 32/32] net/ntnic: revert untrusted loop bound Serhii Iliushyk
2025-02-20 22:31 ` Stephen Hemminger
2025-02-20 23:49 ` [PATCH v1 00/32] add new adapter NT400D13 Stephen Hemminger
2025-02-22 21:41 ` Stephen Hemminger
2025-04-11 10:36 ` Serhii Iliushyk
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250220220406.3925597-15-sil-plv@napatech.com \
--to=sil-plv@napatech.com \
--cc=ckm@napatech.com \
--cc=dev@dpdk.org \
--cc=mko-plv@napatech.com \
--cc=stephen@networkplumber.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.