[PATCH 00/10] clk: imx: Use Clock frameworkt to register UART clocks

[PATCH 00/10] clk: imx: Use Clock frameworkt to register UART clocks

[Adam Ford]

Currenty, most peripherals enable/disable their respecive clocks using
the clock framework, but serial ports various imx platsforms do not.  Some
of the newer NXP SoC's register the UART clocks, but they are not necessarily
associated the to serial_mxc driver, so these clocks need to be manually
enabled, and even when the driver model enumerates the UART, the driver model
doesn't always reflect the proper clock state beacause these clocks are not
controlled by the serial driver.

This series does a few things:

Register the missing UART clocks on imx6, 8mm, 8mn,
fixes a build dependency on CCF_FRAMEWORK on imx8mp in SPL,
bulk enables the UART clocks from the serial_mxc driver,
and finally, removes the manual references to enabling the
UART clocks on Beacon EmbeddedWorks imx8mm, imx8mn, and imx8mp
development kits.

I don't have access to an imx6 board right now, nor do I have imx9 or
imxrt boards, so I can't verify regressions on those platforms.

For users who want to try this series and remove the manual UART calls,
make sure the SoC clock driver is enabled in SPL and OF_SPL_REMOVE_PROPS
should not remove the clocks or clock names.

With this series both "clk dump" and "dm tree" show the UART clocks are
registred and the one clocking the console UART is enabled and running.

Adam Ford (10):
  clk: imx6q: Properly handle imx6qp ESPI clk_sels
  clk: imx6q: Register UART clocks
  clk: imx8mm: register UART clocks
  clk: imx8mn: register UART clocks
  serial: mxc: Support bulk enabling clocks
  board: beacon: imx8mm: Let clock system enable UART clock
  board: beacon: imx8mn: Let clock system enable UART clock
  clk: imx: select SPL_CLK_COMPOSITE_CCF when SPL_CLK_IMX8MP
  configs: imx8mp_beacon: Select SPL_CLK_IMX8MP
  board: beacon: imx8mp: Let clock system enable UART clock

 board/beacon/imx8mm/spl.c             |  6 +----
 board/beacon/imx8mn/spl.c             |  2 --
 board/beacon/imx8mp/spl.c             |  2 --
 configs/imx8mp_beacon_defconfig       |  1 +
 drivers/clk/imx/Kconfig               |  1 +
 drivers/clk/imx/clk-imx6q.c           | 34 ++++++++++++++++++++++++---
 drivers/clk/imx/clk-imx8mm.c          | 34 +++++++++++++++++++++++++++
 drivers/clk/imx/clk-imx8mn.c          | 32 +++++++++++++++++++++++++
 drivers/serial/serial_mxc.c           | 11 +++++++++
 include/dm/platform_data/serial_mxc.h |  1 +
 10 files changed, 112 insertions(+), 12 deletions(-)

---
V2: Fix name of "ECSPI" and elimiate helper function, and fix build error.


-- 
2.45.2

[PATCH V2 01/10] clk: imx6q: Properly handle imx6qp ECSPI clk_sels

[Adam Ford]

The ECSPI clock has the ability to select between pll3_60m and
osc on the imx6qp, where it's fixed on other variants.  Fix this
by adding using a helper function to determine SoC variant and
register the clock accordingly.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
---
 drivers/clk/imx/clk-imx6q.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

V2:  Fix the name "ECSPI" and elimiate helper function by
     directly calling of_machine_is_compatible.

diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index df9f0285e1e..15ad0c9ac06 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -35,6 +35,7 @@ static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
 static const char *const periph_sels[]	= { "periph_pre", "periph_clk2", };
 static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m",
 					       "pll2_pfd0_352m", "pll2_198m", };
+static const char *const ecspi_sels[] = { "pll3_60m", "osc", };
 
 static int imx6q_clk_probe(struct udevice *dev)
 {
@@ -78,6 +79,11 @@ static int imx6q_clk_probe(struct udevice *dev)
 	       imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 
+	if (of_machine_is_compatible("fsl,imx6qp")
+		clk_dm(IMX6QDL_CLK_ECSPI_SEL,
+		       imx_clk_mux("ecspi_sel",	base + 0x38, 18, 1, ecspi_sels,
+				   ARRAY_SIZE(ecspi_sels)));
+
 	clk_dm(IMX6QDL_CLK_USDHC1_PODF,
 	       imx_clk_divider("usdhc1_podf", "usdhc1_sel",
 			       base + 0x24, 11, 3));
@@ -91,8 +97,12 @@ static int imx6q_clk_probe(struct udevice *dev)
 	       imx_clk_divider("usdhc4_podf", "usdhc4_sel",
 			       base + 0x24, 22, 3));
 
-	clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
-	       imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
+	if (of_machine_is_compatible("fsl,imx6qp")
+		clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
+		       imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6));
+	else
+		clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
+		       imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
 
 	clk_dm(IMX6QDL_CLK_ECSPI1,
 	       imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
-- 
2.45.2

Re: [PATCH V2 01/10] clk: imx6q: Properly handle imx6qp ECSPI clk_sels

[Peng Fan]

On Tue, Mar 11, 2025 at 07:30:21PM -0500, Adam Ford wrote:
>The ECSPI clock has the ability to select between pll3_60m and
>osc on the imx6qp, where it's fixed on other variants.  Fix this
>by adding using a helper function to determine SoC variant and
>register the clock accordingly.
>
>Signed-off-by: Adam Ford <aford173@gmail.com>
>Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

[PATCH V2 02/10] clk: imx6q: Register UART clocks

[Adam Ford]

In order to use the driver model and clock system to enable UART
clocks from the serial driver, it's necessary to register the UART
clocks.  With the helper function to check for imx6qp vs other
variants, the UART can register for both scenarios.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
V2:  Directly call of_machine_is_compatible("fsl,imx6qp") instead of
     using a helper function
---
 drivers/clk/imx/clk-imx6q.c | 20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 15ad0c9ac06..a4295614016 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -35,6 +35,7 @@ static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
 static const char *const periph_sels[]	= { "periph_pre", "periph_clk2", };
 static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m",
 					       "pll2_pfd0_352m", "pll2_198m", };
+static const char *const uart_sels[] = { "pll3_80m", "osc", };
 static const char *const ecspi_sels[] = { "pll3_60m", "osc", };
 
 static int imx6q_clk_probe(struct udevice *dev)
@@ -79,10 +80,14 @@ static int imx6q_clk_probe(struct udevice *dev)
 	       imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 
-	if (of_machine_is_compatible("fsl,imx6qp")
+	if (of_machine_is_compatible("fsl,imx6qp") {
+		clk_dm(IMX6QDL_CLK_UART_SEL,
+		       imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels,
+				   ARRAY_SIZE(uart_sels)));
 		clk_dm(IMX6QDL_CLK_ECSPI_SEL,
 		       imx_clk_mux("ecspi_sel",	base + 0x38, 18, 1, ecspi_sels,
 				   ARRAY_SIZE(ecspi_sels)));
+	}
 
 	clk_dm(IMX6QDL_CLK_USDHC1_PODF,
 	       imx_clk_divider("usdhc1_podf", "usdhc1_sel",
@@ -97,12 +102,17 @@ static int imx6q_clk_probe(struct udevice *dev)
 	       imx_clk_divider("usdhc4_podf", "usdhc4_sel",
 			       base + 0x24, 22, 3));
 
-	if (of_machine_is_compatible("fsl,imx6qp")
+	if (of_machine_is_compatible("fsl,imx6qp") {
+		clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF,
+		       imx_clk_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6));
 		clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
 		       imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6));
-	else
+	} else {
+		clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF,
+		       imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6));
 		clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
 		       imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
+	}
 
 	clk_dm(IMX6QDL_CLK_ECSPI1,
 	       imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
@@ -112,6 +122,10 @@ static int imx6q_clk_probe(struct udevice *dev)
 	       imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4));
 	clk_dm(IMX6QDL_CLK_ECSPI4,
 	       imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6));
+	clk_dm(IMX6QDL_CLK_UART_IPG,
+	       imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24));
+	clk_dm(IMX6QDL_CLK_UART_SERIAL,
+	       imx_clk_gate2("uart_serial", "uart_serial_podf",  base + 0x7c, 26));
 	clk_dm(IMX6QDL_CLK_USDHC1,
 	       imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
 	clk_dm(IMX6QDL_CLK_USDHC2,
-- 
2.45.2

RE: [PATCH V2 02/10] clk: imx6q: Register UART clocks

[Peng Fan]

> Subject: [PATCH V2 02/10] clk: imx6q: Register UART clocks
> 
> In order to use the driver model and clock system to enable UART
> clocks from the serial driver, it's necessary to register the UART clocks.
> With the helper function to check for imx6qp vs other variants, the
> UART can register for both scenarios.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

[PATCH V2 03/10] clk: imx8mm: register UART clocks

[Adam Ford]

In order to let the serial driver enable the clocks, the UART clocks
must be registered first.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
 drivers/clk/imx/clk-imx8mm.c | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index bb6958f0ec2..378c07caba3 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -81,6 +81,22 @@ static const char * const imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m"
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
+static const char * const imx8mm_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+					  "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4",
+					  "audio_pll2_out", };
+
+static const char * const imx8mm_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+					  "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3",
+					  "audio_pll2_out", };
+
+static const char * const imx8mm_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+					  "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4",
+					  "audio_pll2_out", };
+
+static const char * const imx8mm_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+					  "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3",
+					  "audio_pll2_out", };
+
 #if CONFIG_IS_ENABLED(PCIE_DW_IMX)
 static const char * const imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m",
 						      "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m",
@@ -322,6 +338,24 @@ static int imx8mm_clk_probe(struct udevice *dev)
 	       imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
 	clk_dm(IMX8MM_CLK_I2C4,
 	       imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
+
+	clk_dm(IMX8MM_CLK_UART1,
+	       imx8m_clk_composite("uart1", imx8mm_uart1_sels, base + 0xaf00));
+	clk_dm(IMX8MM_CLK_UART2,
+	       imx8m_clk_composite("uart2", imx8mm_uart2_sels, base + 0xaf80));
+	clk_dm(IMX8MM_CLK_UART3,
+	       imx8m_clk_composite("uart3", imx8mm_uart3_sels, base + 0xb000));
+	clk_dm(IMX8MM_CLK_UART4,
+	       imx8m_clk_composite("uart4", imx8mm_uart4_sels, base + 0xb080));
+	clk_dm(IMX8MM_CLK_UART1_ROOT,
+	       imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
+	clk_dm(IMX8MM_CLK_UART2_ROOT,
+	       imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
+	clk_dm(IMX8MM_CLK_UART3_ROOT,
+	       imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
+	clk_dm(IMX8MM_CLK_UART4_ROOT,
+	       imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
+
 	clk_dm(IMX8MM_CLK_WDOG,
 	       imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
 	clk_dm(IMX8MM_CLK_USDHC3,
-- 
2.45.2

Re: [PATCH V2 03/10] clk: imx8mm: register UART clocks

[Peng Fan]

On Tue, Mar 11, 2025 at 07:30:23PM -0500, Adam Ford wrote:
>In order to let the serial driver enable the clocks, the UART clocks
>must be registered first.
>
>Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

[PATCH V2 04/10] clk: imx8mn: register UART clocks

[Adam Ford]

In order to let the serial driver enable the clocks, the UART clocks
must be registered first.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
 drivers/clk/imx/clk-imx8mn.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index be15ebd0e25..54ae887817a 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -97,6 +97,22 @@ static const char * const imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m"
 						"sys_pll3_out", "audio_pll1_out", "video_pll_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
+static const char * const imx8mn_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+						 "clk_ext4", "audio_pll2_out", };
+
+static const char * const imx8mn_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+						 "clk_ext3", "audio_pll2_out", };
+
+static const char * const imx8mn_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+						 "clk_ext4", "audio_pll2_out", };
+
+static const char * const imx8mn_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+						 "clk_ext3", "audio_pll2_out", };
+
 #ifndef CONFIG_XPL_BUILD
 static const char * const imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
@@ -311,6 +327,14 @@ static int imx8mn_clk_probe(struct udevice *dev)
 	       imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
 	clk_dm(IMX8MN_CLK_I2C4,
 	       imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
+	clk_dm(IMX8MN_CLK_UART1,
+	       imx8m_clk_composite("uart1", imx8mn_uart1_sels, base + 0xaf00));
+	clk_dm(IMX8MN_CLK_UART2,
+	       imx8m_clk_composite("uart2", imx8mn_uart2_sels, base + 0xaf80));
+	clk_dm(IMX8MN_CLK_UART3,
+	       imx8m_clk_composite("uart3", imx8mn_uart3_sels, base + 0xb000));
+	clk_dm(IMX8MN_CLK_UART4,
+	       imx8m_clk_composite("uart4", imx8mn_uart4_sels, base + 0xb080));
 	clk_dm(IMX8MN_CLK_WDOG,
 	       imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
 	clk_dm(IMX8MN_CLK_USDHC3,
@@ -355,6 +379,14 @@ static int imx8mn_clk_probe(struct udevice *dev)
 	       imx_clk_gate2_shared2("nand_usdhc_rawnand_clk",
 				     "nand_usdhc_bus", base + 0x4300, 0,
 				     &share_count_nand));
+	clk_dm(IMX8MN_CLK_UART1_ROOT,
+	       imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
+	clk_dm(IMX8MN_CLK_UART2_ROOT,
+	       imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
+	clk_dm(IMX8MN_CLK_UART3_ROOT,
+	       imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
+	clk_dm(IMX8MN_CLK_UART4_ROOT,
+	       imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
 	clk_dm(IMX8MN_CLK_USB1_CTRL_ROOT,
 		imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
 
-- 
2.45.2

Re: [PATCH V2 04/10] clk: imx8mn: register UART clocks

[Peng Fan]

On Tue, Mar 11, 2025 at 07:30:24PM -0500, Adam Ford wrote:
>In order to let the serial driver enable the clocks, the UART clocks
>must be registered first.
>
>Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

[PATCH V2 05/10] serial: mxc: Support bulk enabling clocks

[Adam Ford]

Depending on the platform, there may be multiple clock sources
required to enable a UART.  Use the bulk functions to get and
enable the clocks when the UART probes.  This can facilitate
the removal of functions to manually enable the clock.

This is made dependent on CLK_CCF which is used on imx6q,
imx8m[mnqp], several imxrt, imx9.  If/when the UART clock
registration is done for older boards, this limitation
could be updated.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
 drivers/serial/serial_mxc.c           | 11 +++++++++++
 include/dm/platform_data/serial_mxc.h |  1 +
 2 files changed, 12 insertions(+)
 
 V2:  Fix build issue when built without CLK_CCF

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index c5fd740be4d..28f4435d01d 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -3,6 +3,7 @@
  * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
  */
 
+#include <clk.h>
 #include <dm.h>
 #include <errno.h>
 #include <watchdog.h>
@@ -312,7 +313,17 @@ int mxc_serial_setbrg(struct udevice *dev, int baudrate)
 static int mxc_serial_probe(struct udevice *dev)
 {
 	struct mxc_serial_plat *plat = dev_get_plat(dev);
+#if CONFIG_IS_ENABLED(CLK_CCF)
+	int ret;
 
+	ret = clk_get_bulk(dev, &plat->clks);
+	if (ret)
+		return ret;
+
+	ret = clk_enable_bulk(&plat->clks);
+	if (ret)
+		return ret;
+#endif
 	_mxc_serial_init(plat->reg, plat->use_dte);
 
 	return 0;
diff --git a/include/dm/platform_data/serial_mxc.h b/include/dm/platform_data/serial_mxc.h
index cc59eeb1dd1..6f607b987ef 100644
--- a/include/dm/platform_data/serial_mxc.h
+++ b/include/dm/platform_data/serial_mxc.h
@@ -9,6 +9,7 @@
 /* Information about a serial port */
 struct mxc_serial_plat {
 	struct mxc_uart *reg;  /* address of registers in physical memory */
+	struct clk_bulk clks;
 	bool use_dte;
 };
 
-- 
2.45.2

Re: [PATCH V2 05/10] serial: mxc: Support bulk enabling clocks

[Peng Fan]

On Tue, Mar 11, 2025 at 07:30:25PM -0500, Adam Ford wrote:
>Depending on the platform, there may be multiple clock sources
>required to enable a UART.  Use the bulk functions to get and
>enable the clocks when the UART probes.  This can facilitate
>the removal of functions to manually enable the clock.
>
>This is made dependent on CLK_CCF which is used on imx6q,
>imx8m[mnqp], several imxrt, imx9.  If/when the UART clock
>registration is done for older boards, this limitation
>could be updated.
>
>Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

[PATCH V2 06/10] board: beacon: imx8mm: Let clock system enable UART clock

[Adam Ford]

Now that the UART driver can enable the required clocks, remove
the hard-coded clock enable.  This requires a small re-order
of a couple functions.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
 board/beacon/imx8mm/spl.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
index 12013aa5a4d..93ee5b7ee0c 100644
--- a/board/beacon/imx8mm/spl.c
+++ b/board/beacon/imx8mm/spl.c
@@ -100,9 +100,6 @@ void board_init_f(ulong dummy)
 	int ret;
 
 	arch_cpu_init();
-
-	init_uart_clk(1);
-
 	timer_init();
 
 	/* Clear the BSS. */
@@ -114,8 +111,6 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 
-	preloader_console_init();
-
 	ret = uclass_get_device_by_name(UCLASS_CLK,
 					"clock-controller@30380000",
 					&dev);
@@ -124,6 +119,7 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 
+	preloader_console_init();
 	enable_tzc380();
 
 	power_init_board();
-- 
2.45.2

Re: [PATCH V2 06/10] board: beacon: imx8mm: Let clock system enable UART clock

[Peng Fan]

On Tue, Mar 11, 2025 at 07:30:26PM -0500, Adam Ford wrote:
>Now that the UART driver can enable the required clocks, remove
>the hard-coded clock enable.  This requires a small re-order
>of a couple functions.
>
>Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

[PATCH V2 07/10] board: beacon: imx8mn: Let clock system enable UART clock

[Adam Ford]

Now that the UART driver can enable the required clocks, remove
the hard-coded clock enable.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
 board/beacon/imx8mn/spl.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c
index f03841e5a01..e91d3fdcf5e 100644
--- a/board/beacon/imx8mn/spl.c
+++ b/board/beacon/imx8mn/spl.c
@@ -111,8 +111,6 @@ int board_early_init_f(void)
 	/* Claiming pwm pins prevents LCD flicker during startup*/
 	imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
 
-	init_uart_clk(1);
-
 	return 0;
 }
 
-- 
2.45.2

Re: [PATCH V2 07/10] board: beacon: imx8mn: Let clock system enable UART clock

[Peng Fan]

On Tue, Mar 11, 2025 at 07:30:27PM -0500, Adam Ford wrote:
>Now that the UART driver can enable the required clocks, remove
>the hard-coded clock enable.
>
>Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

[PATCH V2 08/10] clk: imx: select SPL_CLK_COMPOSITE_CCF when SPL_CLK_IMX8MP

[Adam Ford]

If SPL_CLK_IMX8MP is selected alone, it causes a build error.
The clock composite is required when using the clock framework, so
select it when SPL_CLK_IMX8MP is enabled.  This is already being
done outside of SPL.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
 drivers/clk/imx/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 56d893e0579..d17a54fb9b3 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -60,6 +60,7 @@ config SPL_CLK_IMX8MP
 	depends on ARCH_IMX8M && SPL
 	select SPL_CLK
 	select SPL_CLK_CCF
+	select SPL_CLK_COMPOSITE_CCF
 	help
 	  This enables SPL DM/DTS support for clock driver in i.MX8MP
 
-- 
2.45.2

Re: [PATCH V2 08/10] clk: imx: select SPL_CLK_COMPOSITE_CCF when SPL_CLK_IMX8MP

[Peng Fan]

On Tue, Mar 11, 2025 at 07:30:28PM -0500, Adam Ford wrote:
>If SPL_CLK_IMX8MP is selected alone, it causes a build error.
>The clock composite is required when using the clock framework, so
>select it when SPL_CLK_IMX8MP is enabled.  This is already being
>done outside of SPL.
>
>Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

[PATCH V2 09/10] configs: imx8mp_beacon: Select SPL_CLK_IMX8MP

[Adam Ford]

In preparation to remove manual references for enabling some clocks,
enable SPL_CLK_IMX8MP which automatically enables SPL_CCF and
SPL_CLK_COMPOSITE_CCF which permit various drivers to activate
their respective clocks automatically.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
 configs/imx8mp_beacon_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig
index f39e4f5dd28..9709f628f9c 100644
--- a/configs/imx8mp_beacon_defconfig
+++ b/configs/imx8mp_beacon_defconfig
@@ -86,6 +86,7 @@ CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="eth1"
 CONFIG_SPL_DM=y
 CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
 CONFIG_CLK_IMX8MP=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x42800000
-- 
2.45.2

Re: [PATCH V2 09/10] configs: imx8mp_beacon: Select SPL_CLK_IMX8MP

[Peng Fan]

On Tue, Mar 11, 2025 at 07:30:29PM -0500, Adam Ford wrote:
>In preparation to remove manual references for enabling some clocks,
>enable SPL_CLK_IMX8MP which automatically enables SPL_CCF and
>SPL_CLK_COMPOSITE_CCF which permit various drivers to activate
>their respective clocks automatically.
>
>Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

[PATCH V2 10/10] board: beacon: imx8mp: Let clock system enable UART clock

[Adam Ford]

Now that the UART driver can enable the required clocks, remove
the hard-coded clock enable.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
 board/beacon/imx8mp/spl.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/board/beacon/imx8mp/spl.c b/board/beacon/imx8mp/spl.c
index 30d577f7e0e..6b357d90a3f 100644
--- a/board/beacon/imx8mp/spl.c
+++ b/board/beacon/imx8mp/spl.c
@@ -112,8 +112,6 @@ void board_init_f(ulong dummy)
 
 	arch_cpu_init();
 
-	init_uart_clk(1);
-
 	ret = spl_early_init();
 	if (ret) {
 		debug("spl_init() failed: %d\n", ret);
-- 
2.45.2

Re: [PATCH V2 10/10] board: beacon: imx8mp: Let clock system enable UART clock

[Peng Fan]

On Tue, Mar 11, 2025 at 07:30:30PM -0500, Adam Ford wrote:
>Now that the UART driver can enable the required clocks, remove
>the hard-coded clock enable.
>
>Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

Re: [PATCH 00/10] clk: imx: Use Clock frameworkt to register UART clocks

[Fabio Estevam]

On Tue, Mar 11, 2025 at 9:31 PM Adam Ford <aford173@gmail.com> wrote:

> ---
> V2: Fix name of "ECSPI" and elimiate helper function, and fix build error.

Still get errors in CI:

https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/1057306

Please make sure v3 passes CI.

+In file included from board/liebherr/display5/display5.c:30:
3873+include/dm/platform_data/serial_mxc.h:12:25: error: field 'clks'
has incomplete type
3874+ 12 | struct clk_bulk clks;
3875+ | ^~~~
3876+make[2]: *** [scripts/Makefile.build:257:
board/liebherr/display5/display5.o] Error 1
3877+make[1]: *** [Makefile:1917: board/liebherr/display5] Error 2
3878+make: *** [Makefile:177: sub-make] Error 2
3879 arm: + kp_imx6q_tpc
3880+drivers/clk/imx/clk-imx6q.c: In function 'imx6q_clk_probe':
3881+drivers/clk/imx/clk-imx6q.c:83:51: error: expected ')' before '{' token
3882+ 83 | if (of_machine_is_compatible("fsl,imx6qp") {
3883+ | ~ ^~
3884+ | )
3885+drivers/clk/imx/clk-imx6q.c:83:9: note:
'-Wmisleading-indentation' is disabled from this point onwards, since
column-tracking was disabled due to the size of the code/headers
3886+ | ^~
3887+drivers/clk/imx/clk-imx6q.c:83:9: note: adding
'-flarge-source-files' will allow for more column-tracking support, at
the expense of compilation time and memory
3888+drivers/clk/imx/clk-imx6q.c:179:1: error: expected declaration or
statement at end of input
3889+ 179 | };
3890+ | ^
3891+drivers/clk/imx/clk-imx6q.c: At top level:
3892+drivers/clk/imx/clk-imx6q.c:41:12: error: 'imx6q_clk_probe'
defined but not used [-Werror=unused-function]
3893+ 41 | static int imx6q_clk_probe(struct udevice *dev)
3894+ | ^~~~~~~~~~~~~~~
3895+drivers/clk/imx/clk-imx6q.c:39:26: error: 'ecspi_sels' defined
but not used [-Werror=unused-const-variable=]
3896+ 39 | static const char *const ecspi_sels[] = { "pll3_60m", "osc", };
3897+ | ^~~~~~~~~~
3898+drivers/clk/imx/clk-imx6q.c:38:26: error: 'uart_sels' defined but
not used [-Werror=unused-const-variable=]
3899+ 38 | static const char *const uart_sels[] = { "pll3_80m", "osc", };
3900+ | ^~~~~~~~~
3901+drivers/clk/imx/clk-imx6q.c:36:26: error: 'periph_pre_sels'
defined but not used [-Werror=unused-const-variable=]
3902+ 36 | static const char *const periph_pre_sels[] = { "pll2_bus",
"pll2_pfd2_396m",
3903+ | ^~~~~~~~~~~~~~~
3904+drivers/clk/imx/clk-imx6q.c:35:26: error: 'periph_sels' defined
but not used [-Werror=unused-const-variable=]
3905+ 35 | static const char *const periph_sels[] = { "periph_pre",
"periph_clk2", };
3906+ | ^~~~~~~~~~~
3907+drivers/clk/imx/clk-imx6q.c:26:23: error: 'imx6q_clk_ops' defined
but not used [-Werror=unused-variable]
3908+ 26 | static struct clk_ops imx6q_clk_ops = {
3909+ | ^~~~~~~~~~~~~
3910+cc1: all warnings being treated as errors
3911+make[4]: *** [scripts/Makefile.build:257:
drivers/clk/imx/clk-imx6q.o] Error 1
3912+make[3]: *** [scripts/Makefile.build:398: drivers/clk/imx] Error 2
3913+make[2]: *** [scripts/Makefile.build:398: drivers/clk] Error 2
3914+make[1]: *** [Makefile:1917: drivers] Error 2
3915+make: *** [Makefile:177: sub-make] Error 2

Re: [PATCH 00/10] clk: imx: Use Clock frameworkt to register UART clocks

[Adam Ford]

On Tue, Mar 11, 2025 at 9:31 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> On Tue, Mar 11, 2025 at 9:31 PM Adam Ford <aford173@gmail.com> wrote:
>
> > ---
> > V2: Fix name of "ECSPI" and elimiate helper function, and fix build error.
>
> Still get errors in CI:
>
> https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/1057306
>
> Please make sure v3 passes CI.

I ran the config that failed on my V3, and it passes that build test,
but I don't want to waste your time if it fails on others I don't know
about.  Can you point me to documentation on how to test this across
multiple boards/platforms before I resubmit it?

adam
>
> +In file included from board/liebherr/display5/display5.c:30:
> 3873+include/dm/platform_data/serial_mxc.h:12:25: error: field 'clks'
> has incomplete type
> 3874+ 12 | struct clk_bulk clks;
> 3875+ | ^~~~
> 3876+make[2]: *** [scripts/Makefile.build:257:
> board/liebherr/display5/display5.o] Error 1
> 3877+make[1]: *** [Makefile:1917: board/liebherr/display5] Error 2
> 3878+make: *** [Makefile:177: sub-make] Error 2
> 3879 arm: + kp_imx6q_tpc
> 3880+drivers/clk/imx/clk-imx6q.c: In function 'imx6q_clk_probe':
> 3881+drivers/clk/imx/clk-imx6q.c:83:51: error: expected ')' before '{' token
> 3882+ 83 | if (of_machine_is_compatible("fsl,imx6qp") {
> 3883+ | ~ ^~
> 3884+ | )
> 3885+drivers/clk/imx/clk-imx6q.c:83:9: note:
> '-Wmisleading-indentation' is disabled from this point onwards, since
> column-tracking was disabled due to the size of the code/headers
> 3886+ | ^~
> 3887+drivers/clk/imx/clk-imx6q.c:83:9: note: adding
> '-flarge-source-files' will allow for more column-tracking support, at
> the expense of compilation time and memory
> 3888+drivers/clk/imx/clk-imx6q.c:179:1: error: expected declaration or
> statement at end of input
> 3889+ 179 | };
> 3890+ | ^
> 3891+drivers/clk/imx/clk-imx6q.c: At top level:
> 3892+drivers/clk/imx/clk-imx6q.c:41:12: error: 'imx6q_clk_probe'
> defined but not used [-Werror=unused-function]
> 3893+ 41 | static int imx6q_clk_probe(struct udevice *dev)
> 3894+ | ^~~~~~~~~~~~~~~
> 3895+drivers/clk/imx/clk-imx6q.c:39:26: error: 'ecspi_sels' defined
> but not used [-Werror=unused-const-variable=]
> 3896+ 39 | static const char *const ecspi_sels[] = { "pll3_60m", "osc", };
> 3897+ | ^~~~~~~~~~
> 3898+drivers/clk/imx/clk-imx6q.c:38:26: error: 'uart_sels' defined but
> not used [-Werror=unused-const-variable=]
> 3899+ 38 | static const char *const uart_sels[] = { "pll3_80m", "osc", };
> 3900+ | ^~~~~~~~~
> 3901+drivers/clk/imx/clk-imx6q.c:36:26: error: 'periph_pre_sels'
> defined but not used [-Werror=unused-const-variable=]
> 3902+ 36 | static const char *const periph_pre_sels[] = { "pll2_bus",
> "pll2_pfd2_396m",
> 3903+ | ^~~~~~~~~~~~~~~
> 3904+drivers/clk/imx/clk-imx6q.c:35:26: error: 'periph_sels' defined
> but not used [-Werror=unused-const-variable=]
> 3905+ 35 | static const char *const periph_sels[] = { "periph_pre",
> "periph_clk2", };
> 3906+ | ^~~~~~~~~~~
> 3907+drivers/clk/imx/clk-imx6q.c:26:23: error: 'imx6q_clk_ops' defined
> but not used [-Werror=unused-variable]
> 3908+ 26 | static struct clk_ops imx6q_clk_ops = {
> 3909+ | ^~~~~~~~~~~~~
> 3910+cc1: all warnings being treated as errors
> 3911+make[4]: *** [scripts/Makefile.build:257:
> drivers/clk/imx/clk-imx6q.o] Error 1
> 3912+make[3]: *** [scripts/Makefile.build:398: drivers/clk/imx] Error 2
> 3913+make[2]: *** [scripts/Makefile.build:398: drivers/clk] Error 2
> 3914+make[1]: *** [Makefile:1917: drivers] Error 2
> 3915+make: *** [Makefile:177: sub-make] Error 2

Re: [PATCH 00/10] clk: imx: Use Clock frameworkt to register UART clocks

[Fabio Estevam]

Hi Adam,

On Sat, Mar 15, 2025 at 12:37 PM Adam Ford <aford173@gmail.com> wrote:

> I ran the config that failed on my V3, and it passes that build test,
> but I don't want to waste your time if it fails on others I don't know
> about.  Can you point me to documentation on how to test this across
> multiple boards/platforms before I resubmit it?

Please check doc/develop/ci_testing.rst

"The second way is to use GitHub.  This requires a GitHub account
and to fork the repository at https://github.com/u-boot/u-boot and to then
submit a pull request as this will trigger an Azure pipeline run.  Clicking on
your pull request on the list at https://github.com/u-boot/u-boot/pulls and
then the "Checks" tab will show the results."

Re: [PATCH 00/10] clk: imx: Use Clock frameworkt to register UART clocks

[Adam Ford]

On Sat, Mar 15, 2025 at 11:17 AM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Adam,
>
> On Sat, Mar 15, 2025 at 12:37 PM Adam Ford <aford173@gmail.com> wrote:
>
> > I ran the config that failed on my V3, and it passes that build test,
> > but I don't want to waste your time if it fails on others I don't know
> > about.  Can you point me to documentation on how to test this across
> > multiple boards/platforms before I resubmit it?
>
> Please check doc/develop/ci_testing.rst
>
> "The second way is to use GitHub.  This requires a GitHub account
> and to fork the repository at https://github.com/u-boot/u-boot and to then
> submit a pull request as this will trigger an Azure pipeline run.  Clicking on
> your pull request on the list at https://github.com/u-boot/u-boot/pulls and
> then the "Checks" tab will show the results."

The doc you referred me to states:  Currently, we support running
GitLab CI pipelines only for custodians, due to the resources the
project has available

I tried pushing my branch to Github, but I don't have permission.  I
tried pushing it to my own github account, but it doesn't appear the
CI/CD stuff work.  I looked at the log provided from the pipeline, and
I have been able to successfully build for that machine along with a
couple others that I have manually tested.  Are you OK if I submit, or
is there something you want me to try before I do it?  I have a second
series I would like to submit soon which reduce my SPL size when
enabling CLK and CCF from:

   text    data     bss     dec     hex filename
  95988   22668      80 118736   1cfd0 spl/u-boot-spl
to
  91898   22668      80 114646   1bfd6 spl/u-boot-spl

It requires this series in order to accomplish some of these goals.

adam

Re: [PATCH 00/10] clk: imx: Use Clock frameworkt to register UART clocks

[Fabio Estevam]

On Sun, Mar 16, 2025 at 7:18 PM Adam Ford <aford173@gmail.com> wrote:

> The doc you referred me to states:  Currently, we support running
> GitLab CI pipelines only for custodians, due to the resources the
> project has available

Correct, so you should use the Github method.

> I tried pushing my branch to Github, but I don't have permission.  I
> tried pushing it to my own github account, but it doesn't appear the
> CI/CD stuff work.  I looked at the log provided from the pipeline, and

You should clone U-Boot into your local Github repo. Push your series
into your repo and then create a pull request at:
https://github.com/u-boot/u-boot/pulls

Not sure about the problem you got.

> I have been able to successfully build for that machine along with a
> couple others that I have manually tested.  Are you OK if I submit, or
> is there something you want me to try before I do it?  I have a second

Feel free to post your updated series and I'll get it to run through CI.