From: Uma Shankar <uma.shankar@intel.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, harry.wentland@amd.com,
pekka.paalanen@haloniitty.fi, sebastian.wick@redhat.com,
jadahl@redhat.com, mwen@igalia.com, contact@emersion.fr,
naveen1.kumar@intel.com,
Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>,
Uma Shankar <uma.shankar@intel.com>
Subject: [v4 11/23] drm/i915/color: Create a transfer function color pipeline
Date: Wed, 12 Mar 2025 12:54:13 +0530 [thread overview]
Message-ID: <20250312072425.3099205-12-uma.shankar@intel.com> (raw)
In-Reply-To: <20250312072425.3099205-1-uma.shankar@intel.com>
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add a color pipeline with three colorops in the sequence
1D LUT MULTSEG - CTM - 1D LUT MULTSEG
This pipeline can be used to do any color space conversion or HDR
tone mapping
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 175 +++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_color.h | 3 +
2 files changed, 178 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 615f7bb9dc09..f86754cfbfef 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -30,6 +30,7 @@
#include "intel_display_types.h"
#include "intel_dsb.h"
#include "intel_vrr.h"
+#include "skl_universal_plane.h"
struct intel_color_funcs {
int (*color_check)(struct intel_atomic_state *state,
@@ -3937,6 +3938,139 @@ static const struct intel_color_funcs ilk_color_funcs = {
.get_config = ilk_get_config,
};
+static const struct drm_color_lut_range xelpd_degamma_hdr[] = {
+ /* segment 1 */
+ {
+ .flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+ DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+ DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+ DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+ .count = 128,
+ .start = 0, .end = (1 << 24) - 1,
+ .norm_factor = (1 << 24),
+ .precision = {
+ .intp = 0,
+ .fracp = 24,
+ },
+ },
+ /* segment 2 */
+ {
+ .flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+ DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+ DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+ DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+ .count = 1,
+ .start = (1 << 24), .end = (1 << 24),
+ .norm_factor = (1 << 24),
+ .precision = {
+ .intp = 3,
+ .fracp = 24,
+ },
+ },
+ /* Segment 3 */
+ {
+ .flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+ DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+ DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+ DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+ .count = 1,
+ .start = 3 * (1 << 24), .end = 3 * (1 << 24),
+ .norm_factor = (1 << 24),
+ .precision = {
+ .intp = 3,
+ .fracp = 24,
+ },
+ },
+ /* Segment 4 */
+ {
+ .flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+ DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+ DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+ DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+ .count = 1,
+ .start = 7 * (1 << 24), .end = 7 * (1 << 24),
+ .norm_factor = (1 << 24),
+ .precision = {
+ .intp = 3,
+ .fracp = 24,
+ },
+ }
+};
+
+/* FIXME input bpc? */
+static const struct drm_color_lut_range xelpd_gamma_hdr[] = {
+ /* segment 1 */
+ {
+ .flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+ DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+ DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+ DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+ .count = 9,
+ .start = 0, .end = 8,
+ .norm_factor = 8 * 32,
+ .precision = {
+ .intp = 0,
+ .fracp = 24,
+ },
+ },
+ /* segment 2 */
+ {
+ .flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+ DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+ DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+ DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+ .count = 30,
+ .start = 8 * 2, .end = 8 * (32 - 1),
+ .norm_factor = 8 * 32,
+ .precision = {
+ .intp = 0,
+ .fracp = 24,
+ },
+ },
+ /* segment 3 */
+ {
+ .flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+ DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+ DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+ DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+ .count = 1,
+ .start = 8 * 32, .end = 8 * 32,
+ .norm_factor = 8 * 32,
+ .precision = {
+ .intp = 3,
+ .fracp = 24,
+ },
+ },
+ /* segment 4 */
+ {
+ .flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+ DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+ DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+ DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+ .count = 1,
+ .start = 3 * 8 * 32, .end = 3 * 8 * 32,
+ .norm_factor = 8 * 32,
+ .precision = {
+ .intp = 3,
+ .fracp = 24,
+ },
+ },
+ /* segment 5 */
+ {
+ .flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+ DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+ DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+ DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+ .count = 1,
+ .start = 7 * 8 * 32, .end = 7 * 8 * 32,
+ .norm_factor = 8 * 32,
+ .precision = {
+ .intp = 3,
+ .fracp = 24,
+ },
+ },
+};
+
/* TODO: Move to another file */
struct intel_plane_colorop *intel_colorop_alloc(void)
{
@@ -3976,6 +4110,47 @@ struct intel_plane_colorop *intel_plane_colorop_create(enum intel_color_block id
return colorop;
}
+int intel_plane_tf_pipeline_init(struct drm_plane *plane, struct drm_prop_enum_list *list)
+{
+ struct intel_plane_colorop *colorop;
+ struct drm_device *dev = plane->dev;
+ int ret;
+ struct drm_colorop *prev_op;
+
+ colorop = intel_plane_colorop_create(CB_PLANE_PRE_CSC_LUT);
+
+ ret = drm_colorop_curve_1d_lut_multseg_init(dev, &colorop->base,
+ plane, xelpd_degamma_hdr,
+ sizeof(xelpd_degamma_hdr), true);
+ if (ret)
+ return ret;
+
+ list->type = colorop->base.base.id;
+ list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d", colorop->base.base.id);
+
+ /* TODO: handle failures and clean up*/
+ prev_op = &colorop->base;
+
+ colorop = intel_plane_colorop_create(CB_PLANE_CSC);
+ ret = drm_colorop_ctm_3x3_init(dev, &colorop->base, plane, true);
+ if (ret)
+ return ret;
+
+ drm_colorop_set_next_property(prev_op, &colorop->base);
+ prev_op = &colorop->base;
+
+ colorop = intel_plane_colorop_create(CB_PLANE_POST_CSC_LUT);
+ ret = drm_colorop_curve_1d_lut_multseg_init(dev, &colorop->base,
+ plane, xelpd_gamma_hdr,
+ sizeof(xelpd_gamma_hdr), true);
+ if (ret)
+ return ret;
+
+ drm_colorop_set_next_property(prev_op, &colorop->base);
+
+ return 0;
+}
+
void intel_color_crtc_init(struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h
index a9f229e37317..abbc41d730a9 100644
--- a/drivers/gpu/drm/i915/display/intel_color.h
+++ b/drivers/gpu/drm/i915/display/intel_color.h
@@ -14,6 +14,8 @@ struct intel_crtc;
struct intel_display;
struct intel_dsb;
struct drm_property_blob;
+struct drm_plane;
+struct drm_prop_enum_list;
enum intel_color_block;
void intel_color_init_hooks(struct intel_display *display);
@@ -41,5 +43,6 @@ bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,
void intel_color_assert_luts(const struct intel_crtc_state *crtc_state);
struct intel_plane_colorop *intel_colorop_alloc(void);
struct intel_plane_colorop *intel_plane_colorop_create(enum intel_color_block id);
+int intel_plane_tf_pipeline_init(struct drm_plane *plane, struct drm_prop_enum_list *list);
#endif /* __INTEL_COLOR_H__ */
--
2.42.0
next prev parent reply other threads:[~2025-03-12 7:13 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-12 7:24 [v4 00/23] Plane Color Pipeline support for Intel platforms Uma Shankar
2025-03-12 7:24 ` [NOT FOR REVIEW] [v4 01/23] drm: color pipeline base work Uma Shankar
2025-03-12 7:24 ` [v4 02/23] drm: Add support for 3x3 CTM Uma Shankar
2025-03-12 7:24 ` [v4 03/23] drm: Add Enhanced LUT precision structure Uma Shankar
2025-03-12 7:24 ` [v4 04/23] drm: Add Color lut range attributes Uma Shankar
2025-03-12 7:24 ` [v4 05/23] drm: Add Color ops capability property Uma Shankar
2025-03-12 7:24 ` [v4 06/23] drm: Add 1D LUT multi-segmented color op Uma Shankar
2025-03-12 7:24 ` [v4 07/23] drm: Define helper to initialize segmented 1D LUT Uma Shankar
2025-03-12 7:24 ` [v4 08/23] drm/i915: Add identifiers for intel color blocks Uma Shankar
2025-03-12 7:24 ` [v4 09/23] drm/i915: Add intel_color_op Uma Shankar
2025-03-12 7:24 ` [v4 10/23] drm/i915/color: Add helper to create intel colorop Uma Shankar
2025-03-12 7:24 ` Uma Shankar [this message]
2025-03-12 7:24 ` [v4 12/23] drm/i915/color: Add and attach COLORPIPELINE plane property Uma Shankar
2025-03-12 7:24 ` [v4 13/23] drm/i915/color: Add framework to set colorop Uma Shankar
2025-03-12 7:24 ` [v4 14/23] drm/i915/color: Add callbacks to set plane CTM Uma Shankar
2025-03-12 7:24 ` [v4 15/23] drm/i915/color: Add new color callbacks for Xelpd Uma Shankar
2025-03-12 7:24 ` [v4 16/23] drm/i915/color: Add plane CTM callback for D13 and beyond Uma Shankar
2025-03-12 7:24 ` [v4 17/23] drm/i915: Add register definitions for Plane Degamma Uma Shankar
2025-03-12 7:24 ` [v4 18/23] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
2025-03-12 7:24 ` [v4 19/23] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
2025-03-12 7:24 ` [v4 20/23] drm/i915/color: Program Pre-CSC registers Uma Shankar
2025-03-12 7:24 ` [v4 21/23] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
2025-03-12 7:24 ` [v4 22/23] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
2025-03-12 7:24 ` [v4 23/23] drm/doc/rfc: Add documentation for multi-segmented 1D LUT Uma Shankar
2025-03-12 7:56 ` ✗ Fi.CI.CHECKPATCH: warning for Plane Color Pipeline support for Intel platforms (rev4) Patchwork
2025-03-12 7:56 ` ✗ Fi.CI.SPARSE: " Patchwork
2025-03-12 8:53 ` ✓ i915.CI.BAT: success " Patchwork
2025-03-13 6:19 ` ✓ CI.Patch_applied: success for Plane Color Pipeline support for Intel platforms (rev3) Patchwork
2025-03-13 6:19 ` ✗ CI.checkpatch: warning " Patchwork
2025-03-13 6:21 ` ✓ CI.KUnit: success " Patchwork
2025-03-13 6:37 ` ✓ CI.Build: " Patchwork
2025-03-13 6:39 ` ✗ CI.Hooks: failure " Patchwork
2025-03-13 6:41 ` ✗ CI.checksparse: warning " Patchwork
2025-03-13 7:11 ` ✓ Xe.CI.BAT: success " Patchwork
2025-03-14 13:03 ` ✗ Xe.CI.Full: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250312072425.3099205-12-uma.shankar@intel.com \
--to=uma.shankar@intel.com \
--cc=chaitanya.kumar.borah@intel.com \
--cc=contact@emersion.fr \
--cc=dri-devel@lists.freedesktop.org \
--cc=harry.wentland@amd.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
--cc=jadahl@redhat.com \
--cc=mwen@igalia.com \
--cc=naveen1.kumar@intel.com \
--cc=pekka.paalanen@haloniitty.fi \
--cc=sebastian.wick@redhat.com \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.