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From: Uma Shankar <uma.shankar@intel.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, harry.wentland@amd.com,
	pekka.paalanen@haloniitty.fi, sebastian.wick@redhat.com,
	jadahl@redhat.com, mwen@igalia.com, contact@emersion.fr,
	naveen1.kumar@intel.com, Uma Shankar <uma.shankar@intel.com>
Subject: [v4 17/23] drm/i915: Add register definitions for Plane Degamma
Date: Wed, 12 Mar 2025 12:54:19 +0530	[thread overview]
Message-ID: <20250312072425.3099205-18-uma.shankar@intel.com> (raw)
In-Reply-To: <20250312072425.3099205-1-uma.shankar@intel.com>

Add macros to define Plane Degamma registers

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 .../i915/display/skl_universal_plane_regs.h   | 53 +++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index ca9fdfbbe57c..2cad4ee9fe04 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -254,6 +254,7 @@
 #define   PLANE_COLOR_PIPE_CSC_ENABLE			REG_BIT(23) /* Pre-ICL */
 #define   PLANE_COLOR_PLANE_CSC_ENABLE			REG_BIT(21) /* ICL+ */
 #define   PLANE_COLOR_INPUT_CSC_ENABLE			REG_BIT(20) /* ICL+ */
+#define   PLANE_COLOR_PRE_CSC_GAMMA_ENABLE		REG_BIT(14)
 #define   PLANE_COLOR_CSC_MODE_MASK			REG_GENMASK(19, 17)
 #define   PLANE_COLOR_CSC_MODE_BYPASS			REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
 #define   PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601		REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
@@ -290,6 +291,58 @@
 									   _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B, \
 									   _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
 
+#define _MMIO_PLANE_GAMC(plane, i, a, b)  _MMIO(_PIPE(plane, a, b) + (i) * 4)
+
+/* Display13 Plane Degmma Reg */
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A      0x701d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B      0x711d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A      0x702d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B      0x712d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe)  _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, \
+                                               _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe)  _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, \
+                                               _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B)
+#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i)   \
+               _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \
+               _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe))
+#define         PLANE_PAL_PREC_AUTO_INCREMENT          REG_BIT(10)
+
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A       0x701d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B       0x711d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A       0x702d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B       0x712d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe)   _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, \
+                                               _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe)   _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, \
+                                               _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B)
+#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i)    \
+               _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe), \
+               _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_INDEX_1_A  0x704d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_1_B  0x714d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_2_A  0x705d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_2_B  0x715d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_1(pipe)      _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_1_A, \
+                                               _PLANE_PRE_CSC_GAMC_INDEX_1_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_2(pipe)      _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_2_A, \
+                                               _PLANE_PRE_CSC_GAMC_INDEX_2_B)
+#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i)       \
+               _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_1(pipe), \
+               _PLANE_PRE_CSC_GAMC_INDEX_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_DATA_1_A   0x704d4
+#define _PLANE_PRE_CSC_GAMC_DATA_1_B   0x714d4
+#define _PLANE_PRE_CSC_GAMC_DATA_2_A   0x705d4
+#define _PLANE_PRE_CSC_GAMC_DATA_2_B   0x715d4
+#define _PLANE_PRE_CSC_GAMC_DATA_1(pipe)       _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_1_A, \
+                                               _PLANE_PRE_CSC_GAMC_DATA_1_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_2(pipe)       _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_2_A, \
+                                               _PLANE_PRE_CSC_GAMC_DATA_2_B)
+#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i)        \
+               _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \
+               _PLANE_PRE_CSC_GAMC_DATA_2(pipe))
+
 #define _PLANE_CSC_RY_GY_1_A			0x70210
 #define _PLANE_CSC_RY_GY_2_A			0x70310
 #define _PLANE_CSC_RY_GY_1_B			0x71210
-- 
2.42.0


  parent reply	other threads:[~2025-03-12  7:13 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-12  7:24 [v4 00/23] Plane Color Pipeline support for Intel platforms Uma Shankar
2025-03-12  7:24 ` [NOT FOR REVIEW] [v4 01/23] drm: color pipeline base work Uma Shankar
2025-03-12  7:24 ` [v4 02/23] drm: Add support for 3x3 CTM Uma Shankar
2025-03-12  7:24 ` [v4 03/23] drm: Add Enhanced LUT precision structure Uma Shankar
2025-03-12  7:24 ` [v4 04/23] drm: Add Color lut range attributes Uma Shankar
2025-03-12  7:24 ` [v4 05/23] drm: Add Color ops capability property Uma Shankar
2025-03-12  7:24 ` [v4 06/23] drm: Add 1D LUT multi-segmented color op Uma Shankar
2025-03-12  7:24 ` [v4 07/23] drm: Define helper to initialize segmented 1D LUT Uma Shankar
2025-03-12  7:24 ` [v4 08/23] drm/i915: Add identifiers for intel color blocks Uma Shankar
2025-03-12  7:24 ` [v4 09/23] drm/i915: Add intel_color_op Uma Shankar
2025-03-12  7:24 ` [v4 10/23] drm/i915/color: Add helper to create intel colorop Uma Shankar
2025-03-12  7:24 ` [v4 11/23] drm/i915/color: Create a transfer function color pipeline Uma Shankar
2025-03-12  7:24 ` [v4 12/23] drm/i915/color: Add and attach COLORPIPELINE plane property Uma Shankar
2025-03-12  7:24 ` [v4 13/23] drm/i915/color: Add framework to set colorop Uma Shankar
2025-03-12  7:24 ` [v4 14/23] drm/i915/color: Add callbacks to set plane CTM Uma Shankar
2025-03-12  7:24 ` [v4 15/23] drm/i915/color: Add new color callbacks for Xelpd Uma Shankar
2025-03-12  7:24 ` [v4 16/23] drm/i915/color: Add plane CTM callback for D13 and beyond Uma Shankar
2025-03-12  7:24 ` Uma Shankar [this message]
2025-03-12  7:24 ` [v4 18/23] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
2025-03-12  7:24 ` [v4 19/23] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
2025-03-12  7:24 ` [v4 20/23] drm/i915/color: Program Pre-CSC registers Uma Shankar
2025-03-12  7:24 ` [v4 21/23] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
2025-03-12  7:24 ` [v4 22/23] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
2025-03-12  7:24 ` [v4 23/23] drm/doc/rfc: Add documentation for multi-segmented 1D LUT Uma Shankar
2025-03-12  7:56 ` ✗ Fi.CI.CHECKPATCH: warning for Plane Color Pipeline support for Intel platforms (rev4) Patchwork
2025-03-12  7:56 ` ✗ Fi.CI.SPARSE: " Patchwork
2025-03-12  8:53 ` ✓ i915.CI.BAT: success " Patchwork
2025-03-13  6:19 ` ✓ CI.Patch_applied: success for Plane Color Pipeline support for Intel platforms (rev3) Patchwork
2025-03-13  6:19 ` ✗ CI.checkpatch: warning " Patchwork
2025-03-13  6:21 ` ✓ CI.KUnit: success " Patchwork
2025-03-13  6:37 ` ✓ CI.Build: " Patchwork
2025-03-13  6:39 ` ✗ CI.Hooks: failure " Patchwork
2025-03-13  6:41 ` ✗ CI.checksparse: warning " Patchwork
2025-03-13  7:11 ` ✓ Xe.CI.BAT: success " Patchwork
2025-03-14 13:03 ` ✗ Xe.CI.Full: failure " Patchwork

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