From: Uma Shankar <uma.shankar@intel.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, harry.wentland@amd.com,
pekka.paalanen@haloniitty.fi, sebastian.wick@redhat.com,
jadahl@redhat.com, mwen@igalia.com, contact@emersion.fr,
naveen1.kumar@intel.com,
Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>,
Uma Shankar <uma.shankar@intel.com>
Subject: [v4 08/23] drm/i915: Add identifiers for intel color blocks
Date: Wed, 12 Mar 2025 12:54:10 +0530 [thread overview]
Message-ID: <20250312072425.3099205-9-uma.shankar@intel.com> (raw)
In-Reply-To: <20250312072425.3099205-1-uma.shankar@intel.com>
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add macros to identify intel color blocks. It will help
in mapping drm_color_ops to intel color HW blocks
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_limits.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h b/drivers/gpu/drm/i915/display/intel_display_limits.h
index f0fa27e365ab..97c960cc16aa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_limits.h
+++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
@@ -138,4 +138,17 @@ enum hpd_pin {
HPD_NUM_PINS
};
+/*
+ * Intel Color Blocks
+ *
+ */
+
+enum intel_color_block {
+ CB_PLANE_PRE_CSC_LUT,
+ CB_PLANE_CSC,
+ CB_PLANE_POST_CSC_LUT,
+
+ I915_MAX_CB
+};
+
#endif /* __INTEL_DISPLAY_LIMITS_H__ */
--
2.42.0
next prev parent reply other threads:[~2025-03-12 7:12 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-12 7:24 [v4 00/23] Plane Color Pipeline support for Intel platforms Uma Shankar
2025-03-12 7:24 ` [NOT FOR REVIEW] [v4 01/23] drm: color pipeline base work Uma Shankar
2025-03-12 7:24 ` [v4 02/23] drm: Add support for 3x3 CTM Uma Shankar
2025-03-12 7:24 ` [v4 03/23] drm: Add Enhanced LUT precision structure Uma Shankar
2025-03-12 7:24 ` [v4 04/23] drm: Add Color lut range attributes Uma Shankar
2025-03-12 7:24 ` [v4 05/23] drm: Add Color ops capability property Uma Shankar
2025-03-12 7:24 ` [v4 06/23] drm: Add 1D LUT multi-segmented color op Uma Shankar
2025-03-12 7:24 ` [v4 07/23] drm: Define helper to initialize segmented 1D LUT Uma Shankar
2025-03-12 7:24 ` Uma Shankar [this message]
2025-03-12 7:24 ` [v4 09/23] drm/i915: Add intel_color_op Uma Shankar
2025-03-12 7:24 ` [v4 10/23] drm/i915/color: Add helper to create intel colorop Uma Shankar
2025-03-12 7:24 ` [v4 11/23] drm/i915/color: Create a transfer function color pipeline Uma Shankar
2025-03-12 7:24 ` [v4 12/23] drm/i915/color: Add and attach COLORPIPELINE plane property Uma Shankar
2025-03-12 7:24 ` [v4 13/23] drm/i915/color: Add framework to set colorop Uma Shankar
2025-03-12 7:24 ` [v4 14/23] drm/i915/color: Add callbacks to set plane CTM Uma Shankar
2025-03-12 7:24 ` [v4 15/23] drm/i915/color: Add new color callbacks for Xelpd Uma Shankar
2025-03-12 7:24 ` [v4 16/23] drm/i915/color: Add plane CTM callback for D13 and beyond Uma Shankar
2025-03-12 7:24 ` [v4 17/23] drm/i915: Add register definitions for Plane Degamma Uma Shankar
2025-03-12 7:24 ` [v4 18/23] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
2025-03-12 7:24 ` [v4 19/23] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
2025-03-12 7:24 ` [v4 20/23] drm/i915/color: Program Pre-CSC registers Uma Shankar
2025-03-12 7:24 ` [v4 21/23] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
2025-03-12 7:24 ` [v4 22/23] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
2025-03-12 7:24 ` [v4 23/23] drm/doc/rfc: Add documentation for multi-segmented 1D LUT Uma Shankar
2025-03-12 7:56 ` ✗ Fi.CI.CHECKPATCH: warning for Plane Color Pipeline support for Intel platforms (rev4) Patchwork
2025-03-12 7:56 ` ✗ Fi.CI.SPARSE: " Patchwork
2025-03-12 8:53 ` ✓ i915.CI.BAT: success " Patchwork
2025-03-13 6:19 ` ✓ CI.Patch_applied: success for Plane Color Pipeline support for Intel platforms (rev3) Patchwork
2025-03-13 6:19 ` ✗ CI.checkpatch: warning " Patchwork
2025-03-13 6:21 ` ✓ CI.KUnit: success " Patchwork
2025-03-13 6:37 ` ✓ CI.Build: " Patchwork
2025-03-13 6:39 ` ✗ CI.Hooks: failure " Patchwork
2025-03-13 6:41 ` ✗ CI.checksparse: warning " Patchwork
2025-03-13 7:11 ` ✓ Xe.CI.BAT: success " Patchwork
2025-03-14 13:03 ` ✗ Xe.CI.Full: failure " Patchwork
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