* [PATCH 2/5] drm/amdgpu/gfx9.4.3: dump full CP packet header FIFOs
2025-03-20 16:56 [PATCH 1/5] drm/amdgpu/gfx9: dump full CP packet header FIFOs Alex Deucher
@ 2025-03-20 16:56 ` Alex Deucher
2025-03-20 16:56 ` [PATCH 3/5] drm/amdgpu/gfx10: " Alex Deucher
` (3 subsequent siblings)
4 siblings, 0 replies; 12+ messages in thread
From: Alex Deucher @ 2025-03-20 16:56 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
In dev core dump, dump the full header fifo for
each queue. Each FIFO has 8 entries.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 52 ++++++++++++++++++-------
1 file changed, 37 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index efe45e4edfd70..0157c96efc06b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -105,9 +105,6 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = {
SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE),
SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT),
SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6),
- /* cp header registers */
- SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
- SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME2_HEADER_DUMP),
/* SE status registers */
SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
@@ -154,6 +151,14 @@ static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9_4_3[] = {
SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
};
struct amdgpu_gfx_ras gfx_v9_4_3_ras;
@@ -4599,12 +4604,21 @@ static void gfx_v9_4_3_ip_print(struct amdgpu_ip_block *ip_block, struct drm_pri
"\nxcc:%d mec:%d, pipe:%d, queue:%d\n",
xcc_id, i, j, k);
for (reg = 0; reg < reg_count; reg++) {
- drm_printf(p,
- "%-50s \t 0x%08x\n",
- gc_cp_reg_list_9_4_3[reg].reg_name,
- adev->gfx.ip_dump_compute_queues
- [xcc_offset + inst_offset +
- reg]);
+ if (i && gc_cp_reg_list_9_4_3[reg].reg_offset ==
+ regCP_MEC_ME1_HEADER_DUMP)
+ drm_printf(p,
+ "%-50s \t 0x%08x\n",
+ "regCP_MEC_ME2_HEADER_DUMP",
+ adev->gfx.ip_dump_compute_queues
+ [xcc_offset + inst_offset +
+ reg]);
+ else
+ drm_printf(p,
+ "%-50s \t 0x%08x\n",
+ gc_cp_reg_list_9_4_3[reg].reg_name,
+ adev->gfx.ip_dump_compute_queues
+ [xcc_offset + inst_offset +
+ reg]);
}
inst_offset += reg_count;
}
@@ -4653,12 +4667,20 @@ static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block)
GET_INST(GC, xcc_id));
for (reg = 0; reg < reg_count; reg++) {
- adev->gfx.ip_dump_compute_queues
- [xcc_offset +
- inst_offset + reg] =
- RREG32(SOC15_REG_ENTRY_OFFSET_INST(
- gc_cp_reg_list_9_4_3[reg],
- GET_INST(GC, xcc_id)));
+ if (i && gc_cp_reg_list_9_4_3[reg].reg_offset ==
+ regCP_MEC_ME1_HEADER_DUMP)
+ adev->gfx.ip_dump_compute_queues
+ [xcc_offset +
+ inst_offset + reg] =
+ RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id),
+ regCP_MEC_ME2_HEADER_DUMP));
+ else
+ adev->gfx.ip_dump_compute_queues
+ [xcc_offset +
+ inst_offset + reg] =
+ RREG32(SOC15_REG_ENTRY_OFFSET_INST(
+ gc_cp_reg_list_9_4_3[reg],
+ GET_INST(GC, xcc_id)));
}
inst_offset += reg_count;
}
--
2.49.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 3/5] drm/amdgpu/gfx10: dump full CP packet header FIFOs
2025-03-20 16:56 [PATCH 1/5] drm/amdgpu/gfx9: dump full CP packet header FIFOs Alex Deucher
2025-03-20 16:56 ` [PATCH 2/5] drm/amdgpu/gfx9.4.3: " Alex Deucher
@ 2025-03-20 16:56 ` Alex Deucher
2025-03-20 16:56 ` [PATCH 4/5] drm/amdgpu/gfx11: " Alex Deucher
` (2 subsequent siblings)
4 siblings, 0 replies; 12+ messages in thread
From: Alex Deucher @ 2025-03-20 16:56 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
In dev core dump, dump the full header fifo for
each queue. Each FIFO has 8 entries.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 64 ++++++++++++++++++++------
1 file changed, 51 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 2275cdfb38cd1..0a817403ceaa2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -368,11 +368,6 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST),
/* cp header registers */
- SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
- SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
- SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
- SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
- SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP),
/* SE status registers */
SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
@@ -421,7 +416,16 @@ static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = {
SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),
- SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS),
+ /* cp header registers */
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
};
static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {
@@ -448,7 +452,32 @@ static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {
SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),
SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),
SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),
- SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI)
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI),
+ /* gfx header registers */
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
};
static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
@@ -9714,9 +9743,14 @@ static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printe
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
for (reg = 0; reg < reg_count; reg++) {
- drm_printf(p, "%-50s \t 0x%08x\n",
- gc_cp_reg_list_10[reg].reg_name,
- adev->gfx.ip_dump_compute_queues[index + reg]);
+ if (i && gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
+ drm_printf(p, "%-50s \t 0x%08x\n",
+ "mmCP_MEC_ME2_HEADER_DUMP",
+ adev->gfx.ip_dump_compute_queues[index + reg]);
+ else
+ drm_printf(p, "%-50s \t 0x%08x\n",
+ gc_cp_reg_list_10[reg].reg_name,
+ adev->gfx.ip_dump_compute_queues[index + reg]);
}
index += reg_count;
}
@@ -9777,9 +9811,13 @@ static void gfx_v10_ip_dump(struct amdgpu_ip_block *ip_block)
nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
for (reg = 0; reg < reg_count; reg++) {
- adev->gfx.ip_dump_compute_queues[index + reg] =
- RREG32(SOC15_REG_ENTRY_OFFSET(
- gc_cp_reg_list_10[reg]));
+ if (i && gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
+ adev->gfx.ip_dump_compute_queues[index + reg] =
+ RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));
+ else
+ adev->gfx.ip_dump_compute_queues[index + reg] =
+ RREG32(SOC15_REG_ENTRY_OFFSET(
+ gc_cp_reg_list_10[reg]));
}
index += reg_count;
}
--
2.49.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 4/5] drm/amdgpu/gfx11: dump full CP packet header FIFOs
2025-03-20 16:56 [PATCH 1/5] drm/amdgpu/gfx9: dump full CP packet header FIFOs Alex Deucher
2025-03-20 16:56 ` [PATCH 2/5] drm/amdgpu/gfx9.4.3: " Alex Deucher
2025-03-20 16:56 ` [PATCH 3/5] drm/amdgpu/gfx10: " Alex Deucher
@ 2025-03-20 16:56 ` Alex Deucher
2025-03-20 16:56 ` [PATCH 5/5] drm/amdgpu/gfx12: " Alex Deucher
2025-03-24 19:48 ` [PATCH 1/5] drm/amdgpu/gfx9: " Alex Deucher
4 siblings, 0 replies; 12+ messages in thread
From: Alex Deucher @ 2025-03-20 16:56 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
In dev core dump, dump the full header fifo for
each queue. Each FIFO has 8 entries.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 59 +++++++++++++++++++++-----
1 file changed, 49 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 719c4aa90a0e0..182f0122998a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -179,9 +179,13 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = {
SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),
SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
/* cp header registers */
- SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
- SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
- SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
/* SE status registers */
SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
@@ -232,7 +236,16 @@ static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_11[] = {
SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
- SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS)
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS),
+ /* cp header registers */
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
};
static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_11[] = {
@@ -261,7 +274,24 @@ static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_11[] = {
SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
- SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ)
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
+ /* cp header registers */
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
};
static const struct soc15_reg_golden golden_settings_gc_11_0[] = {
@@ -6738,9 +6768,14 @@ static void gfx_v11_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printe
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
for (reg = 0; reg < reg_count; reg++) {
- drm_printf(p, "%-50s \t 0x%08x\n",
- gc_cp_reg_list_11[reg].reg_name,
- adev->gfx.ip_dump_compute_queues[index + reg]);
+ if (i && gc_cp_reg_list_11[reg].reg_offset == regCP_MEC_ME1_HEADER_DUMP)
+ drm_printf(p, "%-50s \t 0x%08x\n",
+ "regCP_MEC_ME2_HEADER_DUMP",
+ adev->gfx.ip_dump_compute_queues[index + reg]);
+ else
+ drm_printf(p, "%-50s \t 0x%08x\n",
+ gc_cp_reg_list_11[reg].reg_name,
+ adev->gfx.ip_dump_compute_queues[index + reg]);
}
index += reg_count;
}
@@ -6800,9 +6835,13 @@ static void gfx_v11_ip_dump(struct amdgpu_ip_block *ip_block)
/* ME0 is for GFX so start from 1 for CP */
soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
for (reg = 0; reg < reg_count; reg++) {
+ if (i && gc_cp_reg_list_11[reg].reg_offset == regCP_MEC_ME1_HEADER_DUMP)
adev->gfx.ip_dump_compute_queues[index + reg] =
- RREG32(SOC15_REG_ENTRY_OFFSET(
- gc_cp_reg_list_11[reg]));
+ RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC_ME2_HEADER_DUMP));
+ else
+ adev->gfx.ip_dump_compute_queues[index + reg] =
+ RREG32(SOC15_REG_ENTRY_OFFSET(
+ gc_cp_reg_list_11[reg]));
}
index += reg_count;
}
--
2.49.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 5/5] drm/amdgpu/gfx12: dump full CP packet header FIFOs
2025-03-20 16:56 [PATCH 1/5] drm/amdgpu/gfx9: dump full CP packet header FIFOs Alex Deucher
` (2 preceding siblings ...)
2025-03-20 16:56 ` [PATCH 4/5] drm/amdgpu/gfx11: " Alex Deucher
@ 2025-03-20 16:56 ` Alex Deucher
2025-03-24 19:48 ` [PATCH 1/5] drm/amdgpu/gfx9: " Alex Deucher
4 siblings, 0 replies; 12+ messages in thread
From: Alex Deucher @ 2025-03-20 16:56 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
In dev core dump, dump the full header fifo for
each queue. Each FIFO has 8 entries.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 41 ++++++++++++++++++++++----
1 file changed, 35 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 634dd0abc0e80..ae41c91c9f6a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -135,11 +135,14 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = {
SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0),
SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1),
SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR),
-
/* cp header registers */
- SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
- SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
- SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
/* SE status registers */
SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
@@ -188,7 +191,16 @@ static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = {
SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
- SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS)
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS),
+ /* cp header registers */
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
};
static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = {
@@ -217,7 +229,24 @@ static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = {
SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
- SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ)
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
+ /* cp header registers */
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+ SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
};
static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = {
--
2.49.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 1/5] drm/amdgpu/gfx9: dump full CP packet header FIFOs
2025-03-20 16:56 [PATCH 1/5] drm/amdgpu/gfx9: dump full CP packet header FIFOs Alex Deucher
` (3 preceding siblings ...)
2025-03-20 16:56 ` [PATCH 5/5] drm/amdgpu/gfx12: " Alex Deucher
@ 2025-03-24 19:48 ` Alex Deucher
2025-04-07 8:50 ` Pierre-Eric Pelloux-Prayer
2025-04-07 10:14 ` Khatri, Sunil
4 siblings, 2 replies; 12+ messages in thread
From: Alex Deucher @ 2025-03-24 19:48 UTC (permalink / raw)
To: Alex Deucher; +Cc: amd-gfx
ping on this series?
Alex
On Thu, Mar 20, 2025 at 12:57 PM Alex Deucher <alexander.deucher@amd.com> wrote:
>
> In dev core dump, dump the full header fifo for
> each queue. Each FIFO has 8 entries.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 62 +++++++++++++++++++++------
> 1 file changed, 49 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index f4dfa1418b740..64342160ff7d0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -225,17 +225,36 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9[] = {
> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
> - /* cp header registers */
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> /* SE status registers */
> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
> - SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3),
> + /* packet headers */
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP)
> };
>
> static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
> @@ -277,6 +296,14 @@ static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GFX_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP)
> };
>
> enum ta_ras_gfx_subblock {
> @@ -7340,9 +7367,14 @@ static void gfx_v9_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer
> for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
> drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
> for (reg = 0; reg < reg_count; reg++) {
> - drm_printf(p, "%-50s \t 0x%08x\n",
> - gc_cp_reg_list_9[reg].reg_name,
> - adev->gfx.ip_dump_compute_queues[index + reg]);
> + if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
> + drm_printf(p, "%-50s \t 0x%08x\n",
> + "mmCP_MEC_ME2_HEADER_DUMP",
> + adev->gfx.ip_dump_compute_queues[index + reg]);
> + else
> + drm_printf(p, "%-50s \t 0x%08x\n",
> + gc_cp_reg_list_9[reg].reg_name,
> + adev->gfx.ip_dump_compute_queues[index + reg]);
> }
> index += reg_count;
> }
> @@ -7379,9 +7411,13 @@ static void gfx_v9_ip_dump(struct amdgpu_ip_block *ip_block)
> soc15_grbm_select(adev, 1 + i, j, k, 0, 0);
>
> for (reg = 0; reg < reg_count; reg++) {
> - adev->gfx.ip_dump_compute_queues[index + reg] =
> - RREG32(SOC15_REG_ENTRY_OFFSET(
> - gc_cp_reg_list_9[reg]));
> + if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
> + adev->gfx.ip_dump_compute_queues[index + reg] =
> + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));
> + else
> + adev->gfx.ip_dump_compute_queues[index + reg] =
> + RREG32(SOC15_REG_ENTRY_OFFSET(
> + gc_cp_reg_list_9[reg]));
> }
> index += reg_count;
> }
> --
> 2.49.0
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/5] drm/amdgpu/gfx9: dump full CP packet header FIFOs
2025-03-24 19:48 ` [PATCH 1/5] drm/amdgpu/gfx9: " Alex Deucher
@ 2025-04-07 8:50 ` Pierre-Eric Pelloux-Prayer
2025-04-07 10:14 ` Khatri, Sunil
1 sibling, 0 replies; 12+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-04-07 8:50 UTC (permalink / raw)
To: Alex Deucher, Alex Deucher; +Cc: amd-gfx
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Le 24/03/2025 à 20:48, Alex Deucher a écrit :
> ping on this series?
>
> Alex
>
> On Thu, Mar 20, 2025 at 12:57 PM Alex Deucher <alexander.deucher@amd.com> wrote:
>>
>> In dev core dump, dump the full header fifo for
>> each queue. Each FIFO has 8 entries.
>>
>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 62 +++++++++++++++++++++------
>> 1 file changed, 49 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index f4dfa1418b740..64342160ff7d0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -225,17 +225,36 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9[] = {
>> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
>> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
>> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
>> - /* cp header registers */
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> /* SE status registers */
>> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
>> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
>> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3),
>> + /* packet headers */
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP)
>> };
>>
>> static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
>> @@ -277,6 +296,14 @@ static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
>> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
>> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
>> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GFX_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP)
>> };
>>
>> enum ta_ras_gfx_subblock {
>> @@ -7340,9 +7367,14 @@ static void gfx_v9_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer
>> for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
>> drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
>> for (reg = 0; reg < reg_count; reg++) {
>> - drm_printf(p, "%-50s \t 0x%08x\n",
>> - gc_cp_reg_list_9[reg].reg_name,
>> - adev->gfx.ip_dump_compute_queues[index + reg]);
>> + if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
>> + drm_printf(p, "%-50s \t 0x%08x\n",
>> + "mmCP_MEC_ME2_HEADER_DUMP",
>> + adev->gfx.ip_dump_compute_queues[index + reg]);
>> + else
>> + drm_printf(p, "%-50s \t 0x%08x\n",
>> + gc_cp_reg_list_9[reg].reg_name,
>> + adev->gfx.ip_dump_compute_queues[index + reg]);
>> }
>> index += reg_count;
>> }
>> @@ -7379,9 +7411,13 @@ static void gfx_v9_ip_dump(struct amdgpu_ip_block *ip_block)
>> soc15_grbm_select(adev, 1 + i, j, k, 0, 0);
>>
>> for (reg = 0; reg < reg_count; reg++) {
>> - adev->gfx.ip_dump_compute_queues[index + reg] =
>> - RREG32(SOC15_REG_ENTRY_OFFSET(
>> - gc_cp_reg_list_9[reg]));
>> + if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
>> + adev->gfx.ip_dump_compute_queues[index + reg] =
>> + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));
>> + else
>> + adev->gfx.ip_dump_compute_queues[index + reg] =
>> + RREG32(SOC15_REG_ENTRY_OFFSET(
>> + gc_cp_reg_list_9[reg]));
>> }
>> index += reg_count;
>> }
>> --
>> 2.49.0
>>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/5] drm/amdgpu/gfx9: dump full CP packet header FIFOs
2025-03-24 19:48 ` [PATCH 1/5] drm/amdgpu/gfx9: " Alex Deucher
2025-04-07 8:50 ` Pierre-Eric Pelloux-Prayer
@ 2025-04-07 10:14 ` Khatri, Sunil
2025-04-07 12:56 ` Alex Deucher
1 sibling, 1 reply; 12+ messages in thread
From: Khatri, Sunil @ 2025-04-07 10:14 UTC (permalink / raw)
To: Alex Deucher, Alex Deucher; +Cc: amd-gfx
[-- Attachment #1: Type: text/plain, Size: 7431 bytes --]
On 3/25/2025 1:18 AM, Alex Deucher wrote:
> ping on this series?
>
> Alex
>
> On Thu, Mar 20, 2025 at 12:57 PM Alex Deucher<alexander.deucher@amd.com> wrote:
>> In dev core dump, dump the full header fifo for
>> each queue. Each FIFO has 8 entries.
>>
>> Signed-off-by: Alex Deucher<alexander.deucher@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 62 +++++++++++++++++++++------
>> 1 file changed, 49 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index f4dfa1418b740..64342160ff7d0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -225,17 +225,36 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9[] = {
>> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
>> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
>> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
>> - /* cp header registers */
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> /* SE status registers */
>> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
>> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
>> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3),
>> + /* packet headers */
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
Reading this register in a loop will give value of each queue or we are
reading same register again and again ?
for(i=0; i<reg_count; i++)
adev->gfx.ip_dump_core[i]
=RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_9[i])); With above loop arent
we reading same offset again for
mmCP_CE_HEADER_DUMP,mmCP_PFP_HEADER_DUMP and mmCP_ME_HEADER_DUMP 8 times. How are we making sure we are reading from different queues ?
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP)
>> };
>>
>> static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
>> @@ -277,6 +296,14 @@ static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
>> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
>> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
>> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GFX_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP)
>> };
>>
>> enum ta_ras_gfx_subblock {
>> @@ -7340,9 +7367,14 @@ static void gfx_v9_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer
>> for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
>> drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
>> for (reg = 0; reg < reg_count; reg++) {
>> - drm_printf(p, "%-50s \t 0x%08x\n",
>> - gc_cp_reg_list_9[reg].reg_name,
>> - adev->gfx.ip_dump_compute_queues[index + reg]);
>> + if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
>> + drm_printf(p, "%-50s \t 0x%08x\n",
>> + "mmCP_MEC_ME2_HEADER_DUMP",
>> + adev->gfx.ip_dump_compute_queues[index + reg]);
>> + else
>> + drm_printf(p, "%-50s \t 0x%08x\n",
>> + gc_cp_reg_list_9[reg].reg_name,
>> + adev->gfx.ip_dump_compute_queues[index + reg]);
>> }
>> index += reg_count;
>> }
>> @@ -7379,9 +7411,13 @@ static void gfx_v9_ip_dump(struct amdgpu_ip_block *ip_block)
>> soc15_grbm_select(adev, 1 + i, j, k, 0, 0);
>>
>> for (reg = 0; reg < reg_count; reg++) {
>> - adev->gfx.ip_dump_compute_queues[index + reg] =
>> - RREG32(SOC15_REG_ENTRY_OFFSET(
>> - gc_cp_reg_list_9[reg]));
>> + if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
>> + adev->gfx.ip_dump_compute_queues[index + reg] =
>> + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));
>> + else
>> + adev->gfx.ip_dump_compute_queues[index + reg] =
>> + RREG32(SOC15_REG_ENTRY_OFFSET(
>> + gc_cp_reg_list_9[reg]));
When value of (i != 0), arent we reading same register i.e
mmCP_MEC_ME1_HEADER_DUMP 8 times, how are we making sure when we read it
again its reading for another queue ?
Regards
Sunil Khatri
>> }
>> index += reg_count;
>> }
>> --
>> 2.49.0
>>
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^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/5] drm/amdgpu/gfx9: dump full CP packet header FIFOs
2025-04-07 10:14 ` Khatri, Sunil
@ 2025-04-07 12:56 ` Alex Deucher
2025-04-07 13:27 ` Khatri, Sunil
0 siblings, 1 reply; 12+ messages in thread
From: Alex Deucher @ 2025-04-07 12:56 UTC (permalink / raw)
To: Khatri, Sunil; +Cc: Alex Deucher, amd-gfx
On Mon, Apr 7, 2025 at 6:14 AM Khatri, Sunil <sukhatri@amd.com> wrote:
>
>
> On 3/25/2025 1:18 AM, Alex Deucher wrote:
>
> ping on this series?
>
> Alex
>
> On Thu, Mar 20, 2025 at 12:57 PM Alex Deucher <alexander.deucher@amd.com> wrote:
>
> In dev core dump, dump the full header fifo for
> each queue. Each FIFO has 8 entries.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 62 +++++++++++++++++++++------
> 1 file changed, 49 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index f4dfa1418b740..64342160ff7d0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -225,17 +225,36 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9[] = {
> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
> - /* cp header registers */
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> /* SE status registers */
> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
> - SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3),
> + /* packet headers */
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>
> Reading this register in a loop will give value of each queue or we are reading same register again and again ?
The register is an accessor for the header FIFO in the queue hardware.
The FIFO is 8 entries deep so if you read the register 8 times, you
can dump the full FIFO.
> for (i = 0; i < reg_count; i++)
> adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_9[i])); With above loop arent we reading same offset again for
>
> mmCP_CE_HEADER_DUMP,mmCP_PFP_HEADER_DUMP and mmCP_ME_HEADER_DUMP 8 times. How are we making sure we are reading from different queues ?
The me/pipes/queues are indexed via soc15_grbm_select().
Alex
>
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP)
> };
>
> static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
> @@ -277,6 +296,14 @@ static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GFX_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP)
> };
>
> enum ta_ras_gfx_subblock {
> @@ -7340,9 +7367,14 @@ static void gfx_v9_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer
> for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
> drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
> for (reg = 0; reg < reg_count; reg++) {
> - drm_printf(p, "%-50s \t 0x%08x\n",
> - gc_cp_reg_list_9[reg].reg_name,
> - adev->gfx.ip_dump_compute_queues[index + reg]);
> + if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
> + drm_printf(p, "%-50s \t 0x%08x\n",
> + "mmCP_MEC_ME2_HEADER_DUMP",
> + adev->gfx.ip_dump_compute_queues[index + reg]);
> + else
> + drm_printf(p, "%-50s \t 0x%08x\n",
> + gc_cp_reg_list_9[reg].reg_name,
> + adev->gfx.ip_dump_compute_queues[index + reg]);
> }
> index += reg_count;
> }
> @@ -7379,9 +7411,13 @@ static void gfx_v9_ip_dump(struct amdgpu_ip_block *ip_block)
> soc15_grbm_select(adev, 1 + i, j, k, 0, 0);
>
> for (reg = 0; reg < reg_count; reg++) {
> - adev->gfx.ip_dump_compute_queues[index + reg] =
> - RREG32(SOC15_REG_ENTRY_OFFSET(
> - gc_cp_reg_list_9[reg]));
> + if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
> + adev->gfx.ip_dump_compute_queues[index + reg] =
> + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));
> + else
> + adev->gfx.ip_dump_compute_queues[index + reg] =
> + RREG32(SOC15_REG_ENTRY_OFFSET(
> + gc_cp_reg_list_9[reg]));
>
> When value of (i != 0), arent we reading same register i.e mmCP_MEC_ME1_HEADER_DUMP 8 times, how are we making sure when we read it again its reading for another queue ?
>
> Regards
> Sunil Khatri
>
> }
> index += reg_count;
> }
> --
> 2.49.0
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/5] drm/amdgpu/gfx9: dump full CP packet header FIFOs
2025-04-07 12:56 ` Alex Deucher
@ 2025-04-07 13:27 ` Khatri, Sunil
2025-04-07 13:45 ` Alex Deucher
0 siblings, 1 reply; 12+ messages in thread
From: Khatri, Sunil @ 2025-04-07 13:27 UTC (permalink / raw)
To: Alex Deucher; +Cc: Alex Deucher, amd-gfx
[-- Attachment #1: Type: text/plain, Size: 8514 bytes --]
On 4/7/2025 6:26 PM, Alex Deucher wrote:
> On Mon, Apr 7, 2025 at 6:14 AM Khatri, Sunil<sukhatri@amd.com> wrote:
>>
>> On 3/25/2025 1:18 AM, Alex Deucher wrote:
>>
>> ping on this series?
>>
>> Alex
>>
>> On Thu, Mar 20, 2025 at 12:57 PM Alex Deucher<alexander.deucher@amd.com> wrote:
>>
>> In dev core dump, dump the full header fifo for
>> each queue. Each FIFO has 8 entries.
>>
>> Signed-off-by: Alex Deucher<alexander.deucher@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 62 +++++++++++++++++++++------
>> 1 file changed, 49 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index f4dfa1418b740..64342160ff7d0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -225,17 +225,36 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9[] = {
>> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
>> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
>> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
>> - /* cp header registers */
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> /* SE status registers */
>> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
>> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
>> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3),
>> + /* packet headers */
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>>
>> Reading this register in a loop will give value of each queue or we are reading same register again and again ?
> The register is an accessor for the header FIFO in the queue hardware.
> The FIFO is 8 entries deep so if you read the register 8 times, you
> can dump the full FIFO.
>
> Thanks for this information. I was kind of thinking the same but dint know it works directly and need not to change the way we read like setting grbm etc.
>
>> for (i = 0; i < reg_count; i++)
>> adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_9[i])); With above loop arent we reading same offset again for
>>
>> mmCP_CE_HEADER_DUMP,mmCP_PFP_HEADER_DUMP and mmCP_ME_HEADER_DUMP 8 times. How are we making sure we are reading from different queues ?
> The me/pipes/queues are indexed via soc15_grbm_select().
>
> Alex
>
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP)
>> };
>>
>> static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
>> @@ -277,6 +296,14 @@ static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
>> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
>> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
>> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GFX_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP)
>> };
>>
>> enum ta_ras_gfx_subblock {
>> @@ -7340,9 +7367,14 @@ static void gfx_v9_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer
>> for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
>> drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
>> for (reg = 0; reg < reg_count; reg++) {
>> - drm_printf(p, "%-50s \t 0x%08x\n",
>> - gc_cp_reg_list_9[reg].reg_name,
>> - adev->gfx.ip_dump_compute_queues[index + reg]);
>> + if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
>> + drm_printf(p, "%-50s \t 0x%08x\n",
>> + "mmCP_MEC_ME2_HEADER_DUMP",
>> + adev->gfx.ip_dump_compute_queues[index + reg]);
>> + else
>> + drm_printf(p, "%-50s \t 0x%08x\n",
>> + gc_cp_reg_list_9[reg].reg_name,
>> + adev->gfx.ip_dump_compute_queues[index + reg]);
>> }
>> index += reg_count;
>> }
>> @@ -7379,9 +7411,13 @@ static void gfx_v9_ip_dump(struct amdgpu_ip_block *ip_block)
>> soc15_grbm_select(adev, 1 + i, j, k, 0, 0);
>>
>> for (reg = 0; reg < reg_count; reg++) {
>> - adev->gfx.ip_dump_compute_queues[index + reg] =
>> - RREG32(SOC15_REG_ENTRY_OFFSET(
>> - gc_cp_reg_list_9[reg]));
>> + if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
>> + adev->gfx.ip_dump_compute_queues[index + reg] =
>> + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));
>> + else
>> + adev->gfx.ip_dump_compute_queues[index + reg] =
>> + RREG32(SOC15_REG_ENTRY_OFFSET(
>> + gc_cp_reg_list_9[reg]));
>>
>> When value of (i != 0), arent we reading same register i.e mmCP_MEC_ME1_HEADER_DUMP 8 times, how are we making sure when we read it again its reading for another queue ?
>>
>> Regards
>> Sunil Khatri
I am assuming here also same explanation applies that when we read the
same register again we are getting the next value in the queue but why
use this value of offset mmCP_MEC_ME1_HEADER_DUMP but read the register
mmCP_MEC_ME2_HEADER_DUMP ??
For i=0, we are dumping mmCP_MEC_ME2_HEADER_DUMP but for value of i >0
we are dumping mmCP_MEC_ME1_HEADER_DUMP ? Is that because
mmCP_MEC_ME1_HEADER_DUMP belongs to MEC1 i.e for mec0 and for i > 0 i.e
MEC2 we need to read mmCP_MEC_ME2_HEADER_DUMP ?
>>
>> }
>> index += reg_count;
>> }
>> --
>> 2.49.0
>>
[-- Attachment #2: Type: text/html, Size: 9754 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/5] drm/amdgpu/gfx9: dump full CP packet header FIFOs
2025-04-07 13:27 ` Khatri, Sunil
@ 2025-04-07 13:45 ` Alex Deucher
2025-04-07 14:00 ` Khatri, Sunil
0 siblings, 1 reply; 12+ messages in thread
From: Alex Deucher @ 2025-04-07 13:45 UTC (permalink / raw)
To: Khatri, Sunil; +Cc: Alex Deucher, amd-gfx
On Mon, Apr 7, 2025 at 9:27 AM Khatri, Sunil <sukhatri@amd.com> wrote:
>
>
> On 4/7/2025 6:26 PM, Alex Deucher wrote:
>
> On Mon, Apr 7, 2025 at 6:14 AM Khatri, Sunil <sukhatri@amd.com> wrote:
>
> On 3/25/2025 1:18 AM, Alex Deucher wrote:
>
> ping on this series?
>
> Alex
>
> On Thu, Mar 20, 2025 at 12:57 PM Alex Deucher <alexander.deucher@amd.com> wrote:
>
> In dev core dump, dump the full header fifo for
> each queue. Each FIFO has 8 entries.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 62 +++++++++++++++++++++------
> 1 file changed, 49 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index f4dfa1418b740..64342160ff7d0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -225,17 +225,36 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9[] = {
> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
> - /* cp header registers */
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> /* SE status registers */
> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
> - SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3),
> + /* packet headers */
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>
> Reading this register in a loop will give value of each queue or we are reading same register again and again ?
>
> The register is an accessor for the header FIFO in the queue hardware.
> The FIFO is 8 entries deep so if you read the register 8 times, you
> can dump the full FIFO.
>
> Thanks for this information. I was kind of thinking the same but dint know it works directly and need not to change the way we read like setting grbm etc.
>
> for (i = 0; i < reg_count; i++)
> adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_9[i])); With above loop arent we reading same offset again for
>
> mmCP_CE_HEADER_DUMP,mmCP_PFP_HEADER_DUMP and mmCP_ME_HEADER_DUMP 8 times. How are we making sure we are reading from different queues ?
>
> The me/pipes/queues are indexed via soc15_grbm_select().
>
> Alex
>
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP)
> };
>
> static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
> @@ -277,6 +296,14 @@ static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GFX_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP)
> };
>
> enum ta_ras_gfx_subblock {
> @@ -7340,9 +7367,14 @@ static void gfx_v9_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer
> for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
> drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
> for (reg = 0; reg < reg_count; reg++) {
> - drm_printf(p, "%-50s \t 0x%08x\n",
> - gc_cp_reg_list_9[reg].reg_name,
> - adev->gfx.ip_dump_compute_queues[index + reg]);
> + if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
> + drm_printf(p, "%-50s \t 0x%08x\n",
> + "mmCP_MEC_ME2_HEADER_DUMP",
> + adev->gfx.ip_dump_compute_queues[index + reg]);
> + else
> + drm_printf(p, "%-50s \t 0x%08x\n",
> + gc_cp_reg_list_9[reg].reg_name,
> + adev->gfx.ip_dump_compute_queues[index + reg]);
> }
> index += reg_count;
> }
> @@ -7379,9 +7411,13 @@ static void gfx_v9_ip_dump(struct amdgpu_ip_block *ip_block)
> soc15_grbm_select(adev, 1 + i, j, k, 0, 0);
>
> for (reg = 0; reg < reg_count; reg++) {
> - adev->gfx.ip_dump_compute_queues[index + reg] =
> - RREG32(SOC15_REG_ENTRY_OFFSET(
> - gc_cp_reg_list_9[reg]));
> + if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
> + adev->gfx.ip_dump_compute_queues[index + reg] =
> + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));
> + else
> + adev->gfx.ip_dump_compute_queues[index + reg] =
> + RREG32(SOC15_REG_ENTRY_OFFSET(
> + gc_cp_reg_list_9[reg]));
>
> When value of (i != 0), arent we reading same register i.e mmCP_MEC_ME1_HEADER_DUMP 8 times, how are we making sure when we read it again its reading for another queue ?
>
> Regards
> Sunil Khatri
>
> I am assuming here also same explanation applies that when we read the same register again we are getting the next value in the queue but why use this value of offset mmCP_MEC_ME1_HEADER_DUMP but read the register mmCP_MEC_ME2_HEADER_DUMP ??
>
>
> For i=0, we are dumping mmCP_MEC_ME2_HEADER_DUMP but for value of i >0 we are dumping mmCP_MEC_ME1_HEADER_DUMP ? Is that because mmCP_MEC_ME1_HEADER_DUMP belongs to MEC1 i.e for mec0 and for i > 0 i.e MEC2 we need to read mmCP_MEC_ME2_HEADER_DUMP ?
>
Yes. There are different registers for each ME. ME0 uses
mmCP_[CE|PFP|ME]_HEADER_DUMP, ME1 uses mmCP_MEC_ME1_HEADER_DUMP and
ME2 uses mmCP_MEC_ME2_HEADER_DUMP.
Alex
> }
> index += reg_count;
> }
> --
> 2.49.0
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/5] drm/amdgpu/gfx9: dump full CP packet header FIFOs
2025-04-07 13:45 ` Alex Deucher
@ 2025-04-07 14:00 ` Khatri, Sunil
0 siblings, 0 replies; 12+ messages in thread
From: Khatri, Sunil @ 2025-04-07 14:00 UTC (permalink / raw)
To: Alex Deucher; +Cc: Alex Deucher, amd-gfx
Thanks for the insight Alex.
Series Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
On 4/7/2025 7:15 PM, Alex Deucher wrote:
> On Mon, Apr 7, 2025 at 9:27 AM Khatri, Sunil <sukhatri@amd.com> wrote:
>>
>> On 4/7/2025 6:26 PM, Alex Deucher wrote:
>>
>> On Mon, Apr 7, 2025 at 6:14 AM Khatri, Sunil <sukhatri@amd.com> wrote:
>>
>> On 3/25/2025 1:18 AM, Alex Deucher wrote:
>>
>> ping on this series?
>>
>> Alex
>>
>> On Thu, Mar 20, 2025 at 12:57 PM Alex Deucher <alexander.deucher@amd.com> wrote:
>>
>> In dev core dump, dump the full header fifo for
>> each queue. Each FIFO has 8 entries.
>>
>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 62 +++++++++++++++++++++------
>> 1 file changed, 49 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index f4dfa1418b740..64342160ff7d0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -225,17 +225,36 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9[] = {
>> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
>> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
>> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
>> - /* cp header registers */
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> /* SE status registers */
>> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
>> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
>> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
>> - SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3),
>> + /* packet headers */
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>>
>> Reading this register in a loop will give value of each queue or we are reading same register again and again ?
>>
>> The register is an accessor for the header FIFO in the queue hardware.
>> The FIFO is 8 entries deep so if you read the register 8 times, you
>> can dump the full FIFO.
>>
>> Thanks for this information. I was kind of thinking the same but dint know it works directly and need not to change the way we read like setting grbm etc.
>>
>> for (i = 0; i < reg_count; i++)
>> adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_9[i])); With above loop arent we reading same offset again for
>>
>> mmCP_CE_HEADER_DUMP,mmCP_PFP_HEADER_DUMP and mmCP_ME_HEADER_DUMP 8 times. How are we making sure we are reading from different queues ?
>>
>> The me/pipes/queues are indexed via soc15_grbm_select().
>>
>> Alex
>>
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP)
>> };
>>
>> static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
>> @@ -277,6 +296,14 @@ static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
>> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
>> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
>> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GFX_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP)
>> };
>>
>> enum ta_ras_gfx_subblock {
>> @@ -7340,9 +7367,14 @@ static void gfx_v9_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer
>> for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
>> drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
>> for (reg = 0; reg < reg_count; reg++) {
>> - drm_printf(p, "%-50s \t 0x%08x\n",
>> - gc_cp_reg_list_9[reg].reg_name,
>> - adev->gfx.ip_dump_compute_queues[index + reg]);
>> + if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
>> + drm_printf(p, "%-50s \t 0x%08x\n",
>> + "mmCP_MEC_ME2_HEADER_DUMP",
>> + adev->gfx.ip_dump_compute_queues[index + reg]);
>> + else
>> + drm_printf(p, "%-50s \t 0x%08x\n",
>> + gc_cp_reg_list_9[reg].reg_name,
>> + adev->gfx.ip_dump_compute_queues[index + reg]);
>> }
>> index += reg_count;
>> }
>> @@ -7379,9 +7411,13 @@ static void gfx_v9_ip_dump(struct amdgpu_ip_block *ip_block)
>> soc15_grbm_select(adev, 1 + i, j, k, 0, 0);
>>
>> for (reg = 0; reg < reg_count; reg++) {
>> - adev->gfx.ip_dump_compute_queues[index + reg] =
>> - RREG32(SOC15_REG_ENTRY_OFFSET(
>> - gc_cp_reg_list_9[reg]));
>> + if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
>> + adev->gfx.ip_dump_compute_queues[index + reg] =
>> + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));
>> + else
>> + adev->gfx.ip_dump_compute_queues[index + reg] =
>> + RREG32(SOC15_REG_ENTRY_OFFSET(
>> + gc_cp_reg_list_9[reg]));
>>
>> When value of (i != 0), arent we reading same register i.e mmCP_MEC_ME1_HEADER_DUMP 8 times, how are we making sure when we read it again its reading for another queue ?
>>
>> Regards
>> Sunil Khatri
>>
>> I am assuming here also same explanation applies that when we read the same register again we are getting the next value in the queue but why use this value of offset mmCP_MEC_ME1_HEADER_DUMP but read the register mmCP_MEC_ME2_HEADER_DUMP ??
>>
>>
>> For i=0, we are dumping mmCP_MEC_ME2_HEADER_DUMP but for value of i >0 we are dumping mmCP_MEC_ME1_HEADER_DUMP ? Is that because mmCP_MEC_ME1_HEADER_DUMP belongs to MEC1 i.e for mec0 and for i > 0 i.e MEC2 we need to read mmCP_MEC_ME2_HEADER_DUMP ?
>>
> Yes. There are different registers for each ME. ME0 uses
> mmCP_[CE|PFP|ME]_HEADER_DUMP, ME1 uses mmCP_MEC_ME1_HEADER_DUMP and
> ME2 uses mmCP_MEC_ME2_HEADER_DUMP.
>
> Alex
>
>> }
>> index += reg_count;
>> }
>> --
>> 2.49.0
>>
^ permalink raw reply [flat|nested] 12+ messages in thread