From: Alex Elder <elder@riscstar.com>
To: p.zabel@pengutronix.de, mturquette@baylibre.com,
sboyd@kernel.org, dlan@gentoo.org
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu,
spacemit@lists.linux.dev, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH RESEND 4/7] clk: spacemit: define existing syscon resets
Date: Fri, 21 Mar 2025 10:18:27 -0500 [thread overview]
Message-ID: <20250321151831.623575-5-elder@riscstar.com> (raw)
In-Reply-To: <20250321151831.623575-1-elder@riscstar.com>
Define reset controls associated with the MPMU, APBC, and APMU
SpacemiT K1 CCUs. These already have clocks associated with them.
Signed-off-by: Alex Elder <elder@riscstar.com>
---
drivers/clk/spacemit/ccu-k1.c | 132 ++++++++++++++++++++++++++++++++++
1 file changed, 132 insertions(+)
diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c
index 6d879411c6c05..be8abd27753cb 100644
--- a/drivers/clk/spacemit/ccu-k1.c
+++ b/drivers/clk/spacemit/ccu-k1.c
@@ -151,6 +151,13 @@ struct k1_ccu_data {
const struct ccu_reset_controller_data *rst_data;
};
+#define RST_DATA(_offset, _assert_mask, _deassert_mask) \
+ { \
+ .offset = (_offset), \
+ .assert_mask = (_assert_mask), \
+ .deassert_mask = (_deassert_mask), \
+ }
+
struct ccu_reset_controller {
struct regmap *regmap;
const struct ccu_reset_controller_data *data;
@@ -1428,6 +1435,7 @@ static struct spacemit_ccu_clk k1_ccu_apbs_clks[] = {
static const struct k1_ccu_data k1_ccu_apbs_data = {
.clk = k1_ccu_apbs_clks,
+ /* No resets in the APBS CCU */
};
static struct spacemit_ccu_clk k1_ccu_mpmu_clks[] = {
@@ -1467,8 +1475,18 @@ static struct spacemit_ccu_clk k1_ccu_mpmu_clks[] = {
{ 0, NULL },
};
+static const struct ccu_reset_data mpmu_reset_data[] = {
+ [RST_WDT] = RST_DATA(MPMU_WDTPCR, BIT(2), 0),
+};
+
+static const struct ccu_reset_controller_data mpmu_reset_controller_data = {
+ .count = ARRAY_SIZE(mpmu_reset_data),
+ .data = mpmu_reset_data,
+};
+
static const struct k1_ccu_data k1_ccu_mpmu_data = {
.clk = k1_ccu_mpmu_clks,
+ .rst_data = &mpmu_reset_controller_data,
};
static struct spacemit_ccu_clk k1_ccu_apbc_clks[] = {
@@ -1575,8 +1593,68 @@ static struct spacemit_ccu_clk k1_ccu_apbc_clks[] = {
{ 0, NULL },
};
+static const struct ccu_reset_data apbc_reset_data[] = {
+ [RST_UART0] = RST_DATA(APBC_UART1_CLK_RST, BIT(2), 0),
+ [RST_UART2] = RST_DATA(APBC_UART2_CLK_RST, BIT(2), 0),
+ [RST_GPIO] = RST_DATA(APBC_GPIO_CLK_RST, BIT(2), 0),
+ [RST_PWM0] = RST_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM1] = RST_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM2] = RST_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM3] = RST_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM4] = RST_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM5] = RST_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM6] = RST_DATA(APBC_PWM6_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM7] = RST_DATA(APBC_PWM7_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM8] = RST_DATA(APBC_PWM8_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM9] = RST_DATA(APBC_PWM9_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM10] = RST_DATA(APBC_PWM10_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM11] = RST_DATA(APBC_PWM11_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM12] = RST_DATA(APBC_PWM12_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM13] = RST_DATA(APBC_PWM13_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM14] = RST_DATA(APBC_PWM14_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM15] = RST_DATA(APBC_PWM15_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM16] = RST_DATA(APBC_PWM16_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM17] = RST_DATA(APBC_PWM17_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM18] = RST_DATA(APBC_PWM18_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM19] = RST_DATA(APBC_PWM19_CLK_RST, BIT(2), BIT(0)),
+ [RST_SSP3] = RST_DATA(APBC_SSP3_CLK_RST, BIT(2), 0),
+ [RST_UART3] = RST_DATA(APBC_UART3_CLK_RST, BIT(2), 0),
+ [RST_RTC] = RST_DATA(APBC_RTC_CLK_RST, BIT(2), 0),
+ [RST_TWSI0] = RST_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0),
+ [RST_TIMERS1] = RST_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0),
+ [RST_AIB] = RST_DATA(APBC_AIB_CLK_RST, BIT(2), 0),
+ [RST_TIMERS2] = RST_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0),
+ [RST_ONEWIRE] = RST_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0),
+ [RST_SSPA0] = RST_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0),
+ [RST_SSPA1] = RST_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0),
+ [RST_DRO] = RST_DATA(APBC_DRO_CLK_RST, BIT(2), 0),
+ [RST_IR] = RST_DATA(APBC_IR_CLK_RST, BIT(2), 0),
+ [RST_TWSI1] = RST_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0),
+ [RST_TSEN] = RST_DATA(APBC_TSEN_CLK_RST, BIT(2), 0),
+ [RST_TWSI2] = RST_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0),
+ [RST_TWSI4] = RST_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0),
+ [RST_TWSI5] = RST_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0),
+ [RST_TWSI6] = RST_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0),
+ [RST_TWSI7] = RST_DATA(APBC_TWSI7_CLK_RST, BIT(2), 0),
+ [RST_TWSI8] = RST_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0),
+ [RST_IPC_AP2AUD] = RST_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0),
+ [RST_UART4] = RST_DATA(APBC_UART4_CLK_RST, BIT(2), 0),
+ [RST_UART5] = RST_DATA(APBC_UART5_CLK_RST, BIT(2), 0),
+ [RST_UART6] = RST_DATA(APBC_UART6_CLK_RST, BIT(2), 0),
+ [RST_UART7] = RST_DATA(APBC_UART7_CLK_RST, BIT(2), 0),
+ [RST_UART8] = RST_DATA(APBC_UART8_CLK_RST, BIT(2), 0),
+ [RST_UART9] = RST_DATA(APBC_UART9_CLK_RST, BIT(2), 0),
+ [RST_CAN0] = RST_DATA(APBC_CAN0_CLK_RST, BIT(2), 0),
+};
+
+static const struct ccu_reset_controller_data apbc_reset_controller_data = {
+ .count = ARRAY_SIZE(apbc_reset_data),
+ .data = apbc_reset_data,
+};
+
static const struct k1_ccu_data k1_ccu_apbc_data = {
.clk = k1_ccu_apbc_clks,
+ .rst_data = &apbc_reset_controller_data,
};
static struct spacemit_ccu_clk k1_ccu_apmu_clks[] = {
@@ -1645,8 +1723,62 @@ static struct spacemit_ccu_clk k1_ccu_apmu_clks[] = {
{ 0, NULL },
};
+static const struct ccu_reset_data apmu_reset_data[] = {
+ [RST_CCIC_4X] = RST_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_CCIC1_PHY] = RST_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)),
+ [RST_SDH_AXI] = RST_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)),
+ [RST_SDH0] = RST_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_SDH1] = RST_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_SDH2] = RST_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_USBP1_AXI] = RST_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(4)),
+ [RST_USB_AXI] = RST_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)),
+ [RST_USB3_0] = RST_DATA(APMU_USB_CLK_RES_CTRL, 0,
+ BIT(9)|BIT(10)|BIT(11)),
+ [RST_QSPI] = RST_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_QSPI_BUS] = RST_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)),
+ [RST_DMA] = RST_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)),
+ [RST_AES] = RST_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)),
+ [RST_VPU] = RST_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)),
+ [RST_GPU] = RST_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_EMMC] = RST_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_EMMC_X] = RST_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(0)),
+ [RST_AUDIO] = RST_DATA(APMU_AUDIO_CLK_RES_CTRL, 0,
+ BIT(0) | BIT(2) | BIT(3)),
+ [RST_HDMI] = RST_DATA(APMU_HDMI_CLK_RES_CTRL, 0, BIT(9)),
+ [RST_PCIE0] = RST_DATA(APMU_PCIE_CLK_RES_CTRL_0, BIT(8),
+ BIT(3) | BIT(4) | BIT(5)),
+ [RST_PCIE1] = RST_DATA(APMU_PCIE_CLK_RES_CTRL_1, BIT(8),
+ BIT(3) | BIT(4) | BIT(5)),
+ [RST_PCIE2] = RST_DATA(APMU_PCIE_CLK_RES_CTRL_2, BIT(8),
+ BIT(3) | BIT(4) | BIT(5)),
+ [RST_EMAC0] = RST_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_EMAC1] = RST_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_JPG] = RST_DATA(APMU_JPG_CLK_RES_CTRL, 0, BIT(0)),
+ [RST_CCIC2PHY] = RST_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)),
+ [RST_CCIC3PHY] = RST_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)),
+ [RST_CSI] = RST_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_ISP] = RST_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(0)),
+ [RST_ISP_CPP] = RST_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(27)),
+ [RST_ISP_BUS] = RST_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(3)),
+ [RST_ISP_CI] = RST_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)),
+ [RST_DPU_MCLK] = RST_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)),
+ [RST_DPU_ESC] = RST_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)),
+ [RST_DPU_HCLK] = RST_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)),
+ [RST_DPU_SPIBUS] = RST_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(4)),
+ [RST_DPU_SPI_HBUS] = RST_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(2)),
+ [RST_V2D] = RST_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)),
+ [RST_MIPI] = RST_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(15)),
+ [RST_MC] = RST_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)),
+};
+
+static const struct ccu_reset_controller_data apmu_reset_controller_data = {
+ .count = ARRAY_SIZE(apmu_reset_data),
+ .data = apmu_reset_data,
+};
+
static const struct k1_ccu_data k1_ccu_apmu_data = {
.clk = k1_ccu_apmu_clks,
+ .rst_data = &apmu_reset_controller_data,
};
static struct ccu_reset_controller *
--
2.43.0
WARNING: multiple messages have this Message-ID (diff)
From: Alex Elder <elder@riscstar.com>
To: p.zabel@pengutronix.de, mturquette@baylibre.com,
sboyd@kernel.org, dlan@gentoo.org
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu,
spacemit@lists.linux.dev, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH RESEND 4/7] clk: spacemit: define existing syscon resets
Date: Fri, 21 Mar 2025 10:18:27 -0500 [thread overview]
Message-ID: <20250321151831.623575-5-elder@riscstar.com> (raw)
In-Reply-To: <20250321151831.623575-1-elder@riscstar.com>
Define reset controls associated with the MPMU, APBC, and APMU
SpacemiT K1 CCUs. These already have clocks associated with them.
Signed-off-by: Alex Elder <elder@riscstar.com>
---
drivers/clk/spacemit/ccu-k1.c | 132 ++++++++++++++++++++++++++++++++++
1 file changed, 132 insertions(+)
diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c
index 6d879411c6c05..be8abd27753cb 100644
--- a/drivers/clk/spacemit/ccu-k1.c
+++ b/drivers/clk/spacemit/ccu-k1.c
@@ -151,6 +151,13 @@ struct k1_ccu_data {
const struct ccu_reset_controller_data *rst_data;
};
+#define RST_DATA(_offset, _assert_mask, _deassert_mask) \
+ { \
+ .offset = (_offset), \
+ .assert_mask = (_assert_mask), \
+ .deassert_mask = (_deassert_mask), \
+ }
+
struct ccu_reset_controller {
struct regmap *regmap;
const struct ccu_reset_controller_data *data;
@@ -1428,6 +1435,7 @@ static struct spacemit_ccu_clk k1_ccu_apbs_clks[] = {
static const struct k1_ccu_data k1_ccu_apbs_data = {
.clk = k1_ccu_apbs_clks,
+ /* No resets in the APBS CCU */
};
static struct spacemit_ccu_clk k1_ccu_mpmu_clks[] = {
@@ -1467,8 +1475,18 @@ static struct spacemit_ccu_clk k1_ccu_mpmu_clks[] = {
{ 0, NULL },
};
+static const struct ccu_reset_data mpmu_reset_data[] = {
+ [RST_WDT] = RST_DATA(MPMU_WDTPCR, BIT(2), 0),
+};
+
+static const struct ccu_reset_controller_data mpmu_reset_controller_data = {
+ .count = ARRAY_SIZE(mpmu_reset_data),
+ .data = mpmu_reset_data,
+};
+
static const struct k1_ccu_data k1_ccu_mpmu_data = {
.clk = k1_ccu_mpmu_clks,
+ .rst_data = &mpmu_reset_controller_data,
};
static struct spacemit_ccu_clk k1_ccu_apbc_clks[] = {
@@ -1575,8 +1593,68 @@ static struct spacemit_ccu_clk k1_ccu_apbc_clks[] = {
{ 0, NULL },
};
+static const struct ccu_reset_data apbc_reset_data[] = {
+ [RST_UART0] = RST_DATA(APBC_UART1_CLK_RST, BIT(2), 0),
+ [RST_UART2] = RST_DATA(APBC_UART2_CLK_RST, BIT(2), 0),
+ [RST_GPIO] = RST_DATA(APBC_GPIO_CLK_RST, BIT(2), 0),
+ [RST_PWM0] = RST_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM1] = RST_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM2] = RST_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM3] = RST_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM4] = RST_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM5] = RST_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM6] = RST_DATA(APBC_PWM6_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM7] = RST_DATA(APBC_PWM7_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM8] = RST_DATA(APBC_PWM8_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM9] = RST_DATA(APBC_PWM9_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM10] = RST_DATA(APBC_PWM10_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM11] = RST_DATA(APBC_PWM11_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM12] = RST_DATA(APBC_PWM12_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM13] = RST_DATA(APBC_PWM13_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM14] = RST_DATA(APBC_PWM14_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM15] = RST_DATA(APBC_PWM15_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM16] = RST_DATA(APBC_PWM16_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM17] = RST_DATA(APBC_PWM17_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM18] = RST_DATA(APBC_PWM18_CLK_RST, BIT(2), BIT(0)),
+ [RST_PWM19] = RST_DATA(APBC_PWM19_CLK_RST, BIT(2), BIT(0)),
+ [RST_SSP3] = RST_DATA(APBC_SSP3_CLK_RST, BIT(2), 0),
+ [RST_UART3] = RST_DATA(APBC_UART3_CLK_RST, BIT(2), 0),
+ [RST_RTC] = RST_DATA(APBC_RTC_CLK_RST, BIT(2), 0),
+ [RST_TWSI0] = RST_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0),
+ [RST_TIMERS1] = RST_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0),
+ [RST_AIB] = RST_DATA(APBC_AIB_CLK_RST, BIT(2), 0),
+ [RST_TIMERS2] = RST_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0),
+ [RST_ONEWIRE] = RST_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0),
+ [RST_SSPA0] = RST_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0),
+ [RST_SSPA1] = RST_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0),
+ [RST_DRO] = RST_DATA(APBC_DRO_CLK_RST, BIT(2), 0),
+ [RST_IR] = RST_DATA(APBC_IR_CLK_RST, BIT(2), 0),
+ [RST_TWSI1] = RST_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0),
+ [RST_TSEN] = RST_DATA(APBC_TSEN_CLK_RST, BIT(2), 0),
+ [RST_TWSI2] = RST_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0),
+ [RST_TWSI4] = RST_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0),
+ [RST_TWSI5] = RST_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0),
+ [RST_TWSI6] = RST_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0),
+ [RST_TWSI7] = RST_DATA(APBC_TWSI7_CLK_RST, BIT(2), 0),
+ [RST_TWSI8] = RST_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0),
+ [RST_IPC_AP2AUD] = RST_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0),
+ [RST_UART4] = RST_DATA(APBC_UART4_CLK_RST, BIT(2), 0),
+ [RST_UART5] = RST_DATA(APBC_UART5_CLK_RST, BIT(2), 0),
+ [RST_UART6] = RST_DATA(APBC_UART6_CLK_RST, BIT(2), 0),
+ [RST_UART7] = RST_DATA(APBC_UART7_CLK_RST, BIT(2), 0),
+ [RST_UART8] = RST_DATA(APBC_UART8_CLK_RST, BIT(2), 0),
+ [RST_UART9] = RST_DATA(APBC_UART9_CLK_RST, BIT(2), 0),
+ [RST_CAN0] = RST_DATA(APBC_CAN0_CLK_RST, BIT(2), 0),
+};
+
+static const struct ccu_reset_controller_data apbc_reset_controller_data = {
+ .count = ARRAY_SIZE(apbc_reset_data),
+ .data = apbc_reset_data,
+};
+
static const struct k1_ccu_data k1_ccu_apbc_data = {
.clk = k1_ccu_apbc_clks,
+ .rst_data = &apbc_reset_controller_data,
};
static struct spacemit_ccu_clk k1_ccu_apmu_clks[] = {
@@ -1645,8 +1723,62 @@ static struct spacemit_ccu_clk k1_ccu_apmu_clks[] = {
{ 0, NULL },
};
+static const struct ccu_reset_data apmu_reset_data[] = {
+ [RST_CCIC_4X] = RST_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_CCIC1_PHY] = RST_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)),
+ [RST_SDH_AXI] = RST_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)),
+ [RST_SDH0] = RST_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_SDH1] = RST_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_SDH2] = RST_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_USBP1_AXI] = RST_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(4)),
+ [RST_USB_AXI] = RST_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)),
+ [RST_USB3_0] = RST_DATA(APMU_USB_CLK_RES_CTRL, 0,
+ BIT(9)|BIT(10)|BIT(11)),
+ [RST_QSPI] = RST_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_QSPI_BUS] = RST_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)),
+ [RST_DMA] = RST_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)),
+ [RST_AES] = RST_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)),
+ [RST_VPU] = RST_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)),
+ [RST_GPU] = RST_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_EMMC] = RST_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_EMMC_X] = RST_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(0)),
+ [RST_AUDIO] = RST_DATA(APMU_AUDIO_CLK_RES_CTRL, 0,
+ BIT(0) | BIT(2) | BIT(3)),
+ [RST_HDMI] = RST_DATA(APMU_HDMI_CLK_RES_CTRL, 0, BIT(9)),
+ [RST_PCIE0] = RST_DATA(APMU_PCIE_CLK_RES_CTRL_0, BIT(8),
+ BIT(3) | BIT(4) | BIT(5)),
+ [RST_PCIE1] = RST_DATA(APMU_PCIE_CLK_RES_CTRL_1, BIT(8),
+ BIT(3) | BIT(4) | BIT(5)),
+ [RST_PCIE2] = RST_DATA(APMU_PCIE_CLK_RES_CTRL_2, BIT(8),
+ BIT(3) | BIT(4) | BIT(5)),
+ [RST_EMAC0] = RST_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_EMAC1] = RST_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_JPG] = RST_DATA(APMU_JPG_CLK_RES_CTRL, 0, BIT(0)),
+ [RST_CCIC2PHY] = RST_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)),
+ [RST_CCIC3PHY] = RST_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)),
+ [RST_CSI] = RST_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)),
+ [RST_ISP] = RST_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(0)),
+ [RST_ISP_CPP] = RST_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(27)),
+ [RST_ISP_BUS] = RST_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(3)),
+ [RST_ISP_CI] = RST_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)),
+ [RST_DPU_MCLK] = RST_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)),
+ [RST_DPU_ESC] = RST_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)),
+ [RST_DPU_HCLK] = RST_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)),
+ [RST_DPU_SPIBUS] = RST_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(4)),
+ [RST_DPU_SPI_HBUS] = RST_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(2)),
+ [RST_V2D] = RST_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)),
+ [RST_MIPI] = RST_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(15)),
+ [RST_MC] = RST_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)),
+};
+
+static const struct ccu_reset_controller_data apmu_reset_controller_data = {
+ .count = ARRAY_SIZE(apmu_reset_data),
+ .data = apmu_reset_data,
+};
+
static const struct k1_ccu_data k1_ccu_apmu_data = {
.clk = k1_ccu_apmu_clks,
+ .rst_data = &apmu_reset_controller_data,
};
static struct ccu_reset_controller *
--
2.43.0
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next prev parent reply other threads:[~2025-03-21 15:18 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-21 15:18 [PATCH RESEND 0/7] clk: spacemit: add K1 reset support Alex Elder
2025-03-21 15:18 ` Alex Elder
2025-03-21 15:18 ` [PATCH RESEND 1/7] dt-bindings: soc: spacemit: define spacemit,k1-ccu resets Alex Elder
2025-03-21 15:18 ` Alex Elder
2025-03-21 20:42 ` Rob Herring
2025-03-21 20:42 ` Rob Herring
2025-03-21 22:25 ` Yixun Lan
2025-03-21 22:25 ` Yixun Lan
2025-03-22 14:27 ` Alex Elder
2025-03-22 14:27 ` Alex Elder
2025-03-22 16:51 ` Yixun Lan
2025-03-22 16:51 ` Yixun Lan
2025-03-21 15:18 ` [PATCH RESEND 2/7] clk: spacemit: define struct k1_ccu_data Alex Elder
2025-03-21 15:18 ` Alex Elder
2025-03-22 15:50 ` Yixun Lan
2025-03-22 15:50 ` Yixun Lan
2025-03-23 12:43 ` Alex Elder
2025-03-23 12:43 ` Alex Elder
2025-03-23 13:04 ` Yixun Lan
2025-03-23 13:04 ` Yixun Lan
2025-03-23 22:30 ` Alex Elder
2025-03-23 22:30 ` Alex Elder
2025-03-28 17:24 ` Alex Elder
2025-03-28 17:24 ` Alex Elder
2025-03-24 11:53 ` Haylen Chu
2025-03-24 11:53 ` Haylen Chu
2025-03-24 12:17 ` Alex Elder
2025-03-24 12:17 ` Alex Elder
2025-03-21 15:18 ` [PATCH RESEND 3/7] clk: spacemit: add reset controller support Alex Elder
2025-03-21 15:18 ` Alex Elder
2025-03-22 16:19 ` Yixun Lan
2025-03-22 16:19 ` Yixun Lan
2025-03-23 13:23 ` Alex Elder
2025-03-23 13:23 ` Alex Elder
2025-03-24 6:40 ` Yixun Lan
2025-03-24 6:40 ` Yixun Lan
2025-03-24 12:20 ` Haylen Chu
2025-03-24 12:20 ` Haylen Chu
2025-03-24 12:52 ` Alex Elder
2025-03-24 12:52 ` Alex Elder
2025-03-21 15:18 ` Alex Elder [this message]
2025-03-21 15:18 ` [PATCH RESEND 4/7] clk: spacemit: define existing syscon resets Alex Elder
2025-03-22 16:29 ` Yixun Lan
2025-03-22 16:29 ` Yixun Lan
2025-03-23 13:23 ` Alex Elder
2025-03-23 13:23 ` Alex Elder
2025-03-24 6:24 ` Yixun Lan
2025-03-24 6:24 ` Yixun Lan
2025-03-21 15:18 ` [PATCH RESEND 5/7] clk: spacemit: make clocks optional Alex Elder
2025-03-21 15:18 ` Alex Elder
2025-03-21 15:18 ` [PATCH RESEND 6/7] clk: spacemit: define new syscons with only resets Alex Elder
2025-03-21 15:18 ` Alex Elder
2025-03-22 16:42 ` Yixun Lan
2025-03-22 16:42 ` Yixun Lan
2025-03-23 13:23 ` Alex Elder
2025-03-23 13:23 ` Alex Elder
2025-03-24 6:21 ` Yixun Lan
2025-03-24 6:21 ` Yixun Lan
2025-03-28 17:24 ` Alex Elder
2025-03-28 17:24 ` Alex Elder
2025-03-21 15:18 ` [PATCH RESEND 7/7] riscv: dts: spacemit: add reset support for the K1 SoC Alex Elder
2025-03-21 15:18 ` Alex Elder
2025-03-22 16:48 ` Yixun Lan
2025-03-22 16:48 ` Yixun Lan
2025-03-23 13:23 ` Alex Elder
2025-03-23 13:23 ` Alex Elder
2025-03-24 6:06 ` Yixun Lan
2025-03-24 6:06 ` Yixun Lan
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