[PATCH V9 00/24] drm: sun4i: add Display Engine 3.3 (DE33) support

[PATCH V9 00/24] drm: sun4i: add Display Engine 3.3 (DE33) support

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

I've spoken with Ryan and he agreed to let me take over this series to
get the display engine working on the Allwinner H616. I've taken his
previous patch series for Display Engine 3.3 and combined it with the
LCD controller patch series. I've also fixed a few additional bugs and
made some changes to the device tree bindings.

Changes since V8:
 - Combined the DE33 [1] series and the LCD [2] series to better track
   all patches necessary to output to an LCD display for the Allwinner
   H700.
 - Added a required LVDS reset as requested here [3].
 - Added compatible strings with a fallback for
   allwinner,sun50i-h616-display-engine, allwinner,sun50i-h616-tcon-top,
   and allwinner,sun50i-h616-sram-c.
 - Added binding documentation for the LCD controller.
 - Renamed the de3_sram device tree node to de33_sram.
 - Corrected the LVDS reset for the LCD controller binding.
 - Removed the PWM pins from the pincontroller bindings, as PWM is not
   yet supported.
 - Reordered the patches so that a binding or a device tree node is not
   referenced before it is defined.

[1] https://lore.kernel.org/linux-sunxi/20250310092345.31708-1-ryan@testtoast.com/
[2] https://lore.kernel.org/linux-sunxi/20250216092827.15444-1-ryan@testtoast.com/
[3] https://lore.kernel.org/linux-sunxi/38669808.XM6RcZxFsP@jernej-laptop/

Chris Morgan (24):
  dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset
  clk: sunxi-ng: h616: Add LVDS reset for LCD TCON
  drm: sun4i: de2/de3: add mixer version enum
  drm: sun4i: de2/de3: refactor mixer initialisation
  drm: sun4i: de2/de3: add generic blender register reference function
  drm: sun4i: de2/de3: use generic register reference function for layer
    configuration
  dt-bindings: allwinner: add H616 DE33 bus binding
  dt-bindings: allwinner: add H616 DE33 clock binding
  dt-bindings: allwinner: add H616 DE33 mixer binding
  clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support
  drm: sun4i: de33: vi_scaler: add Display Engine 3.3 (DE33) support
  drm: sun4i: de33: mixer: add Display Engine 3.3 (DE33) support
  drm: sun4i: de33: mixer: add mixer configuration for the H616
  dt-bindings: allwinner: Add TCON_TOP and TCON_LCD clock/reset defines
  dt-bindings: display: sun4i: Add compatible strings for H616 DE
  dt-bindings: display: sun4i: Add compatible strings for H616 TCON TOP
  dt-bindings: sram: sunxi-sram: Add H616 SRAM C compatible
  dt-bindings: display: Add R40 and H616 display engine compatibles
  drm/sun4i: tcon: Add support for R40 LCD
  arm64: dts: allwinner: h616: add display engine, bus and mixer nodes
  arm64: dts: allwinner: h616: Add TCON nodes to H616 DTSI
  arm64: dts: allwinner: h616: add LCD and LVDS pins
  arm64: dts: allwinner: rg35xx: Add GPIO backlight control
  arm64: dts: allwinner: rg35xx: Enable LCD output

 .../bus/allwinner,sun50i-a64-de2.yaml         |   7 +-
 .../clock/allwinner,sun8i-a83t-de2-clk.yaml   |   1 +
 .../allwinner,sun4i-a10-display-engine.yaml   |  39 +--
 .../display/allwinner,sun4i-a10-tcon.yaml     |  10 +
 .../allwinner,sun8i-a83t-de2-mixer.yaml       |  34 ++-
 .../display/allwinner,sun8i-r40-tcon-top.yaml |  13 +-
 .../allwinner,sun4i-a10-system-control.yaml   |   4 +-
 .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 224 ++++++++++++++++++
 .../sun50i-h700-anbernic-rg35xx-2024.dts      |  64 +++++
 drivers/clk/sunxi-ng/ccu-sun50i-h616.c        |   1 +
 drivers/clk/sunxi-ng/ccu-sun8i-de2.c          |  25 ++
 drivers/gpu/drm/sun4i/sun4i_tcon.c            |   9 +
 drivers/gpu/drm/sun4i/sun8i_csc.c             |   4 +-
 drivers/gpu/drm/sun4i/sun8i_mixer.c           | 168 ++++++++++---
 drivers/gpu/drm/sun4i/sun8i_mixer.h           |  30 ++-
 drivers/gpu/drm/sun4i/sun8i_ui_layer.c        |  27 ++-
 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c       |   2 +-
 drivers/gpu/drm/sun4i/sun8i_vi_layer.c        |  14 +-
 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c       |   6 +-
 include/dt-bindings/clock/sun8i-tcon-top.h    |   2 +
 include/dt-bindings/reset/sun50i-h616-ccu.h   |   1 +
 21 files changed, 597 insertions(+), 88 deletions(-)

-- 
2.43.0

[PATCH V9 01/24] dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Add the required LVDS reset binding for the LCD TCON.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
---
 include/dt-bindings/reset/sun50i-h616-ccu.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h
index 81b1eba2a7f7..ba626f7015b5 100644
--- a/include/dt-bindings/reset/sun50i-h616-ccu.h
+++ b/include/dt-bindings/reset/sun50i-h616-ccu.h
@@ -69,5 +69,6 @@
 #define RST_BUS_GPADC		60
 #define RST_BUS_TCON_LCD0	61
 #define RST_BUS_TCON_LCD1	62
+#define RST_BUS_LVDS		63
 
 #endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */
-- 
2.43.0

[PATCH V9 02/24] clk: sunxi-ng: h616: Add LVDS reset for LCD TCON

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Add the required LVDS reset for the LCD TCON. Note that while this
reset is exposed for the T507, H616, and H700 only the H700 has
an LCD controller.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
---
 drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
index daa462c7d477..955c614830fa 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
@@ -1094,6 +1094,7 @@ static const struct ccu_reset_map sun50i_h616_ccu_resets[] = {
 	[RST_BUS_TCON_LCD1]	= { 0xb7c, BIT(17) },
 	[RST_BUS_TCON_TV0]	= { 0xb9c, BIT(16) },
 	[RST_BUS_TCON_TV1]	= { 0xb9c, BIT(17) },
+	[RST_BUS_LVDS]		= { 0xbac, BIT(16) },
 	[RST_BUS_TVE_TOP]	= { 0xbbc, BIT(16) },
 	[RST_BUS_TVE0]		= { 0xbbc, BIT(17) },
 	[RST_BUS_HDCP]		= { 0xc4c, BIT(16) },
-- 
2.43.0

[PATCH V9 03/24] drm: sun4i: de2/de3: add mixer version enum

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

The Allwinner DE2 and DE3 display engine mixers are currently identified
by a simple boolean flag. This will not scale to support additional DE
variants.

Convert the boolean flag to an enum.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
---
Changelog v5..v6:
- Update struct comment regarding change from is_de3 flag to de_type
---
 drivers/gpu/drm/sun4i/sun8i_csc.c       |  4 ++--
 drivers/gpu/drm/sun4i/sun8i_mixer.c     | 14 ++++++++++++--
 drivers/gpu/drm/sun4i/sun8i_mixer.h     |  4 ++--
 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c |  2 +-
 drivers/gpu/drm/sun4i/sun8i_vi_layer.c  |  8 ++++----
 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c |  4 ++--
 6 files changed, 23 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
index 58480d8e4f70..6f4a2e9c6fca 100644
--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
+++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
@@ -212,7 +212,7 @@ void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
 {
 	u32 base;
 
-	if (mixer->cfg->is_de3) {
+	if (mixer->cfg->de_type == sun8i_mixer_de3) {
 		sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, layer,
 						mode, encoding, range);
 		return;
@@ -228,7 +228,7 @@ void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable)
 {
 	u32 base;
 
-	if (mixer->cfg->is_de3) {
+	if (mixer->cfg->de_type == sun8i_mixer_de3) {
 		sun8i_de3_ccsc_enable(mixer->engine.regs, layer, enable);
 		return;
 	}
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 8b41d33baa30..2252bef19597 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -537,7 +537,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
 	base = sun8i_blender_base(mixer);
 
 	/* Reset registers and disable unused sub-engines */
-	if (mixer->cfg->is_de3) {
+	if (mixer->cfg->de_type == sun8i_mixer_de3) {
 		for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4)
 			regmap_write(mixer->engine.regs, i, 0);
 
@@ -628,6 +628,7 @@ static void sun8i_mixer_remove(struct platform_device *pdev)
 
 static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = {
 	.ccsc		= CCSC_MIXER0_LAYOUT,
+	.de_type	= sun8i_mixer_de2,
 	.scaler_mask	= 0xf,
 	.scanline_yuv	= 2048,
 	.ui_num		= 3,
@@ -636,6 +637,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = {
 
 static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = {
 	.ccsc		= CCSC_MIXER1_LAYOUT,
+	.de_type	= sun8i_mixer_de2,
 	.scaler_mask	= 0x3,
 	.scanline_yuv	= 2048,
 	.ui_num		= 1,
@@ -644,6 +646,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = {
 
 static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
 	.ccsc		= CCSC_MIXER0_LAYOUT,
+	.de_type	= sun8i_mixer_de2,
 	.mod_rate	= 432000000,
 	.scaler_mask	= 0xf,
 	.scanline_yuv	= 2048,
@@ -653,6 +656,7 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
 
 static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
 	.ccsc		= CCSC_MIXER0_LAYOUT,
+	.de_type	= sun8i_mixer_de2,
 	.mod_rate	= 297000000,
 	.scaler_mask	= 0xf,
 	.scanline_yuv	= 2048,
@@ -662,6 +666,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
 
 static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
 	.ccsc		= CCSC_MIXER1_LAYOUT,
+	.de_type	= sun8i_mixer_de2,
 	.mod_rate	= 297000000,
 	.scaler_mask	= 0x3,
 	.scanline_yuv	= 2048,
@@ -670,6 +675,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
 };
 
 static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
+	.de_type = sun8i_mixer_de2,
 	.vi_num = 2,
 	.ui_num = 1,
 	.scaler_mask = 0x3,
@@ -680,6 +686,7 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
 
 static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = {
 	.ccsc		= CCSC_D1_MIXER0_LAYOUT,
+	.de_type	= sun8i_mixer_de2,
 	.mod_rate	= 297000000,
 	.scaler_mask	= 0x3,
 	.scanline_yuv	= 2048,
@@ -689,6 +696,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = {
 
 static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = {
 	.ccsc		= CCSC_MIXER1_LAYOUT,
+	.de_type	= sun8i_mixer_de2,
 	.mod_rate	= 297000000,
 	.scaler_mask	= 0x1,
 	.scanline_yuv	= 1024,
@@ -698,6 +706,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = {
 
 static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = {
 	.ccsc		= CCSC_MIXER0_LAYOUT,
+	.de_type	= sun8i_mixer_de2,
 	.mod_rate	= 297000000,
 	.scaler_mask	= 0xf,
 	.scanline_yuv	= 4096,
@@ -707,6 +716,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = {
 
 static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
 	.ccsc		= CCSC_MIXER1_LAYOUT,
+	.de_type	= sun8i_mixer_de2,
 	.mod_rate	= 297000000,
 	.scaler_mask	= 0x3,
 	.scanline_yuv	= 2048,
@@ -716,7 +726,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
 
 static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = {
 	.ccsc		= CCSC_MIXER0_LAYOUT,
-	.is_de3		= true,
+	.de_type	= sun8i_mixer_de3,
 	.mod_rate	= 600000000,
 	.scaler_mask	= 0xf,
 	.scanline_yuv	= 4096,
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index d7898c9c9cc0..7fe5ce20082a 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -162,7 +162,7 @@ enum {
  * @ccsc: select set of CCSC base addresses from the enumeration above.
  * @mod_rate: module clock rate that needs to be set in order to have
  *	a functional block.
- * @is_de3: true, if this is next gen display engine 3.0, false otherwise.
+ * @de_type: sun8i_mixer_type enum representing the display engine generation.
  * @scaline_yuv: size of a scanline for VI scaler for YUV formats.
  */
 struct sun8i_mixer_cfg {
@@ -214,7 +214,7 @@ engine_to_sun8i_mixer(struct sunxi_engine *engine)
 static inline u32
 sun8i_blender_base(struct sun8i_mixer *mixer)
 {
-	return mixer->cfg->is_de3 ? DE3_BLD_BASE : DE2_BLD_BASE;
+	return mixer->cfg->de_type == sun8i_mixer_de3 ? DE3_BLD_BASE : DE2_BLD_BASE;
 }
 
 static inline u32
diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
index ae0806bccac7..504ffa0971a4 100644
--- a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
@@ -93,7 +93,7 @@ static u32 sun8i_ui_scaler_base(struct sun8i_mixer *mixer, int channel)
 {
 	int vi_num = mixer->cfg->vi_num;
 
-	if (mixer->cfg->is_de3)
+	if (mixer->cfg->de_type == sun8i_mixer_de3)
 		return DE3_VI_SCALER_UNIT_BASE +
 		       DE3_VI_SCALER_UNIT_SIZE * vi_num +
 		       DE3_UI_SCALER_UNIT_SIZE * (channel - vi_num);
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
index 9c09d9c08496..a7a3a75ffd63 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
@@ -25,7 +25,7 @@ static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
 
 	ch_base = sun8i_channel_base(mixer, channel);
 
-	if (mixer->cfg->is_de3) {
+	if (mixer->cfg->de_type >= sun8i_mixer_de3) {
 		mask = SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK |
 		       SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_MASK;
 		val = SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA
@@ -483,7 +483,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
 	if (!layer)
 		return ERR_PTR(-ENOMEM);
 
-	if (mixer->cfg->is_de3) {
+	if (mixer->cfg->de_type >= sun8i_mixer_de3) {
 		formats = sun8i_vi_layer_de3_formats;
 		format_count = ARRAY_SIZE(sun8i_vi_layer_de3_formats);
 	} else {
@@ -507,7 +507,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
 
 	plane_cnt = mixer->cfg->ui_num + mixer->cfg->vi_num;
 
-	if (mixer->cfg->vi_num == 1 || mixer->cfg->is_de3) {
+	if (mixer->cfg->vi_num == 1 || mixer->cfg->de_type >= sun8i_mixer_de3) {
 		ret = drm_plane_create_alpha_property(&layer->plane);
 		if (ret) {
 			dev_err(drm->dev, "Couldn't add alpha property\n");
@@ -524,7 +524,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
 
 	supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) |
 			      BIT(DRM_COLOR_YCBCR_BT709);
-	if (mixer->cfg->is_de3)
+	if (mixer->cfg->de_type >= sun8i_mixer_de3)
 		supported_encodings |= BIT(DRM_COLOR_YCBCR_BT2020);
 
 	supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
index 7ba75011adf9..ad87ab395803 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
@@ -835,7 +835,7 @@ static const u32 bicubic4coefftab32[480] = {
 
 static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel)
 {
-	if (mixer->cfg->is_de3)
+	if (mixer->cfg->de_type == sun8i_mixer_de3)
 		return DE3_VI_SCALER_UNIT_BASE +
 		       DE3_VI_SCALER_UNIT_SIZE * channel;
 	else
@@ -956,7 +956,7 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
 		cvphase = vphase;
 	}
 
-	if (mixer->cfg->is_de3) {
+	if (mixer->cfg->de_type >= sun8i_mixer_de3) {
 		u32 val;
 
 		if (format->hsub == 1 && format->vsub == 1)
-- 
2.43.0

[PATCH V9 04/24] drm: sun4i: de2/de3: refactor mixer initialisation

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Now that the DE variant can be selected by enum, take the oppportunity
to factor out some common initialisation code to a separate function.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
---
Changelog v1..v2:
- Combine base register allocation and initialisation in
  sun8i_mixer_init
- Whitespace fix

Changelog v4..v5:
- Remove trailing whitespace

Changelog v7..v8:
- Remove CSC configuration changes (logically better placed with future
  YUV support) making this the first patch in the series.
---
 drivers/gpu/drm/sun4i/sun8i_mixer.c | 64 +++++++++++++++--------------
 1 file changed, 34 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 2252bef19597..41815b42d6d2 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -425,6 +425,38 @@ static int sun8i_mixer_of_get_id(struct device_node *node)
 	return of_ep.id;
 }
 
+static void sun8i_mixer_init(struct sun8i_mixer *mixer)
+{
+	unsigned int base = sun8i_blender_base(mixer);
+	int plane_cnt, i;
+
+	/* Enable the mixer */
+	regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
+		     SUN8I_MIXER_GLOBAL_CTL_RT_EN);
+
+	/* Set background color to black */
+	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
+		     SUN8I_MIXER_BLEND_COLOR_BLACK);
+
+	/*
+	 * Set fill color of bottom plane to black. Generally not needed
+	 * except when VI plane is at bottom (zpos = 0) and enabled.
+	 */
+	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
+		     SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
+	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
+		     SUN8I_MIXER_BLEND_COLOR_BLACK);
+
+	plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
+	for (i = 0; i < plane_cnt; i++)
+		regmap_write(mixer->engine.regs,
+			     SUN8I_MIXER_BLEND_MODE(base, i),
+			     SUN8I_MIXER_BLEND_MODE_DEF);
+
+	regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
+			   SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
+}
+
 static int sun8i_mixer_bind(struct device *dev, struct device *master,
 			      void *data)
 {
@@ -433,8 +465,6 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
 	struct sun4i_drv *drv = drm->dev_private;
 	struct sun8i_mixer *mixer;
 	void __iomem *regs;
-	unsigned int base;
-	int plane_cnt;
 	int i, ret;
 
 	/*
@@ -534,8 +564,6 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
 
 	list_add_tail(&mixer->engine.list, &drv->engine_list);
 
-	base = sun8i_blender_base(mixer);
-
 	/* Reset registers and disable unused sub-engines */
 	if (mixer->cfg->de_type == sun8i_mixer_de3) {
 		for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4)
@@ -551,7 +579,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
 		regmap_write(mixer->engine.regs, SUN50I_MIXER_FMT_EN, 0);
 		regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC0_EN, 0);
 		regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC1_EN, 0);
-	} else {
+	} else if (mixer->cfg->de_type == sun8i_mixer_de2) {
 		for (i = 0; i < DE2_MIXER_UNIT_SIZE; i += 4)
 			regmap_write(mixer->engine.regs, i, 0);
 
@@ -564,31 +592,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
 		regmap_write(mixer->engine.regs, SUN8I_MIXER_DCSC_EN, 0);
 	}
 
-	/* Enable the mixer */
-	regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
-		     SUN8I_MIXER_GLOBAL_CTL_RT_EN);
-
-	/* Set background color to black */
-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
-		     SUN8I_MIXER_BLEND_COLOR_BLACK);
-
-	/*
-	 * Set fill color of bottom plane to black. Generally not needed
-	 * except when VI plane is at bottom (zpos = 0) and enabled.
-	 */
-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
-		     SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
-		     SUN8I_MIXER_BLEND_COLOR_BLACK);
-
-	plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
-	for (i = 0; i < plane_cnt; i++)
-		regmap_write(mixer->engine.regs,
-			     SUN8I_MIXER_BLEND_MODE(base, i),
-			     SUN8I_MIXER_BLEND_MODE_DEF);
-
-	regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
-			   SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
+	sun8i_mixer_init(mixer);
 
 	return 0;
 
-- 
2.43.0

[PATCH V9 05/24] drm: sun4i: de2/de3: add generic blender register reference function

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

The DE2 and DE3 engines have a blender register range within the
mixer engine register map, whereas the DE33 separates this out into
a separate display group.

Prepare for this by adding a function to look the blender reference up,
with a subsequent patch to add a conditional based on the DE type.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 drivers/gpu/drm/sun4i/sun8i_mixer.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index 7fe5ce20082a..43c413052a22 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -217,6 +217,12 @@ sun8i_blender_base(struct sun8i_mixer *mixer)
 	return mixer->cfg->de_type == sun8i_mixer_de3 ? DE3_BLD_BASE : DE2_BLD_BASE;
 }
 
+static inline struct regmap *
+sun8i_blender_regmap(struct sun8i_mixer *mixer)
+{
+	return mixer->engine.regs;
+}
+
 static inline u32
 sun8i_channel_base(struct sun8i_mixer *mixer, int channel)
 {
-- 
2.43.0

[PATCH V9 06/24] drm: sun4i: de2/de3: use generic register reference function for layer configuration

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Use the new blender register lookup function where required in the layer
commit and update code.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
Changelog v2..v3:
- Refactor for 6.11 layer init/modesetting changes
---
 drivers/gpu/drm/sun4i/sun8i_mixer.c    | 5 +++--
 drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 7 +++++--
 drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 6 ++++--
 3 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 41815b42d6d2..cc4da11e2c10 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -274,6 +274,7 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
 {
 	struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
 	u32 bld_base = sun8i_blender_base(mixer);
+	struct regmap *bld_regs = sun8i_blender_regmap(mixer);
 	struct drm_plane_state *plane_state;
 	struct drm_plane *plane;
 	u32 route = 0, pipe_en = 0;
@@ -313,8 +314,8 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
 		pipe_en |= SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
 	}
 
-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ROUTE(bld_base), route);
-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+	regmap_write(bld_regs, SUN8I_MIXER_BLEND_ROUTE(bld_base), route);
+	regmap_write(bld_regs, SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
 		     pipe_en | SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
 
 	regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
index b90e5edef4e8..7a21d32ff1e4 100644
--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
@@ -23,6 +23,7 @@
 #include "sun8i_mixer.h"
 #include "sun8i_ui_layer.h"
 #include "sun8i_ui_scaler.h"
+#include "sun8i_vi_scaler.h"
 
 static void sun8i_ui_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
 					int overlay, struct drm_plane *plane)
@@ -51,6 +52,7 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
 {
 	struct drm_plane_state *state = plane->state;
 	u32 src_w, src_h, dst_w, dst_h;
+	struct regmap *bld_regs;
 	u32 bld_base, ch_base;
 	u32 outsize, insize;
 	u32 hphase, vphase;
@@ -59,6 +61,7 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
 			 channel, overlay);
 
 	bld_base = sun8i_blender_base(mixer);
+	bld_regs = sun8i_blender_regmap(mixer);
 	ch_base = sun8i_channel_base(mixer, channel);
 
 	src_w = drm_rect_width(&state->src) >> 16;
@@ -103,10 +106,10 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
 	DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
 			 state->dst.x1, state->dst.y1);
 	DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
-	regmap_write(mixer->engine.regs,
+	regmap_write(bld_regs,
 		     SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
 		     SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
-	regmap_write(mixer->engine.regs,
+	regmap_write(bld_regs,
 		     SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
 		     outsize);
 
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
index a7a3a75ffd63..3d81d23d0195 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
@@ -55,6 +55,7 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
 	struct drm_plane_state *state = plane->state;
 	const struct drm_format_info *format = state->fb->format;
 	u32 src_w, src_h, dst_w, dst_h;
+	struct regmap *bld_regs;
 	u32 bld_base, ch_base;
 	u32 outsize, insize;
 	u32 hphase, vphase;
@@ -66,6 +67,7 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
 			 channel, overlay);
 
 	bld_base = sun8i_blender_base(mixer);
+	bld_regs = sun8i_blender_regmap(mixer);
 	ch_base = sun8i_channel_base(mixer, channel);
 
 	src_w = drm_rect_width(&state->src) >> 16;
@@ -183,10 +185,10 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
 	DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
 			 state->dst.x1, state->dst.y1);
 	DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
-	regmap_write(mixer->engine.regs,
+	regmap_write(bld_regs,
 		     SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
 		     SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
-	regmap_write(mixer->engine.regs,
+	regmap_write(bld_regs,
 		     SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
 		     outsize);
 
-- 
2.43.0

[PATCH V9 07/24] dt-bindings: allwinner: add H616 DE33 bus binding

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

The Allwinner H616 and variants have a new display engine revision
(DE33).

Add a display engine bus binding for the DE33. Note that the DE33
requires 3 register blocks instead of 1. To keep things simple
remove the maxItems value for registers for the child nodes and instead
rely on the bindings for the child nodes such as
allwinner,sun8i-a83t-de2-mixer.yaml to enforce the max values.

Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
Changelog v1..v2:
- Correct DE2 bus enum to reflect fallback devices accurately.

Changelog v2..v3:
- Separate content into three patches for three separate subsystems

Changelog v5..v6:
- Increase reg maxItems to 3.

Changelog v8..v9:
- Remove maxItems from child nodes completely and rely on bindings for
  child nodes to enforce maxItems.
- Remove reviewed and acked tags due to changes made.
---
 .../devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml  | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml b/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml
index 9845a187bdf6..9d9418c40b95 100644
--- a/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml
+++ b/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml
@@ -24,7 +24,9 @@ properties:
     oneOf:
       - const: allwinner,sun50i-a64-de2
       - items:
-          - const: allwinner,sun50i-h6-de3
+          - enum:
+              - allwinner,sun50i-h6-de3
+              - allwinner,sun50i-h616-de33
           - const: allwinner,sun50i-a64-de2
 
   reg:
@@ -47,9 +49,6 @@ patternProperties:
   "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-fA-F]+$":
     type: object
     additionalProperties: true
-    properties:
-      reg:
-        maxItems: 1
 
     required:
       - reg
-- 
2.43.0

[PATCH V9 08/24] dt-bindings: allwinner: add H616 DE33 clock binding

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

The Allwinner H616 and variants have a new display engine revision
(DE33).

Add a clock binding for the DE33.

Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
Changelog v2..v3:
- Separate content into three patches for three separate subsystems
---
 .../devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml  | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml
index 70369bd633e4..7fcd55d468d4 100644
--- a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml
+++ b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml
@@ -25,6 +25,7 @@ properties:
       - const: allwinner,sun50i-a64-de2-clk
       - const: allwinner,sun50i-h5-de2-clk
       - const: allwinner,sun50i-h6-de3-clk
+      - const: allwinner,sun50i-h616-de33-clk
       - items:
           - const: allwinner,sun8i-r40-de2-clk
           - const: allwinner,sun8i-h3-de2-clk
-- 
2.43.0

[PATCH V9 09/24] dt-bindings: allwinner: add H616 DE33 mixer binding

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

The Allwinner H616 and variants have a new display engine revision
(DE33).

The mixer configuration registers are significantly different to the DE3
and DE2 revisions, being split into separate top and display blocks,
therefore a fallback for the mixer compatible is not provided.

Add a display engine mixer binding for the DE33.

Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
Changelog v2..v3:
- Separate content into three patches for three separate subsystems

Changelog v5..v6:
- Increase reg maxItems to 3 and add conditional for h616-de33

Changelog v8..v9:
- Correct conditional logic for reg items as it was not working for me
  when using dtbs_check
- Add reg-names property and description for the registers used by the
  DE33 mixer
- Removed Acked and Reviewed tags so that change can be re-reviewed.
---
 .../allwinner,sun8i-a83t-de2-mixer.yaml       | 34 +++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml
index b75c1ec686ad..cbd18fd83e52 100644
--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml
+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml
@@ -24,9 +24,11 @@ properties:
       - allwinner,sun50i-a64-de2-mixer-0
       - allwinner,sun50i-a64-de2-mixer-1
       - allwinner,sun50i-h6-de3-mixer-0
+      - allwinner,sun50i-h616-de33-mixer-0
 
-  reg:
-    maxItems: 1
+  reg: true
+
+  reg-names: true
 
   clocks:
     items:
@@ -61,6 +63,34 @@ properties:
     required:
       - port@1
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - allwinner,sun50i-h616-de33-mixer-0
+    then:
+      properties:
+        reg:
+          description: |
+            Registers for controlling individual layers of the display
+            engine (layers), global control (top), and display blending
+            control (display). Names are from Allwinner BSP kernel.
+          maxItems: 3
+        reg-names:
+          items:
+            - const: layers
+            - const: top
+            - const: display
+      required:
+        - reg-names
+
+    else:
+      properties:
+        reg:
+          maxItems: 1
+
 required:
   - compatible
   - reg
-- 
2.43.0

[PATCH V9 10/24] clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

The DE33 is a newer version of the Allwinner Display Engine IP block,
found in the H616, H618, H700 and T507 SoCs. DE2 and DE3 are already
supported by the mainline driver.

The DE33 in the H616 has mixer0 and writeback units. The clocks
and resets required are identical to the H3 and H5 respectively, so use
those existing structs for the H616 description.

There are two additional 32-bit registers (at offsets 0x24 and 0x28)
which require clearing and setting respectively to bring up the
hardware. The function of these registers is currently unknown, and the
values are taken from the out-of-tree driver.

Add the required clock description struct and compatible string to the
DE2 driver.

Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
Changelog v2..v3:
- Lowercase hex value

Changelog v2..v3:
- Correct #include for writel()

Changelog v4..v5:
- Whitespace fix
---
 drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index f2aa71206bc2..a6cd0f988859 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -5,6 +5,7 @@
 
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
+#include <linux/io.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
@@ -239,6 +240,16 @@ static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
 	.num_resets	= ARRAY_SIZE(sun50i_h5_de2_resets),
 };
 
+static const struct sunxi_ccu_desc sun50i_h616_de33_clk_desc = {
+	.ccu_clks	= sun8i_de2_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_de2_ccu_clks),
+
+	.hw_clks	= &sun8i_h3_de2_hw_clks,
+
+	.resets		= sun50i_h5_de2_resets,
+	.num_resets	= ARRAY_SIZE(sun50i_h5_de2_resets),
+};
+
 static int sunxi_de2_clk_probe(struct platform_device *pdev)
 {
 	struct clk *bus_clk, *mod_clk;
@@ -291,6 +302,16 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev)
 		goto err_disable_mod_clk;
 	}
 
+	/*
+	 * The DE33 requires these additional (unknown) registers set
+	 * during initialisation.
+	 */
+	if (of_device_is_compatible(pdev->dev.of_node,
+				    "allwinner,sun50i-h616-de33-clk")) {
+		writel(0, reg + 0x24);
+		writel(0x0000a980, reg + 0x28);
+	}
+
 	ret = devm_sunxi_ccu_probe(&pdev->dev, reg, ccu_desc);
 	if (ret)
 		goto err_assert_reset;
@@ -335,6 +356,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
 		.compatible = "allwinner,sun50i-h6-de3-clk",
 		.data = &sun50i_h5_de2_clk_desc,
 	},
+	{
+		.compatible = "allwinner,sun50i-h616-de33-clk",
+		.data = &sun50i_h616_de33_clk_desc,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, sunxi_de2_clk_ids);
-- 
2.43.0

[PATCH V9 11/24] drm: sun4i: de33: vi_scaler: add Display Engine 3.3 (DE33) support

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

The vi_scaler appears to be used in preference to the ui_scaler module
for hardware video scaling in the DE33.

Enable support for this scaler.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 drivers/gpu/drm/sun4i/sun8i_ui_layer.c  | 20 ++++++++++++++++----
 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c |  4 +++-
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
index 7a21d32ff1e4..3eefdb710dee 100644
--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
@@ -94,12 +94,24 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
 		hscale = state->src_w / state->crtc_w;
 		vscale = state->src_h / state->crtc_h;
 
-		sun8i_ui_scaler_setup(mixer, channel, src_w, src_h, dst_w,
-				      dst_h, hscale, vscale, hphase, vphase);
-		sun8i_ui_scaler_enable(mixer, channel, true);
+		if (mixer->cfg->de_type == sun8i_mixer_de33) {
+			sun8i_vi_scaler_setup(mixer, channel, src_w, src_h,
+					      dst_w, dst_h, hscale, vscale,
+					      hphase, vphase,
+					      state->fb->format);
+			sun8i_vi_scaler_enable(mixer, channel, true);
+		} else {
+			sun8i_ui_scaler_setup(mixer, channel, src_w, src_h,
+					      dst_w, dst_h, hscale, vscale,
+					      hphase, vphase);
+			sun8i_ui_scaler_enable(mixer, channel, true);
+		}
 	} else {
 		DRM_DEBUG_DRIVER("HW scaling is not needed\n");
-		sun8i_ui_scaler_enable(mixer, channel, false);
+		if (mixer->cfg->de_type == sun8i_mixer_de33)
+			sun8i_vi_scaler_enable(mixer, channel, false);
+		else
+			sun8i_ui_scaler_enable(mixer, channel, false);
 	}
 
 	/* Set base coordinates */
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
index ad87ab395803..6839fd5ab602 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
@@ -835,7 +835,9 @@ static const u32 bicubic4coefftab32[480] = {
 
 static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel)
 {
-	if (mixer->cfg->de_type == sun8i_mixer_de3)
+	if (mixer->cfg->de_type == sun8i_mixer_de33)
+		return sun8i_channel_base(mixer, channel) + 0x3000;
+	else if (mixer->cfg->de_type == sun8i_mixer_de3)
 		return DE3_VI_SCALER_UNIT_BASE +
 		       DE3_VI_SCALER_UNIT_SIZE * channel;
 	else
-- 
2.43.0

[PATCH V9 12/24] drm: sun4i: de33: mixer: add Display Engine 3.3 (DE33) support

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

The DE33 is a newer version of the Allwinner Display Engine IP block,
found in the H616, H618, H700 and T507 SoCs. DE2 and DE3 are already
supported by the mainline driver.

Notable features (from the H616 datasheet and implemented):
- 4096 x 2048 (4K) output support

Other features (implemented but not in this patchset):
- AFBC ARM Frame Buffer Compression support
- YUV pipeline support

The DE2 and DE3 engines have a blender register range within the
mixer engine register map, whereas the DE33 separates this out into
a separate display group, and adds a top register map.

The DE33 also appears to remove the global double buffer control
register, present in the DE2 and DE3.

Extend the mixer to support the DE33.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
Changelog v4..v5:
- Whitespace fixes
- Correct strict mode warnings from checkpatch.pl

Changelog v7..v8:
- Add top/disp regmaps to mixer for DE33
- Remove YUV-specific code
- Remove use of global double buffer
- Remove unneeded if/then parentheses and fix an alignment issue as
  suggested by checkpatch.pl

Changelog v8..v9:
- Change devm_platform_ioremap_resource() for the 2nd and 3rd register
  set to devm_platform_ioremap_resource_byname() since we now are
  enforcing reg-names in the device tree.
---
 drivers/gpu/drm/sun4i/sun8i_mixer.c | 82 +++++++++++++++++++++++++----
 drivers/gpu/drm/sun4i/sun8i_mixer.h | 22 ++++++--
 2 files changed, 90 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index cc4da11e2c10..0d4695132dae 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -318,8 +318,9 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
 	regmap_write(bld_regs, SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
 		     pipe_en | SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
 
-	regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
-		     SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
+	if (mixer->cfg->de_type != sun8i_mixer_de33)
+		regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
+			     SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
 }
 
 static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
@@ -368,25 +369,31 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine,
 				 const struct drm_display_mode *mode)
 {
 	struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
+	struct regmap *bld_regs;
 	u32 bld_base, size, val;
 	bool interlaced;
 
 	bld_base = sun8i_blender_base(mixer);
+	bld_regs = sun8i_blender_regmap(mixer);
 	interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
 	size = SUN8I_MIXER_SIZE(mode->hdisplay, mode->vdisplay);
 
 	DRM_DEBUG_DRIVER("Updating global size W: %u H: %u\n",
 			 mode->hdisplay, mode->vdisplay);
 
-	regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_SIZE, size);
-	regmap_write(engine->regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size);
+	if (mixer->cfg->de_type == sun8i_mixer_de33)
+		regmap_write(mixer->top_regs, SUN50I_MIXER_GLOBAL_SIZE, size);
+	else
+		regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_SIZE, size);
+
+	regmap_write(bld_regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size);
 
 	if (interlaced)
 		val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED;
 	else
 		val = 0;
 
-	regmap_update_bits(engine->regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base),
+	regmap_update_bits(bld_regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base),
 			   SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, val);
 
 	DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n",
@@ -400,12 +407,29 @@ static const struct sunxi_engine_ops sun8i_engine_ops = {
 };
 
 static const struct regmap_config sun8i_mixer_regmap_config = {
+	.name		= "layers",
 	.reg_bits	= 32,
 	.val_bits	= 32,
 	.reg_stride	= 4,
 	.max_register	= 0xffffc, /* guessed */
 };
 
+static const struct regmap_config sun8i_top_regmap_config = {
+	.name		= "top",
+	.reg_bits	= 32,
+	.val_bits	= 32,
+	.reg_stride	= 4,
+	.max_register	= 0x3c,
+};
+
+static const struct regmap_config sun8i_disp_regmap_config = {
+	.name		= "display",
+	.reg_bits	= 32,
+	.val_bits	= 32,
+	.reg_stride	= 4,
+	.max_register	= 0x20000,
+};
+
 static int sun8i_mixer_of_get_id(struct device_node *node)
 {
 	struct device_node *ep, *remote;
@@ -428,33 +452,45 @@ static int sun8i_mixer_of_get_id(struct device_node *node)
 
 static void sun8i_mixer_init(struct sun8i_mixer *mixer)
 {
+	struct regmap *top_regs, *disp_regs;
 	unsigned int base = sun8i_blender_base(mixer);
 	int plane_cnt, i;
 
+	if (mixer->cfg->de_type == sun8i_mixer_de33) {
+		top_regs = mixer->top_regs;
+		disp_regs = mixer->disp_regs;
+	} else {
+		top_regs = mixer->engine.regs;
+		disp_regs = mixer->engine.regs;
+	}
+
 	/* Enable the mixer */
-	regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
+	regmap_write(top_regs, SUN8I_MIXER_GLOBAL_CTL,
 		     SUN8I_MIXER_GLOBAL_CTL_RT_EN);
 
+	if (mixer->cfg->de_type == sun8i_mixer_de33)
+		regmap_write(top_regs, SUN50I_MIXER_GLOBAL_CLK, 1);
+
 	/* Set background color to black */
-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
+	regmap_write(disp_regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
 		     SUN8I_MIXER_BLEND_COLOR_BLACK);
 
 	/*
 	 * Set fill color of bottom plane to black. Generally not needed
 	 * except when VI plane is at bottom (zpos = 0) and enabled.
 	 */
-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
+	regmap_write(disp_regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
 		     SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
+	regmap_write(disp_regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
 		     SUN8I_MIXER_BLEND_COLOR_BLACK);
 
 	plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
 	for (i = 0; i < plane_cnt; i++)
-		regmap_write(mixer->engine.regs,
+		regmap_write(disp_regs,
 			     SUN8I_MIXER_BLEND_MODE(base, i),
 			     SUN8I_MIXER_BLEND_MODE_DEF);
 
-	regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
+	regmap_update_bits(disp_regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
 			   SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
 }
 
@@ -526,6 +562,30 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
 		return PTR_ERR(mixer->engine.regs);
 	}
 
+	if (mixer->cfg->de_type == sun8i_mixer_de33) {
+		regs = devm_platform_ioremap_resource_byname(pdev, "top");
+		if (IS_ERR(regs))
+			return PTR_ERR(regs);
+
+		mixer->top_regs = devm_regmap_init_mmio(dev, regs,
+							&sun8i_top_regmap_config);
+		if (IS_ERR(mixer->top_regs)) {
+			dev_err(dev, "Couldn't create the top regmap\n");
+			return PTR_ERR(mixer->top_regs);
+		}
+
+		regs = devm_platform_ioremap_resource_byname(pdev, "display");
+		if (IS_ERR(regs))
+			return PTR_ERR(regs);
+
+		mixer->disp_regs = devm_regmap_init_mmio(dev, regs,
+							 &sun8i_disp_regmap_config);
+		if (IS_ERR(mixer->disp_regs)) {
+			dev_err(dev, "Couldn't create the disp regmap\n");
+			return PTR_ERR(mixer->disp_regs);
+		}
+	}
+
 	mixer->reset = devm_reset_control_get(dev, NULL);
 	if (IS_ERR(mixer->reset)) {
 		dev_err(dev, "Couldn't get our reset line\n");
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index 43c413052a22..d87d197610e1 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -21,6 +21,9 @@
 #define SUN8I_MIXER_GLOBAL_DBUFF		0x8
 #define SUN8I_MIXER_GLOBAL_SIZE			0xc
 
+#define SUN50I_MIXER_GLOBAL_SIZE		0x8
+#define SUN50I_MIXER_GLOBAL_CLK			0xc
+
 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN		BIT(0)
 
 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE		BIT(0)
@@ -151,6 +154,12 @@ enum {
 	CCSC_D1_MIXER0_LAYOUT,
 };
 
+enum sun8i_mixer_type {
+	sun8i_mixer_de2,
+	sun8i_mixer_de3,
+	sun8i_mixer_de33,
+};
+
 /**
  * struct sun8i_mixer_cfg - mixer HW configuration
  * @vi_num: number of VI channels
@@ -171,8 +180,9 @@ struct sun8i_mixer_cfg {
 	int		scaler_mask;
 	int		ccsc;
 	unsigned long	mod_rate;
-	unsigned int	is_de3 : 1;
+	unsigned int	de_type;
 	unsigned int	scanline_yuv;
+	unsigned int	map[6];
 };
 
 struct sun8i_mixer {
@@ -184,6 +194,9 @@ struct sun8i_mixer {
 
 	struct clk			*bus_clk;
 	struct clk			*mod_clk;
+
+	struct regmap			*top_regs;
+	struct regmap			*disp_regs;
 };
 
 enum {
@@ -220,13 +233,16 @@ sun8i_blender_base(struct sun8i_mixer *mixer)
 static inline struct regmap *
 sun8i_blender_regmap(struct sun8i_mixer *mixer)
 {
-	return mixer->engine.regs;
+	return mixer->cfg->de_type == sun8i_mixer_de33 ?
+		mixer->disp_regs : mixer->engine.regs;
 }
 
 static inline u32
 sun8i_channel_base(struct sun8i_mixer *mixer, int channel)
 {
-	if (mixer->cfg->is_de3)
+	if (mixer->cfg->de_type == sun8i_mixer_de33)
+		return mixer->cfg->map[channel] * 0x20000 + DE2_CH_SIZE;
+	else if (mixer->cfg->de_type == sun8i_mixer_de3)
 		return DE3_CH_BASE + channel * DE3_CH_SIZE;
 	else
 		return DE2_CH_BASE + channel * DE2_CH_SIZE;
-- 
2.43.0

[PATCH V9 13/24] drm: sun4i: de33: mixer: add mixer configuration for the H616

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

The H616 (and related SoC packages sharing the same die) carry the new
DE33 display engine.

Add the mixer configuration and a compatible string for the H616 to the
mixer.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
Changelog v7..v8:
- Separate DE33 support and H616 enablement in the mixer.
---
 drivers/gpu/drm/sun4i/sun8i_mixer.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 0d4695132dae..f774b693634d 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -799,6 +799,17 @@ static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = {
 	.vi_num		= 1,
 };
 
+static const struct sun8i_mixer_cfg sun50i_h616_mixer0_cfg = {
+	.ccsc		= CCSC_MIXER0_LAYOUT,
+	.de_type	= sun8i_mixer_de33,
+	.mod_rate	= 600000000,
+	.scaler_mask	= 0xf,
+	.scanline_yuv	= 4096,
+	.ui_num		= 3,
+	.vi_num		= 1,
+	.map		= {0, 6, 7, 8},
+};
+
 static const struct of_device_id sun8i_mixer_of_table[] = {
 	{
 		.compatible = "allwinner,sun8i-a83t-de2-mixer-0",
@@ -844,6 +855,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
 		.compatible = "allwinner,sun50i-h6-de3-mixer-0",
 		.data = &sun50i_h6_mixer0_cfg,
 	},
+	{
+		.compatible = "allwinner,sun50i-h616-de33-mixer-0",
+		.data = &sun50i_h616_mixer0_cfg,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
-- 
2.43.0

[PATCH V9 14/24] dt-bindings: allwinner: Add TCON_TOP and TCON_LCD clock/reset defines

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

The Allwinner H700 exposes RGB and LVDS pins as well as a HDMI
connector. This requires additional clocks for the TCON_TOP and clock
and resets for the TCON_LCD LCD controllers to be defined as per the
T507 datasheet (which shares the same die).

Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 include/dt-bindings/clock/sun8i-tcon-top.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/sun8i-tcon-top.h b/include/dt-bindings/clock/sun8i-tcon-top.h
index 25164d767835..2a12d047d2e1 100644
--- a/include/dt-bindings/clock/sun8i-tcon-top.h
+++ b/include/dt-bindings/clock/sun8i-tcon-top.h
@@ -7,5 +7,7 @@
 #define CLK_TCON_TOP_TV0	0
 #define CLK_TCON_TOP_TV1	1
 #define CLK_TCON_TOP_DSI	2
+#define CLK_TCON_TOP_LCD0	3
+#define CLK_TCON_TOP_LCD1	4
 
 #endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */
-- 
2.43.0

[PATCH V9 15/24] dt-bindings: display: sun4i: Add compatible strings for H616 DE

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Add compatible strings for allwinner,sun50i-h616-display-engine. The
device is functionally identical to the
allwinner,sun50i-h6-display-engine.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 .../allwinner,sun4i-a10-display-engine.yaml   | 39 +++++++++++--------
 1 file changed, 22 insertions(+), 17 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml
index e6088f379f70..81a173b41534 100644
--- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml
+++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml
@@ -48,23 +48,28 @@ description: |
 
 properties:
   compatible:
-    enum:
-      - allwinner,sun4i-a10-display-engine
-      - allwinner,sun5i-a10s-display-engine
-      - allwinner,sun5i-a13-display-engine
-      - allwinner,sun6i-a31-display-engine
-      - allwinner,sun6i-a31s-display-engine
-      - allwinner,sun7i-a20-display-engine
-      - allwinner,sun8i-a23-display-engine
-      - allwinner,sun8i-a33-display-engine
-      - allwinner,sun8i-a83t-display-engine
-      - allwinner,sun8i-h3-display-engine
-      - allwinner,sun8i-r40-display-engine
-      - allwinner,sun8i-v3s-display-engine
-      - allwinner,sun9i-a80-display-engine
-      - allwinner,sun20i-d1-display-engine
-      - allwinner,sun50i-a64-display-engine
-      - allwinner,sun50i-h6-display-engine
+    oneOf:
+      - enum:
+          - allwinner,sun4i-a10-display-engine
+          - allwinner,sun5i-a10s-display-engine
+          - allwinner,sun5i-a13-display-engine
+          - allwinner,sun6i-a31-display-engine
+          - allwinner,sun6i-a31s-display-engine
+          - allwinner,sun7i-a20-display-engine
+          - allwinner,sun8i-a23-display-engine
+          - allwinner,sun8i-a33-display-engine
+          - allwinner,sun8i-a83t-display-engine
+          - allwinner,sun8i-h3-display-engine
+          - allwinner,sun8i-r40-display-engine
+          - allwinner,sun8i-v3s-display-engine
+          - allwinner,sun9i-a80-display-engine
+          - allwinner,sun20i-d1-display-engine
+          - allwinner,sun50i-a64-display-engine
+          - allwinner,sun50i-h6-display-engine
+      - items:
+          - enum:
+              - allwinner,sun50i-h616-display-engine
+          - const: allwinner,sun50i-h6-display-engine
 
   allwinner,pipelines:
     $ref: /schemas/types.yaml#/definitions/phandle-array
-- 
2.43.0

[PATCH V9 16/24] dt-bindings: display: sun4i: Add compatible strings for H616 TCON TOP

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Add compatible string for allwinner,sun50i-h616-tcon-top with a
fallback string of allwinner,sun50i-h6-tcon-top.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 .../display/allwinner,sun8i-r40-tcon-top.yaml       | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml
index 7d849c4095a3..80f1e49f5b7a 100644
--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml
+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml
@@ -39,10 +39,15 @@ properties:
     const: 1
 
   compatible:
-    enum:
-      - allwinner,sun8i-r40-tcon-top
-      - allwinner,sun20i-d1-tcon-top
-      - allwinner,sun50i-h6-tcon-top
+    oneOf:
+      - enum:
+          - allwinner,sun8i-r40-tcon-top
+          - allwinner,sun20i-d1-tcon-top
+          - allwinner,sun50i-h6-tcon-top
+      - items:
+          - enum:
+              - allwinner,sun50i-h616-tcon-top
+          - const: allwinner,sun50i-h6-tcon-top
 
   reg:
     maxItems: 1
-- 
2.43.0

[PATCH V9 17/24] dt-bindings: sram: sunxi-sram: Add H616 SRAM C compatible

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Add a compatible string for the H616 SRAM C region which is
functionally similar to the A64 SRAM C region.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 .../bindings/sram/allwinner,sun4i-a10-system-control.yaml     | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
index a7236f7db4ec..976d3320c803 100644
--- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
+++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
@@ -102,7 +102,9 @@ patternProperties:
                       - allwinner,sun7i-a20-sram-d
                   - const: allwinner,sun4i-a10-sram-d
               - items:
-                  - const: allwinner,sun50i-h6-sram-c
+                  - enum:
+                      - allwinner,sun50i-h6-sram-c
+                      - allwinner,sun50i-h616-sram-c
                   - const: allwinner,sun50i-a64-sram-c
 
 required:
-- 
2.43.0

[PATCH V9 18/24] dt-bindings: display: Add R40 and H616 display engine compatibles

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Add display engine compatible for the R40 LCD controller, and for the
H616 TV and LCD controller which is functionally identical to the R40.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 .../bindings/display/allwinner,sun4i-a10-tcon.yaml     | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml
index 724d93b9193b..caed517c68de 100644
--- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml
+++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml
@@ -29,6 +29,7 @@ properties:
       - const: allwinner,sun8i-a33-tcon
       - const: allwinner,sun8i-a83t-tcon-lcd
       - const: allwinner,sun8i-a83t-tcon-tv
+      - const: allwinner,sun8i-r40-tcon-lcd
       - const: allwinner,sun8i-r40-tcon-tv
       - const: allwinner,sun8i-v3s-tcon
       - const: allwinner,sun9i-a80-tcon-lcd
@@ -53,9 +54,15 @@ properties:
               - allwinner,sun50i-a64-tcon-tv
           - const: allwinner,sun8i-a83t-tcon-tv
 
+      - items:
+          - enum:
+              - allwinner,sun50i-h616-tcon-lcd
+          - const: allwinner,sun8i-r40-tcon-lcd
+
       - items:
           - enum:
               - allwinner,sun50i-h6-tcon-tv
+              - allwinner,sun50i-h616-tcon-tv
           - const: allwinner,sun8i-r40-tcon-tv
 
   reg:
@@ -231,6 +238,7 @@ allOf:
           contains:
             enum:
               - allwinner,sun8i-a83t-tcon-lcd
+              - allwinner,sun8i-r40-tcon-lcd
               - allwinner,sun8i-v3s-tcon
               - allwinner,sun9i-a80-tcon-lcd
               - allwinner,sun20i-d1-tcon-lcd
@@ -280,6 +288,7 @@ allOf:
               - allwinner,sun9i-a80-tcon-lcd
               - allwinner,sun4i-a10-tcon
               - allwinner,sun8i-a83t-tcon-lcd
+              - allwinner,sun8i-r40-tcon-lcd
               - allwinner,sun20i-d1-tcon-lcd
 
     then:
@@ -297,6 +306,7 @@ allOf:
               - allwinner,sun8i-a23-tcon
               - allwinner,sun8i-a33-tcon
               - allwinner,sun8i-a83t-tcon-lcd
+              - allwinner,sun8i-r40-tcon-lcd
               - allwinner,sun20i-d1-tcon-lcd
 
     then:
-- 
2.43.0

[PATCH V9 19/24] drm/sun4i: tcon: Add support for R40 LCD

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

The Allwinner H616 and related SOCs have an LCD timing controller
(TCON) which is compatible with the R40 SOC's controller and existing
sun4i driver. The H616 does not expose this controller but the H700 and
T507 (based on the same die) do. The controller supports LVDS and RGB
output.

Add quirks and compatible string to cover these SOCs.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 960e83c8291d..8cc8488483ec 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -1514,6 +1514,14 @@ static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = {
 	.has_channel_1		= true,
 };
 
+static const struct sun4i_tcon_quirks sun8i_r40_lcd_quirks = {
+	.supports_lvds		= true,
+	.has_channel_0		= true,
+	.set_mux		= sun8i_r40_tcon_tv_set_mux,
+	.dclk_min_div		= 1,
+	.setup_lvds_phy		= sun6i_tcon_setup_lvds_phy,
+};
+
 static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = {
 	.has_channel_1		= true,
 	.polarity_in_ch0	= true,
@@ -1555,6 +1563,7 @@ const struct of_device_id sun4i_tcon_of_table[] = {
 	{ .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
 	{ .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
 	{ .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
+	{ .compatible = "allwinner,sun8i-r40-tcon-lcd", .data = &sun8i_r40_lcd_quirks },
 	{ .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks },
 	{ .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
 	{ .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
-- 
2.43.0

[PATCH V9 20/24] arm64: dts: allwinner: h616: add display engine, bus and mixer nodes

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

The Allwinner H616 and variants (H618, H700 and T507) have a new display
engine variant (DE33). Support has been added to the existing DE2/DE3
sun4i driver in a previous patch series (x). The variant is selected via
the appropriate mixer device tree compatible string.

Add the respective device-tree nodes for the DE, bus, clock and mixer to
the H616 DTSI, and the matching SRAM section for the DE.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 59 +++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
index cdce3dcb8ec0..542d129da9c3 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -94,6 +94,13 @@ l2_cache: l2-cache {
 		};
 	};
 
+	de: display-engine {
+		compatible = "allwinner,sun50i-h616-display-engine",
+			     "allwinner,sun50i-h6-display-engine";
+		allwinner,pipelines = <&mixer0>;
+		status = "disabled";
+	};
+
 	reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -150,6 +157,52 @@ soc {
 		#size-cells = <1>;
 		ranges = <0x0 0x0 0x0 0x40000000>;
 
+		bus: bus@1000000 {
+			compatible = "allwinner,sun50i-h616-de33",
+				     "allwinner,sun50i-a64-de2";
+			reg = <0x1000000 0x400000>;
+			allwinner,sram = <&de33_sram 1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x1000000 0x400000>;
+
+			display_clocks: clock@8000 {
+				compatible = "allwinner,sun50i-h616-de33-clk";
+				reg = <0x8000 0x100>;
+				clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
+				clock-names = "bus", "mod";
+				resets = <&ccu RST_BUS_DE>;
+				#clock-cells = <1>;
+				#reset-cells = <1>;
+			};
+
+			mixer0: mixer@100000 {
+				compatible = "allwinner,sun50i-h616-de33-mixer-0";
+				reg = <0x100000 0x100000>,
+				      <0x8100 0x40>,
+				      <0x280000 0x20000>;
+				reg-names = "layers", "top", "display";
+				clocks = <&display_clocks CLK_BUS_MIXER0>,
+					 <&display_clocks CLK_MIXER0>;
+				clock-names = "bus", "mod";
+				resets = <&display_clocks RST_MIXER0>;
+				iommus = <&iommu 0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					mixer0_out: port@1 {
+						reg = <1>;
+
+						mixer0_out_tcon_top_mixer0: endpoint {
+							remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
+						};
+					};
+				};
+			};
+		};
+
 		crypto: crypto@1904000 {
 			compatible = "allwinner,sun50i-h616-crypto";
 			reg = <0x01904000 0x800>;
@@ -173,6 +226,12 @@ sram_c: sram@28000 {
 				#address-cells = <1>;
 				#size-cells = <1>;
 				ranges = <0 0x00028000 0x30000>;
+
+				de33_sram: sram-section@0 {
+					compatible = "allwinner,sun50i-h616-sram-c",
+						     "allwinner,sun50i-a64-sram-c";
+					reg = <0x0000 0x1e000>;
+				};
 			};
 		};
 
-- 
2.43.0

[PATCH V9 21/24] arm64: dts: allwinner: h616: Add TCON nodes to H616 DTSI

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

The Allwinner H616 has a display pipeline similar to other Allwinner
devices, specifically the A10, but using a newer display engine
revision (DE33).

Not all output pins are exposed on all package variants, for example
only the H700 and T507 have LCD pins exposed, but all variants support
HDMI output. However on the die these are connected to a display engine
via a TCON TOP and one or more timing controllers (TCONs).

HDMI output support is not provided in this series (but will be in a
subsequent patch) so for now note this within the relevant node to
prevent a DT compiler error.

Add TCON nodes for the TOP, and the LCD and TV timing controllers. The
timing controllers are compatible with the existing R40 driver.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 139 ++++++++++++++++++
 1 file changed, 139 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
index 542d129da9c3..129ce78ae5f3 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -7,9 +7,12 @@
 #include <dt-bindings/clock/sun50i-h616-ccu.h>
 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
 #include <dt-bindings/clock/sun6i-rtc.h>
+#include <dt-bindings/clock/sun8i-de2.h>
+#include <dt-bindings/clock/sun8i-tcon-top.h>
 #include <dt-bindings/reset/sun50i-h616-ccu.h>
 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
 #include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/reset/sun8i-de2.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -912,6 +915,142 @@ ohci3: usb@5311400 {
 			status = "disabled";
 		};
 
+		tcon_top: tcon-top@6510000 {
+			compatible = "allwinner,sun50i-h616-tcon-top",
+				     "allwinner,sun50i-h6-tcon-top";
+			reg = <0x06510000 0x1000>;
+			clocks = <&ccu CLK_BUS_TCON_TOP>,
+				 <&ccu CLK_TCON_TV0>;
+			clock-names = "bus", "tcon-tv0";
+			clock-output-names = "tcon-top-tv0";
+			#clock-cells = <1>;
+			resets = <&ccu RST_BUS_TCON_TOP>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				tcon_top_mixer0_in: port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+
+					tcon_top_mixer0_in_mixer0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
+					};
+				};
+
+				tcon_top_mixer0_out: port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+
+					tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
+					};
+
+					tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
+						reg = <2>;
+						remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
+					};
+				};
+
+				tcon_top_hdmi_in: port@4 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <4>;
+
+					tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&tcon_tv0_out_tcon_top>;
+					};
+				};
+
+				tcon_top_hdmi_out: port@5 {
+					reg = <5>;
+
+					tcon_top_hdmi_out_hdmi: endpoint {
+						/* placeholder for HDMI  - remote-endpoint = <&hdmi_in_tcon_top>;*/
+					};
+				};
+			};
+		};
+
+		tcon_lcd0: lcd-controller@6511000 {
+			compatible = "allwinner,sun50i-h616-tcon-lcd",
+				     "allwinner,sun8i-r40-tcon-lcd";
+			reg = <0x06511000 0x1000>;
+			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_TCON_LCD0>, <&ccu CLK_TCON_LCD0>;
+			clock-names = "ahb", "tcon-ch0";
+			clock-output-names = "tcon-data-clock";
+			#clock-cells = <0>;
+			resets = <&ccu RST_BUS_TCON_LCD0>, <&ccu RST_BUS_LVDS>;
+			reset-names = "lcd", "lvds";
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				tcon_lcd0_in: port@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					tcon_lcd0_in_tcon_top_mixer0: endpoint {
+						remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
+					};
+				};
+
+				tcon_lcd0_out: port@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+		};
+
+		tcon_tv0: lcd-controller@6515000 {
+			compatible = "allwinner,sun50i-h616-tcon-tv",
+				     "allwinner,sun8i-r40-tcon-tv";
+			reg = <0x06515000 0x1000>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_TCON_TV0>,
+				 <&tcon_top CLK_TCON_TOP_TV0>;
+			clock-names = "ahb", "tcon-ch1";
+			#clock-cells = <0>;
+			resets = <&ccu RST_BUS_TCON_TV0>;
+			reset-names = "lcd";
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				tcon_tv0_in: port@0 {
+					reg = <0>;
+
+					tcon_tv0_in_tcon_top_mixer0: endpoint {
+						remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
+					};
+				};
+
+				tcon_tv0_out: port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+
+					tcon_tv0_out_tcon_top: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
+					};
+				};
+			};
+		};
+
 		rtc: rtc@7000000 {
 			compatible = "allwinner,sun50i-h616-rtc";
 			reg = <0x07000000 0x400>;
-- 
2.43.0

[PATCH V9 22/24] arm64: dts: allwinner: h616: add LCD and LVDS pins

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

The Allwinner H616 (and its H618, H700 and T507 package variants with
the same die) have 28 video output pins for RGB/SPI and LVDS display.
These are in GPIO Bank D and are multiplexed.

In RGB mode, pins PD0-PD23 are for 24-bit RGB pixel output, pins
PD24-PD27 are for clock, DE, HSYNC and VSYNC.

In LVDS mode, pins PD0-PD9 are for LVDS0 and LVDS1, and can be
configured by the H616 display engine for either one high-resolution
(dual link) or two low resolution displays.

Add device tree nodes for the LCD, LVDS0, and LVDS1 pins.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
index 129ce78ae5f3..3d8b412afb88 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -325,6 +325,32 @@ ir_rx_pin: ir-rx-pin {
 				function = "ir_rx";
 			};
 
+			/omit-if-no-ref/
+			lcd0_rgb888_pins: lcd0-rgb888-pins {
+				pins = "PD0", "PD1", "PD2", "PD3",
+				       "PD4", "PD5", "PD6", "PD7",
+				       "PD8", "PD9", "PD10", "PD11",
+				       "PD12", "PD13", "PD14", "PD15",
+				       "PD16", "PD17", "PD18", "PD19",
+				       "PD20", "PD21", "PD22", "PD23",
+				       "PD24", "PD25", "PD26", "PD27";
+				function = "lcd0";
+			};
+
+			/omit-if-no-ref/
+			lvds0_pins: lvds0-pins {
+				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
+				       "PD5", "PD6", "PD7", "PD8", "PD9";
+				function = "lvds0";
+			};
+
+			/omit-if-no-ref/
+			lvds1_pins: lvds1-pins {
+				pins = "PD10", "PD11", "PD12", "PD13", "PD14",
+				       "PD15", "PD16", "PD17", "PD18", "PD19";
+				function = "lvds1";
+			};
+
 			mmc0_pins: mmc0-pins {
 				pins = "PF0", "PF1", "PF2", "PF3",
 				       "PF4", "PF5";
-- 
2.43.0

[PATCH V9 23/24] arm64: dts: allwinner: rg35xx: Add GPIO backlight control

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

The LCD backlight for this device can be exposed as a simple GPIO-
controlled device. It would be more accurately modelled using PWM to
enable brightness control, however the PWM driver design for the H616 is
not yet upstreamed.

Add a GPIO backlight node to the DTS.

Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 .../boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
index 7e17ca07892d..95f2ae04bd95 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
@@ -21,6 +21,12 @@ aliases {
 		serial0 = &uart0;
 	};
 
+	backlight: backlight {
+		compatible = "gpio-backlight";
+		gpios = <&pio 3 28 GPIO_ACTIVE_HIGH>; // PD28
+		default-on;
+	};
+
 	battery: battery {
 		compatible = "simple-battery";
 		constant-charge-current-max-microamp = <1024000>;
-- 
2.43.0

[PATCH V9 24/24] arm64: dts: allwinner: rg35xx: Enable LCD output

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

The RG35XX has a 640x480 RGB/SPI LCD panel, supported by the SoC display
pipeline and an NV3052C controller. The H616 SOC's GPIO bank D contains
the muxed display pins for RGB and LVDS output support.

Enable the display engine and LCD timing controller, configure the
panel, and add a fixed 3.3v GPIO-controlled regulator for the panel, and
a VCC supply for the display pins as per the other GPIO banks.

Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 .../sun50i-h700-anbernic-rg35xx-2024.dts      | 59 +++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
index 95f2ae04bd95..260c2d55a86e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
@@ -187,6 +187,49 @@ reg_vcc5v: regulator-vcc5v { /* USB-C power input */
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
 	};
+
+	reg_lcd: regulator-gpio-lcd-vdd {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vdd-lcd";
+		gpio = <&pio 8 15 GPIO_ACTIVE_HIGH>; // PI15
+		enable-active-high;
+	};
+
+	spi_lcd: spi {
+		compatible = "spi-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sck-gpios = <&pio 8 9 GPIO_ACTIVE_HIGH>; // PI9
+		mosi-gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>; // PI10
+		cs-gpios = <&pio 8 8 GPIO_ACTIVE_HIGH>; // PI8
+		num-chipselects = <1>;
+
+		panel: panel@0 {
+			compatible = "anbernic,rg35xx-plus-panel";
+
+			reg = <0>;
+
+			spi-max-frequency = <3125000>;
+			spi-3wire;
+
+			reset-gpios = <&pio 8 14 GPIO_ACTIVE_LOW>; // PI14
+
+			backlight = <&backlight>;
+			power-supply = <&reg_lcd>;
+
+			pinctrl-0 = <&lcd0_rgb888_pins>;
+			pinctrl-names = "default";
+
+			port {
+				panel_in_rgb: endpoint {
+					remote-endpoint = <&tcon_lcd0_out_lcd>;
+				};
+			};
+		};
+	};
 };
 
 &codec {
@@ -199,6 +242,10 @@ &cpu0 {
 	cpu-supply = <&reg_dcdc1>;
 };
 
+&de {
+	status = "okay";
+};
+
 &ehci0 {
 	status = "okay";
 };
@@ -218,6 +265,7 @@ &ohci0 {
 &pio {
 	vcc-pa-supply = <&reg_cldo3>;
 	vcc-pc-supply = <&reg_cldo3>;
+	vcc-pd-supply = <&reg_cldo3>;
 	vcc-pe-supply = <&reg_cldo3>;
 	vcc-pf-supply = <&reg_cldo3>;
 	vcc-pg-supply = <&reg_aldo4>;
@@ -377,3 +425,14 @@ &usbotg {
 &usbphy {
 	status = "okay";
 };
+
+&tcon_lcd0 {
+	status = "okay";
+};
+
+&tcon_lcd0_out {
+	tcon_lcd0_out_lcd: endpoint@1 {
+		reg = <1>;
+		remote-endpoint = <&panel_in_rgb>;
+	};
+};
-- 
2.43.0

Re: [PATCH V9 00/24] drm: sun4i: add Display Engine 3.3 (DE33) support

[Rob Herring]

On Wed, May 7, 2025 at 3:22 PM Chris Morgan <macroalpha82@gmail.com> wrote:
>
> From: Chris Morgan <macromorgan@hotmail.com>
>
> I've spoken with Ryan and he agreed to let me take over this series to
> get the display engine working on the Allwinner H616. I've taken his
> previous patch series for Display Engine 3.3 and combined it with the
> LCD controller patch series. I've also fixed a few additional bugs and
> made some changes to the device tree bindings.
>
> Changes since V8:
>  - Combined the DE33 [1] series and the LCD [2] series to better track
>    all patches necessary to output to an LCD display for the Allwinner
>    H700.
>  - Added a required LVDS reset as requested here [3].
>  - Added compatible strings with a fallback for
>    allwinner,sun50i-h616-display-engine, allwinner,sun50i-h616-tcon-top,
>    and allwinner,sun50i-h616-sram-c.
>  - Added binding documentation for the LCD controller.
>  - Renamed the de3_sram device tree node to de33_sram.
>  - Corrected the LVDS reset for the LCD controller binding.
>  - Removed the PWM pins from the pincontroller bindings, as PWM is not
>    yet supported.
>  - Reordered the patches so that a binding or a device tree node is not
>    referenced before it is defined.
>
> [1] https://lore.kernel.org/linux-sunxi/20250310092345.31708-1-ryan@testtoast.com/
> [2] https://lore.kernel.org/linux-sunxi/20250216092827.15444-1-ryan@testtoast.com/
> [3] https://lore.kernel.org/linux-sunxi/38669808.XM6RcZxFsP@jernej-laptop/
>
> Chris Morgan (24):
>   dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset
>   clk: sunxi-ng: h616: Add LVDS reset for LCD TCON
>   drm: sun4i: de2/de3: add mixer version enum
>   drm: sun4i: de2/de3: refactor mixer initialisation
>   drm: sun4i: de2/de3: add generic blender register reference function
>   drm: sun4i: de2/de3: use generic register reference function for layer
>     configuration
>   dt-bindings: allwinner: add H616 DE33 bus binding
>   dt-bindings: allwinner: add H616 DE33 clock binding
>   dt-bindings: allwinner: add H616 DE33 mixer binding
>   clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support
>   drm: sun4i: de33: vi_scaler: add Display Engine 3.3 (DE33) support
>   drm: sun4i: de33: mixer: add Display Engine 3.3 (DE33) support
>   drm: sun4i: de33: mixer: add mixer configuration for the H616
>   dt-bindings: allwinner: Add TCON_TOP and TCON_LCD clock/reset defines
>   dt-bindings: display: sun4i: Add compatible strings for H616 DE
>   dt-bindings: display: sun4i: Add compatible strings for H616 TCON TOP
>   dt-bindings: sram: sunxi-sram: Add H616 SRAM C compatible
>   dt-bindings: display: Add R40 and H616 display engine compatibles
>   drm/sun4i: tcon: Add support for R40 LCD
>   arm64: dts: allwinner: h616: add display engine, bus and mixer nodes
>   arm64: dts: allwinner: h616: Add TCON nodes to H616 DTSI
>   arm64: dts: allwinner: h616: add LCD and LVDS pins
>   arm64: dts: allwinner: rg35xx: Add GPIO backlight control
>   arm64: dts: allwinner: rg35xx: Enable LCD output

What's the base for this series? It didn't apply for me (using b4).

Rob

Re: [PATCH V9 00/24] drm: sun4i: add Display Engine 3.3 (DE33) support

[Krzysztof Kozlowski]

On Wed, May 07, 2025 at 03:19:19PM GMT, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
> 
> I've spoken with Ryan and he agreed to let me take over this series to
> get the display engine working on the Allwinner H616. I've taken his
> previous patch series for Display Engine 3.3 and combined it with the
> LCD controller patch series. I've also fixed a few additional bugs and
> made some changes to the device tree bindings.
> 
> Changes since V8:
>  - Combined the DE33 [1] series and the LCD [2] series to better track
>    all patches necessary to output to an LCD display for the Allwinner
>    H700.

You have here three or four different subsystems. This does not make it
easier, but it makes it a huge patchbomb with unspecific or complex
base.

Such combination makes no sense, because anyway it will have to be split
per subsystem. You just know made it difficult for maintainers to review
and apply, because they cannot apply entire set.

Best regards,
Krzysztof

Re: [PATCH V9 21/24] arm64: dts: allwinner: h616: Add TCON nodes to H616 DTSI

[kernel test robot]

:::::: 
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
:::::: 

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20250507201943.330111-22-macroalpha82@gmail.com>
References: <20250507201943.330111-22-macroalpha82@gmail.com>
TO: Chris Morgan <macroalpha82@gmail.com>
TO: linux-sunxi@lists.linux.dev
CC: devicetree@vger.kernel.org
CC: dri-devel@lists.freedesktop.org
CC: ryan@testtoast.com
CC: macromorgan@hotmail.com
CC: p.zabel@pengutronix.de
CC: tzimmermann@suse.de
CC: maarten.lankhorst@linux.intel.com
CC: simona@ffwll.ch
CC: airlied@gmail.com
CC: mripard@kernel.org
CC: samuel@sholland.org
CC: jernej.skrabec@gmail.com
CC: wens@csie.org
CC: conor+dt@kernel.org
CC: krzk+dt@kernel.org
CC: robh@kernel.org

Hi Chris,

kernel test robot noticed the following build warnings:

[auto build test WARNING on clk/clk-next]
[also build test WARNING on pza/reset/next robh/for-next linus/master v6.15-rc5]
[cannot apply to sunxi/sunxi/for-next pza/imx-drm/next next-20250508]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Chris-Morgan/dt-bindings-clock-sun50i-h616-ccu-Add-LVDS-reset/20250508-042430
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
patch link:    https://lore.kernel.org/r/20250507201943.330111-22-macroalpha82%40gmail.com
patch subject: [PATCH V9 21/24] arm64: dts: allwinner: h616: Add TCON nodes to H616 DTSI
:::::: branch date: 20 hours ago
:::::: commit date: 20 hours ago
config: arm64-defconfig (https://download.01.org/0day-ci/archive/20250509/202505090037.kjlIx2Fw-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250509/202505090037.kjlIx2Fw-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202505090037.kjlIx2Fw-lkp@intel.com/

dtcheck warnings: (new ones prefixed by >>)
   arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi:157.6-1150.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name
>> arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi:998.26-1006.7: Warning (avoid_unnecessary_addr_size): /soc/lcd-controller@6511000/ports/port@0: unnecessary #address-cells/#size-cells without "ranges", "dma-ranges" or child "reg" property
>> arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi:933.32-942.7: Warning (graph_child_address): /soc/tcon-top@6510000/ports/port@0: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
   arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi:960.30-969.7: Warning (graph_child_address): /soc/tcon-top@6510000/ports/port@4: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
>> arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi:998.26-1006.7: Warning (graph_child_address): /soc/lcd-controller@6511000/ports/port@0: graph node has single child node 'endpoint', #address-cells/#size-cells are not necessary

vim +998 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi

0d17c8651188816 Andre Przywara 2022-07-08   16  
0d17c8651188816 Andre Przywara 2022-07-08   17  / {
0d17c8651188816 Andre Przywara 2022-07-08   18  	interrupt-parent = <&gic>;
0d17c8651188816 Andre Przywara 2022-07-08   19  	#address-cells = <2>;
0d17c8651188816 Andre Przywara 2022-07-08   20  	#size-cells = <2>;
0d17c8651188816 Andre Przywara 2022-07-08   21  
0d17c8651188816 Andre Przywara 2022-07-08   22  	cpus {
0d17c8651188816 Andre Przywara 2022-07-08   23  		#address-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08   24  		#size-cells = <0>;
0d17c8651188816 Andre Przywara 2022-07-08   25  
0d17c8651188816 Andre Przywara 2022-07-08   26  		cpu0: cpu@0 {
0d17c8651188816 Andre Przywara 2022-07-08   27  			compatible = "arm,cortex-a53";
0d17c8651188816 Andre Przywara 2022-07-08   28  			device_type = "cpu";
0d17c8651188816 Andre Przywara 2022-07-08   29  			reg = <0>;
0d17c8651188816 Andre Przywara 2022-07-08   30  			enable-method = "psci";
0d17c8651188816 Andre Przywara 2022-07-08   31  			clocks = <&ccu CLK_CPUX>;
3e057e05b3b281b Martin Botka   2024-04-18   32  			#cooling-cells = <2>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   33  			i-cache-size = <0x8000>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   34  			i-cache-line-size = <64>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   35  			i-cache-sets = <256>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   36  			d-cache-size = <0x8000>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   37  			d-cache-line-size = <64>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   38  			d-cache-sets = <128>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   39  			next-level-cache = <&l2_cache>;
0d17c8651188816 Andre Przywara 2022-07-08   40  		};
0d17c8651188816 Andre Przywara 2022-07-08   41  
0d17c8651188816 Andre Przywara 2022-07-08   42  		cpu1: cpu@1 {
0d17c8651188816 Andre Przywara 2022-07-08   43  			compatible = "arm,cortex-a53";
0d17c8651188816 Andre Przywara 2022-07-08   44  			device_type = "cpu";
0d17c8651188816 Andre Przywara 2022-07-08   45  			reg = <1>;
0d17c8651188816 Andre Przywara 2022-07-08   46  			enable-method = "psci";
0d17c8651188816 Andre Przywara 2022-07-08   47  			clocks = <&ccu CLK_CPUX>;
3e057e05b3b281b Martin Botka   2024-04-18   48  			#cooling-cells = <2>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   49  			i-cache-size = <0x8000>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   50  			i-cache-line-size = <64>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   51  			i-cache-sets = <256>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   52  			d-cache-size = <0x8000>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   53  			d-cache-line-size = <64>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   54  			d-cache-sets = <128>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   55  			next-level-cache = <&l2_cache>;
0d17c8651188816 Andre Przywara 2022-07-08   56  		};
0d17c8651188816 Andre Przywara 2022-07-08   57  
0d17c8651188816 Andre Przywara 2022-07-08   58  		cpu2: cpu@2 {
0d17c8651188816 Andre Przywara 2022-07-08   59  			compatible = "arm,cortex-a53";
0d17c8651188816 Andre Przywara 2022-07-08   60  			device_type = "cpu";
0d17c8651188816 Andre Przywara 2022-07-08   61  			reg = <2>;
0d17c8651188816 Andre Przywara 2022-07-08   62  			enable-method = "psci";
0d17c8651188816 Andre Przywara 2022-07-08   63  			clocks = <&ccu CLK_CPUX>;
3e057e05b3b281b Martin Botka   2024-04-18   64  			#cooling-cells = <2>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   65  			i-cache-size = <0x8000>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   66  			i-cache-line-size = <64>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   67  			i-cache-sets = <256>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   68  			d-cache-size = <0x8000>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   69  			d-cache-line-size = <64>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   70  			d-cache-sets = <128>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   71  			next-level-cache = <&l2_cache>;
0d17c8651188816 Andre Przywara 2022-07-08   72  		};
0d17c8651188816 Andre Przywara 2022-07-08   73  
0d17c8651188816 Andre Przywara 2022-07-08   74  		cpu3: cpu@3 {
0d17c8651188816 Andre Przywara 2022-07-08   75  			compatible = "arm,cortex-a53";
0d17c8651188816 Andre Przywara 2022-07-08   76  			device_type = "cpu";
0d17c8651188816 Andre Przywara 2022-07-08   77  			reg = <3>;
0d17c8651188816 Andre Przywara 2022-07-08   78  			enable-method = "psci";
0d17c8651188816 Andre Przywara 2022-07-08   79  			clocks = <&ccu CLK_CPUX>;
3e057e05b3b281b Martin Botka   2024-04-18   80  			#cooling-cells = <2>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   81  			i-cache-size = <0x8000>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   82  			i-cache-line-size = <64>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   83  			i-cache-sets = <256>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   84  			d-cache-size = <0x8000>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   85  			d-cache-line-size = <64>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   86  			d-cache-sets = <128>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   87  			next-level-cache = <&l2_cache>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   88  		};
d4ec229eaeb8453 Dragan Simic   2024-05-28   89  
d4ec229eaeb8453 Dragan Simic   2024-05-28   90  		l2_cache: l2-cache {
d4ec229eaeb8453 Dragan Simic   2024-05-28   91  			compatible = "cache";
d4ec229eaeb8453 Dragan Simic   2024-05-28   92  			cache-level = <2>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   93  			cache-unified;
d4ec229eaeb8453 Dragan Simic   2024-05-28   94  			cache-size = <0x40000>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   95  			cache-line-size = <64>;
d4ec229eaeb8453 Dragan Simic   2024-05-28   96  			cache-sets = <256>;
0d17c8651188816 Andre Przywara 2022-07-08   97  		};
0d17c8651188816 Andre Przywara 2022-07-08   98  	};
0d17c8651188816 Andre Przywara 2022-07-08   99  
60a0991a3f8618f Chris Morgan   2025-05-07  100  	de: display-engine {
60a0991a3f8618f Chris Morgan   2025-05-07  101  		compatible = "allwinner,sun50i-h616-display-engine",
60a0991a3f8618f Chris Morgan   2025-05-07  102  			     "allwinner,sun50i-h6-display-engine";
60a0991a3f8618f Chris Morgan   2025-05-07  103  		allwinner,pipelines = <&mixer0>;
60a0991a3f8618f Chris Morgan   2025-05-07  104  		status = "disabled";
60a0991a3f8618f Chris Morgan   2025-05-07  105  	};
60a0991a3f8618f Chris Morgan   2025-05-07  106  
0d17c8651188816 Andre Przywara 2022-07-08  107  	reserved-memory {
0d17c8651188816 Andre Przywara 2022-07-08  108  		#address-cells = <2>;
0d17c8651188816 Andre Przywara 2022-07-08  109  		#size-cells = <2>;
0d17c8651188816 Andre Przywara 2022-07-08  110  		ranges;
0d17c8651188816 Andre Przywara 2022-07-08  111  
0d17c8651188816 Andre Przywara 2022-07-08  112  		/*
0d17c8651188816 Andre Przywara 2022-07-08  113  		 * 256 KiB reserved for Trusted Firmware-A (BL31).
0d17c8651188816 Andre Przywara 2022-07-08  114  		 * This is added by BL31 itself, but some bootloaders fail
0d17c8651188816 Andre Przywara 2022-07-08  115  		 * to propagate this into the DTB handed to kernels.
0d17c8651188816 Andre Przywara 2022-07-08  116  		 */
0d17c8651188816 Andre Przywara 2022-07-08  117  		secmon@40000000 {
0d17c8651188816 Andre Przywara 2022-07-08  118  			reg = <0x0 0x40000000 0x0 0x40000>;
0d17c8651188816 Andre Przywara 2022-07-08  119  			no-map;
0d17c8651188816 Andre Przywara 2022-07-08  120  		};
0d17c8651188816 Andre Przywara 2022-07-08  121  	};
0d17c8651188816 Andre Przywara 2022-07-08  122  
0d17c8651188816 Andre Przywara 2022-07-08  123  	osc24M: osc24M-clk {
0d17c8651188816 Andre Przywara 2022-07-08  124  		#clock-cells = <0>;
0d17c8651188816 Andre Przywara 2022-07-08  125  		compatible = "fixed-clock";
0d17c8651188816 Andre Przywara 2022-07-08  126  		clock-frequency = <24000000>;
0d17c8651188816 Andre Przywara 2022-07-08  127  		clock-output-names = "osc24M";
0d17c8651188816 Andre Przywara 2022-07-08  128  	};
0d17c8651188816 Andre Przywara 2022-07-08  129  
0d17c8651188816 Andre Przywara 2022-07-08  130  	pmu {
0d17c8651188816 Andre Przywara 2022-07-08  131  		compatible = "arm,cortex-a53-pmu";
0d17c8651188816 Andre Przywara 2022-07-08  132  		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
0d17c8651188816 Andre Przywara 2022-07-08  133  			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
0d17c8651188816 Andre Przywara 2022-07-08  134  			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
0d17c8651188816 Andre Przywara 2022-07-08  135  			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  136  		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0d17c8651188816 Andre Przywara 2022-07-08  137  	};
0d17c8651188816 Andre Przywara 2022-07-08  138  
0d17c8651188816 Andre Przywara 2022-07-08  139  	psci {
0d17c8651188816 Andre Przywara 2022-07-08  140  		compatible = "arm,psci-0.2";
0d17c8651188816 Andre Przywara 2022-07-08  141  		method = "smc";
0d17c8651188816 Andre Przywara 2022-07-08  142  	};
0d17c8651188816 Andre Przywara 2022-07-08  143  
0d17c8651188816 Andre Przywara 2022-07-08  144  	timer {
0d17c8651188816 Andre Przywara 2022-07-08  145  		compatible = "arm,armv8-timer";
0d17c8651188816 Andre Przywara 2022-07-08  146  		arm,no-tick-in-suspend;
0d17c8651188816 Andre Przywara 2022-07-08  147  		interrupts = <GIC_PPI 13
0d17c8651188816 Andre Przywara 2022-07-08  148  			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0d17c8651188816 Andre Przywara 2022-07-08  149  			     <GIC_PPI 14
0d17c8651188816 Andre Przywara 2022-07-08  150  			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0d17c8651188816 Andre Przywara 2022-07-08  151  			     <GIC_PPI 11
0d17c8651188816 Andre Przywara 2022-07-08  152  			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0d17c8651188816 Andre Przywara 2022-07-08  153  			     <GIC_PPI 10
0d17c8651188816 Andre Przywara 2022-07-08  154  			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0d17c8651188816 Andre Przywara 2022-07-08  155  	};
0d17c8651188816 Andre Przywara 2022-07-08  156  
0d17c8651188816 Andre Przywara 2022-07-08  157  	soc {
0d17c8651188816 Andre Przywara 2022-07-08  158  		compatible = "simple-bus";
0d17c8651188816 Andre Przywara 2022-07-08  159  		#address-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  160  		#size-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  161  		ranges = <0x0 0x0 0x0 0x40000000>;
0d17c8651188816 Andre Przywara 2022-07-08  162  
60a0991a3f8618f Chris Morgan   2025-05-07  163  		bus: bus@1000000 {
60a0991a3f8618f Chris Morgan   2025-05-07  164  			compatible = "allwinner,sun50i-h616-de33",
60a0991a3f8618f Chris Morgan   2025-05-07  165  				     "allwinner,sun50i-a64-de2";
60a0991a3f8618f Chris Morgan   2025-05-07  166  			reg = <0x1000000 0x400000>;
60a0991a3f8618f Chris Morgan   2025-05-07  167  			allwinner,sram = <&de33_sram 1>;
60a0991a3f8618f Chris Morgan   2025-05-07  168  			#address-cells = <1>;
60a0991a3f8618f Chris Morgan   2025-05-07  169  			#size-cells = <1>;
60a0991a3f8618f Chris Morgan   2025-05-07  170  			ranges = <0 0x1000000 0x400000>;
60a0991a3f8618f Chris Morgan   2025-05-07  171  
60a0991a3f8618f Chris Morgan   2025-05-07  172  			display_clocks: clock@8000 {
60a0991a3f8618f Chris Morgan   2025-05-07  173  				compatible = "allwinner,sun50i-h616-de33-clk";
60a0991a3f8618f Chris Morgan   2025-05-07  174  				reg = <0x8000 0x100>;
60a0991a3f8618f Chris Morgan   2025-05-07  175  				clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
60a0991a3f8618f Chris Morgan   2025-05-07  176  				clock-names = "bus", "mod";
60a0991a3f8618f Chris Morgan   2025-05-07  177  				resets = <&ccu RST_BUS_DE>;
60a0991a3f8618f Chris Morgan   2025-05-07  178  				#clock-cells = <1>;
60a0991a3f8618f Chris Morgan   2025-05-07  179  				#reset-cells = <1>;
60a0991a3f8618f Chris Morgan   2025-05-07  180  			};
60a0991a3f8618f Chris Morgan   2025-05-07  181  
60a0991a3f8618f Chris Morgan   2025-05-07  182  			mixer0: mixer@100000 {
60a0991a3f8618f Chris Morgan   2025-05-07  183  				compatible = "allwinner,sun50i-h616-de33-mixer-0";
60a0991a3f8618f Chris Morgan   2025-05-07  184  				reg = <0x100000 0x100000>,
60a0991a3f8618f Chris Morgan   2025-05-07  185  				      <0x8100 0x40>,
60a0991a3f8618f Chris Morgan   2025-05-07  186  				      <0x280000 0x20000>;
60a0991a3f8618f Chris Morgan   2025-05-07  187  				reg-names = "layers", "top", "display";
60a0991a3f8618f Chris Morgan   2025-05-07  188  				clocks = <&display_clocks CLK_BUS_MIXER0>,
60a0991a3f8618f Chris Morgan   2025-05-07  189  					 <&display_clocks CLK_MIXER0>;
60a0991a3f8618f Chris Morgan   2025-05-07  190  				clock-names = "bus", "mod";
60a0991a3f8618f Chris Morgan   2025-05-07  191  				resets = <&display_clocks RST_MIXER0>;
60a0991a3f8618f Chris Morgan   2025-05-07  192  				iommus = <&iommu 0>;
60a0991a3f8618f Chris Morgan   2025-05-07  193  
60a0991a3f8618f Chris Morgan   2025-05-07  194  				ports {
60a0991a3f8618f Chris Morgan   2025-05-07  195  					#address-cells = <1>;
60a0991a3f8618f Chris Morgan   2025-05-07  196  					#size-cells = <0>;
60a0991a3f8618f Chris Morgan   2025-05-07  197  
60a0991a3f8618f Chris Morgan   2025-05-07  198  					mixer0_out: port@1 {
60a0991a3f8618f Chris Morgan   2025-05-07  199  						reg = <1>;
60a0991a3f8618f Chris Morgan   2025-05-07  200  
60a0991a3f8618f Chris Morgan   2025-05-07  201  						mixer0_out_tcon_top_mixer0: endpoint {
60a0991a3f8618f Chris Morgan   2025-05-07  202  							remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
60a0991a3f8618f Chris Morgan   2025-05-07  203  						};
60a0991a3f8618f Chris Morgan   2025-05-07  204  					};
60a0991a3f8618f Chris Morgan   2025-05-07  205  				};
60a0991a3f8618f Chris Morgan   2025-05-07  206  			};
60a0991a3f8618f Chris Morgan   2025-05-07  207  		};
60a0991a3f8618f Chris Morgan   2025-05-07  208  
6ed9a85f1c44d70 Andre Przywara 2024-06-25  209  		crypto: crypto@1904000 {
6ed9a85f1c44d70 Andre Przywara 2024-06-25  210  			compatible = "allwinner,sun50i-h616-crypto";
6ed9a85f1c44d70 Andre Przywara 2024-06-25  211  			reg = <0x01904000 0x800>;
6ed9a85f1c44d70 Andre Przywara 2024-06-25  212  			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
6ed9a85f1c44d70 Andre Przywara 2024-06-25  213  			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>,
6ed9a85f1c44d70 Andre Przywara 2024-06-25  214  				 <&ccu CLK_MBUS_CE>, <&rtc CLK_IOSC>;
6ed9a85f1c44d70 Andre Przywara 2024-06-25  215  			clock-names = "bus", "mod", "ram", "trng";
6ed9a85f1c44d70 Andre Przywara 2024-06-25  216  			resets = <&ccu RST_BUS_CE>;
6ed9a85f1c44d70 Andre Przywara 2024-06-25  217  		};
6ed9a85f1c44d70 Andre Przywara 2024-06-25  218  
0d17c8651188816 Andre Przywara 2022-07-08  219  		syscon: syscon@3000000 {
0d17c8651188816 Andre Przywara 2022-07-08  220  			compatible = "allwinner,sun50i-h616-system-control";
0d17c8651188816 Andre Przywara 2022-07-08  221  			reg = <0x03000000 0x1000>;
0d17c8651188816 Andre Przywara 2022-07-08  222  			#address-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  223  			#size-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  224  			ranges;
0d17c8651188816 Andre Przywara 2022-07-08  225  
0d17c8651188816 Andre Przywara 2022-07-08  226  			sram_c: sram@28000 {
0d17c8651188816 Andre Przywara 2022-07-08  227  				compatible = "mmio-sram";
0d17c8651188816 Andre Przywara 2022-07-08  228  				reg = <0x00028000 0x30000>;
0d17c8651188816 Andre Przywara 2022-07-08  229  				#address-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  230  				#size-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  231  				ranges = <0 0x00028000 0x30000>;
60a0991a3f8618f Chris Morgan   2025-05-07  232  
60a0991a3f8618f Chris Morgan   2025-05-07  233  				de33_sram: sram-section@0 {
60a0991a3f8618f Chris Morgan   2025-05-07  234  					compatible = "allwinner,sun50i-h616-sram-c",
60a0991a3f8618f Chris Morgan   2025-05-07  235  						     "allwinner,sun50i-a64-sram-c";
60a0991a3f8618f Chris Morgan   2025-05-07  236  					reg = <0x0000 0x1e000>;
60a0991a3f8618f Chris Morgan   2025-05-07  237  				};
0d17c8651188816 Andre Przywara 2022-07-08  238  			};
0d17c8651188816 Andre Przywara 2022-07-08  239  		};
0d17c8651188816 Andre Przywara 2022-07-08  240  
0d17c8651188816 Andre Przywara 2022-07-08  241  		ccu: clock@3001000 {
0d17c8651188816 Andre Przywara 2022-07-08  242  			compatible = "allwinner,sun50i-h616-ccu";
0d17c8651188816 Andre Przywara 2022-07-08  243  			reg = <0x03001000 0x1000>;
0d17c8651188816 Andre Przywara 2022-07-08  244  			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
0d17c8651188816 Andre Przywara 2022-07-08  245  			clock-names = "hosc", "losc", "iosc";
0d17c8651188816 Andre Przywara 2022-07-08  246  			#clock-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  247  			#reset-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  248  		};
0d17c8651188816 Andre Przywara 2022-07-08  249  
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  250  		dma: dma-controller@3002000 {
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  251  			compatible = "allwinner,sun50i-h616-dma",
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  252  				     "allwinner,sun50i-a100-dma";
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  253  			reg = <0x03002000 0x1000>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  254  			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  255  			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  256  			clock-names = "bus", "mbus";
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  257  			dma-channels = <16>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  258  			dma-requests = <49>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  259  			resets = <&ccu RST_BUS_DMA>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  260  			#dma-cells = <1>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  261  		};
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  262  
951992797378a21 Martin Botka   2023-09-12  263  		sid: efuse@3006000 {
951992797378a21 Martin Botka   2023-09-12  264  			compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid";
951992797378a21 Martin Botka   2023-09-12  265  			reg = <0x03006000 0x1000>;
951992797378a21 Martin Botka   2023-09-12  266  			#address-cells = <1>;
951992797378a21 Martin Botka   2023-09-12  267  			#size-cells = <1>;
f4318af40544b8e Martin Botka   2024-02-19  268  
f4318af40544b8e Martin Botka   2024-02-19  269  			ths_calibration: thermal-sensor-calibration@14 {
f4318af40544b8e Martin Botka   2024-02-19  270  				reg = <0x14 0x8>;
f4318af40544b8e Martin Botka   2024-02-19  271  			};
3e057e05b3b281b Martin Botka   2024-04-18  272  
3e057e05b3b281b Martin Botka   2024-04-18  273  			cpu_speed_grade: cpu-speed-grade@0 {
3e057e05b3b281b Martin Botka   2024-04-18  274  				reg = <0x0 2>;
3e057e05b3b281b Martin Botka   2024-04-18  275  			};
951992797378a21 Martin Botka   2023-09-12  276  		};
951992797378a21 Martin Botka   2023-09-12  277  
0d17c8651188816 Andre Przywara 2022-07-08  278  		watchdog: watchdog@30090a0 {
0d17c8651188816 Andre Przywara 2022-07-08  279  			compatible = "allwinner,sun50i-h616-wdt",
0d17c8651188816 Andre Przywara 2022-07-08  280  				     "allwinner,sun6i-a31-wdt";
0d17c8651188816 Andre Przywara 2022-07-08  281  			reg = <0x030090a0 0x20>;
0d17c8651188816 Andre Przywara 2022-07-08  282  			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  283  			clocks = <&osc24M>;
0d17c8651188816 Andre Przywara 2022-07-08  284  		};
0d17c8651188816 Andre Przywara 2022-07-08  285  
0d17c8651188816 Andre Przywara 2022-07-08  286  		pio: pinctrl@300b000 {
0d17c8651188816 Andre Przywara 2022-07-08  287  			compatible = "allwinner,sun50i-h616-pinctrl";
0d17c8651188816 Andre Przywara 2022-07-08  288  			reg = <0x0300b000 0x400>;
0d17c8651188816 Andre Przywara 2022-07-08  289  			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
0d17c8651188816 Andre Przywara 2022-07-08  290  				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
0d17c8651188816 Andre Przywara 2022-07-08  291  				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
0d17c8651188816 Andre Przywara 2022-07-08  292  				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
0d17c8651188816 Andre Przywara 2022-07-08  293  				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
0d17c8651188816 Andre Przywara 2022-07-08  294  				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0d17c8651188816 Andre Przywara 2022-07-08  295  				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
0d17c8651188816 Andre Przywara 2022-07-08  296  				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  297  			clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
0d17c8651188816 Andre Przywara 2022-07-08  298  			clock-names = "apb", "hosc", "losc";
0d17c8651188816 Andre Przywara 2022-07-08  299  			gpio-controller;
0d17c8651188816 Andre Przywara 2022-07-08  300  			#gpio-cells = <3>;
0d17c8651188816 Andre Przywara 2022-07-08  301  			interrupt-controller;
0d17c8651188816 Andre Przywara 2022-07-08  302  			#interrupt-cells = <3>;
0d17c8651188816 Andre Przywara 2022-07-08  303  
0d17c8651188816 Andre Przywara 2022-07-08  304  			ext_rgmii_pins: rgmii-pins {
0d17c8651188816 Andre Przywara 2022-07-08  305  				pins = "PI0", "PI1", "PI2", "PI3", "PI4",
0d17c8651188816 Andre Przywara 2022-07-08  306  				       "PI5", "PI7", "PI8", "PI9", "PI10",
0d17c8651188816 Andre Przywara 2022-07-08  307  				       "PI11", "PI12", "PI13", "PI14", "PI15",
0d17c8651188816 Andre Przywara 2022-07-08  308  				       "PI16";
0d17c8651188816 Andre Przywara 2022-07-08  309  				function = "emac0";
0d17c8651188816 Andre Przywara 2022-07-08  310  				drive-strength = <40>;
0d17c8651188816 Andre Przywara 2022-07-08  311  			};
0d17c8651188816 Andre Przywara 2022-07-08  312  
0d17c8651188816 Andre Przywara 2022-07-08  313  			i2c0_pins: i2c0-pins {
5bdeb3d2e240e59 Andre Przywara 2024-03-29  314  				pins = "PI5", "PI6";
0d17c8651188816 Andre Przywara 2022-07-08  315  				function = "i2c0";
0d17c8651188816 Andre Przywara 2022-07-08  316  			};
0d17c8651188816 Andre Przywara 2022-07-08  317  
0d17c8651188816 Andre Przywara 2022-07-08  318  			i2c3_ph_pins: i2c3-ph-pins {
0d17c8651188816 Andre Przywara 2022-07-08  319  				pins = "PH4", "PH5";
0d17c8651188816 Andre Przywara 2022-07-08  320  				function = "i2c3";
0d17c8651188816 Andre Przywara 2022-07-08  321  			};
0d17c8651188816 Andre Przywara 2022-07-08  322  
0d17c8651188816 Andre Przywara 2022-07-08  323  			ir_rx_pin: ir-rx-pin {
0d17c8651188816 Andre Przywara 2022-07-08  324  				pins = "PH10";
0d17c8651188816 Andre Przywara 2022-07-08  325  				function = "ir_rx";
0d17c8651188816 Andre Przywara 2022-07-08  326  			};
0d17c8651188816 Andre Przywara 2022-07-08  327  
0d17c8651188816 Andre Przywara 2022-07-08  328  			mmc0_pins: mmc0-pins {
0d17c8651188816 Andre Przywara 2022-07-08  329  				pins = "PF0", "PF1", "PF2", "PF3",
0d17c8651188816 Andre Przywara 2022-07-08  330  				       "PF4", "PF5";
0d17c8651188816 Andre Przywara 2022-07-08  331  				function = "mmc0";
0d17c8651188816 Andre Przywara 2022-07-08  332  				drive-strength = <30>;
0d17c8651188816 Andre Przywara 2022-07-08  333  				bias-pull-up;
0d17c8651188816 Andre Przywara 2022-07-08  334  			};
0d17c8651188816 Andre Przywara 2022-07-08  335  
0d17c8651188816 Andre Przywara 2022-07-08  336  			/omit-if-no-ref/
0d17c8651188816 Andre Przywara 2022-07-08  337  			mmc1_pins: mmc1-pins {
0d17c8651188816 Andre Przywara 2022-07-08  338  				pins = "PG0", "PG1", "PG2", "PG3",
0d17c8651188816 Andre Przywara 2022-07-08  339  				       "PG4", "PG5";
0d17c8651188816 Andre Przywara 2022-07-08  340  				function = "mmc1";
0d17c8651188816 Andre Przywara 2022-07-08  341  				drive-strength = <30>;
0d17c8651188816 Andre Przywara 2022-07-08  342  				bias-pull-up;
0d17c8651188816 Andre Przywara 2022-07-08  343  			};
0d17c8651188816 Andre Przywara 2022-07-08  344  
0d17c8651188816 Andre Przywara 2022-07-08  345  			mmc2_pins: mmc2-pins {
0d17c8651188816 Andre Przywara 2022-07-08  346  				pins = "PC0", "PC1", "PC5", "PC6",
0d17c8651188816 Andre Przywara 2022-07-08  347  				       "PC8", "PC9", "PC10", "PC11",
0d17c8651188816 Andre Przywara 2022-07-08  348  				       "PC13", "PC14", "PC15", "PC16";
0d17c8651188816 Andre Przywara 2022-07-08  349  				function = "mmc2";
0d17c8651188816 Andre Przywara 2022-07-08  350  				drive-strength = <30>;
0d17c8651188816 Andre Przywara 2022-07-08  351  				bias-pull-up;
0d17c8651188816 Andre Przywara 2022-07-08  352  			};
0d17c8651188816 Andre Przywara 2022-07-08  353  
0d17c8651188816 Andre Przywara 2022-07-08  354  			/omit-if-no-ref/
0d17c8651188816 Andre Przywara 2022-07-08  355  			spi0_pins: spi0-pins {
0d17c8651188816 Andre Przywara 2022-07-08  356  				pins = "PC0", "PC2", "PC4";
0d17c8651188816 Andre Przywara 2022-07-08  357  				function = "spi0";
0d17c8651188816 Andre Przywara 2022-07-08  358  			};
0d17c8651188816 Andre Przywara 2022-07-08  359  
0d17c8651188816 Andre Przywara 2022-07-08  360  			/omit-if-no-ref/
0d17c8651188816 Andre Przywara 2022-07-08  361  			spi0_cs0_pin: spi0-cs0-pin {
0d17c8651188816 Andre Przywara 2022-07-08  362  				pins = "PC3";
0d17c8651188816 Andre Przywara 2022-07-08  363  				function = "spi0";
0d17c8651188816 Andre Przywara 2022-07-08  364  			};
0d17c8651188816 Andre Przywara 2022-07-08  365  
0d17c8651188816 Andre Przywara 2022-07-08  366  			/omit-if-no-ref/
0d17c8651188816 Andre Przywara 2022-07-08  367  			spi1_pins: spi1-pins {
0d17c8651188816 Andre Przywara 2022-07-08  368  				pins = "PH6", "PH7", "PH8";
0d17c8651188816 Andre Przywara 2022-07-08  369  				function = "spi1";
0d17c8651188816 Andre Przywara 2022-07-08  370  			};
0d17c8651188816 Andre Przywara 2022-07-08  371  
0d17c8651188816 Andre Przywara 2022-07-08  372  			/omit-if-no-ref/
0d17c8651188816 Andre Przywara 2022-07-08  373  			spi1_cs0_pin: spi1-cs0-pin {
0d17c8651188816 Andre Przywara 2022-07-08  374  				pins = "PH5";
0d17c8651188816 Andre Przywara 2022-07-08  375  				function = "spi1";
0d17c8651188816 Andre Przywara 2022-07-08  376  			};
0d17c8651188816 Andre Przywara 2022-07-08  377  
fe5128a11f9b5c4 Chen-Yu Tsai   2024-01-28  378  			spdif_tx_pin: spdif-tx-pin {
fe5128a11f9b5c4 Chen-Yu Tsai   2024-01-28  379  				pins = "PH4";
fe5128a11f9b5c4 Chen-Yu Tsai   2024-01-28  380  				function = "spdif";
fe5128a11f9b5c4 Chen-Yu Tsai   2024-01-28  381  			};
fe5128a11f9b5c4 Chen-Yu Tsai   2024-01-28  382  
0d17c8651188816 Andre Przywara 2022-07-08  383  			uart0_ph_pins: uart0-ph-pins {
0d17c8651188816 Andre Przywara 2022-07-08  384  				pins = "PH0", "PH1";
0d17c8651188816 Andre Przywara 2022-07-08  385  				function = "uart0";
0d17c8651188816 Andre Przywara 2022-07-08  386  			};
0d17c8651188816 Andre Przywara 2022-07-08  387  
0d17c8651188816 Andre Przywara 2022-07-08  388  			/omit-if-no-ref/
0d17c8651188816 Andre Przywara 2022-07-08  389  			uart1_pins: uart1-pins {
0d17c8651188816 Andre Przywara 2022-07-08  390  				pins = "PG6", "PG7";
0d17c8651188816 Andre Przywara 2022-07-08  391  				function = "uart1";
0d17c8651188816 Andre Przywara 2022-07-08  392  			};
0d17c8651188816 Andre Przywara 2022-07-08  393  
0d17c8651188816 Andre Przywara 2022-07-08  394  			/omit-if-no-ref/
0d17c8651188816 Andre Przywara 2022-07-08  395  			uart1_rts_cts_pins: uart1-rts-cts-pins {
0d17c8651188816 Andre Przywara 2022-07-08  396  				pins = "PG8", "PG9";
0d17c8651188816 Andre Przywara 2022-07-08  397  				function = "uart1";
0d17c8651188816 Andre Przywara 2022-07-08  398  			};
9583c8d91491f51 Andre Przywara 2024-02-09  399  
9583c8d91491f51 Andre Przywara 2024-02-09  400  			/omit-if-no-ref/
9583c8d91491f51 Andre Przywara 2024-02-09  401  			x32clk_fanout_pin: x32clk-fanout-pin {
9583c8d91491f51 Andre Przywara 2024-02-09  402  				pins = "PG10";
9583c8d91491f51 Andre Przywara 2024-02-09  403  				function = "clock";
9583c8d91491f51 Andre Przywara 2024-02-09  404  			};
0d17c8651188816 Andre Przywara 2022-07-08  405  		};
0d17c8651188816 Andre Przywara 2022-07-08  406  
0d17c8651188816 Andre Przywara 2022-07-08  407  		gic: interrupt-controller@3021000 {
0d17c8651188816 Andre Przywara 2022-07-08  408  			compatible = "arm,gic-400";
0d17c8651188816 Andre Przywara 2022-07-08  409  			reg = <0x03021000 0x1000>,
0d17c8651188816 Andre Przywara 2022-07-08  410  			      <0x03022000 0x2000>,
0d17c8651188816 Andre Przywara 2022-07-08  411  			      <0x03024000 0x2000>,
0d17c8651188816 Andre Przywara 2022-07-08  412  			      <0x03026000 0x2000>;
0d17c8651188816 Andre Przywara 2022-07-08  413  			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0d17c8651188816 Andre Przywara 2022-07-08  414  			interrupt-controller;
0d17c8651188816 Andre Przywara 2022-07-08  415  			#interrupt-cells = <3>;
0d17c8651188816 Andre Przywara 2022-07-08  416  		};
0d17c8651188816 Andre Przywara 2022-07-08  417  
0c85e2e377c368e Andre Przywara 2024-06-16  418  		iommu: iommu@30f0000 {
0c85e2e377c368e Andre Przywara 2024-06-16  419  			compatible = "allwinner,sun50i-h616-iommu";
0c85e2e377c368e Andre Przywara 2024-06-16  420  			reg = <0x030f0000 0x10000>;
0c85e2e377c368e Andre Przywara 2024-06-16  421  			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0c85e2e377c368e Andre Przywara 2024-06-16  422  			clocks = <&ccu CLK_BUS_IOMMU>;
0c85e2e377c368e Andre Przywara 2024-06-16  423  			resets = <&ccu RST_BUS_IOMMU>;
0c85e2e377c368e Andre Przywara 2024-06-16  424  			#iommu-cells = <1>;
0c85e2e377c368e Andre Przywara 2024-06-16  425  		};
0c85e2e377c368e Andre Przywara 2024-06-16  426  
0d17c8651188816 Andre Przywara 2022-07-08  427  		mmc0: mmc@4020000 {
0d17c8651188816 Andre Przywara 2022-07-08  428  			compatible = "allwinner,sun50i-h616-mmc",
0d17c8651188816 Andre Przywara 2022-07-08  429  				     "allwinner,sun50i-a100-mmc";
0d17c8651188816 Andre Przywara 2022-07-08  430  			reg = <0x04020000 0x1000>;
0d17c8651188816 Andre Przywara 2022-07-08  431  			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
0d17c8651188816 Andre Przywara 2022-07-08  432  			clock-names = "ahb", "mmc";
0d17c8651188816 Andre Przywara 2022-07-08  433  			resets = <&ccu RST_BUS_MMC0>;
0d17c8651188816 Andre Przywara 2022-07-08  434  			reset-names = "ahb";
0d17c8651188816 Andre Przywara 2022-07-08  435  			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  436  			pinctrl-names = "default";
0d17c8651188816 Andre Przywara 2022-07-08  437  			pinctrl-0 = <&mmc0_pins>;
0d17c8651188816 Andre Przywara 2022-07-08  438  			status = "disabled";
0d17c8651188816 Andre Przywara 2022-07-08  439  			max-frequency = <150000000>;
0d17c8651188816 Andre Przywara 2022-07-08  440  			cap-sd-highspeed;
0d17c8651188816 Andre Przywara 2022-07-08  441  			cap-mmc-highspeed;
0d17c8651188816 Andre Przywara 2022-07-08  442  			mmc-ddr-3_3v;
0d17c8651188816 Andre Przywara 2022-07-08  443  			cap-sdio-irq;
0d17c8651188816 Andre Przywara 2022-07-08  444  			#address-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  445  			#size-cells = <0>;
0d17c8651188816 Andre Przywara 2022-07-08  446  		};
0d17c8651188816 Andre Przywara 2022-07-08  447  
0d17c8651188816 Andre Przywara 2022-07-08  448  		mmc1: mmc@4021000 {
0d17c8651188816 Andre Przywara 2022-07-08  449  			compatible = "allwinner,sun50i-h616-mmc",
0d17c8651188816 Andre Przywara 2022-07-08  450  				     "allwinner,sun50i-a100-mmc";
0d17c8651188816 Andre Przywara 2022-07-08  451  			reg = <0x04021000 0x1000>;
0d17c8651188816 Andre Przywara 2022-07-08  452  			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
0d17c8651188816 Andre Przywara 2022-07-08  453  			clock-names = "ahb", "mmc";
0d17c8651188816 Andre Przywara 2022-07-08  454  			resets = <&ccu RST_BUS_MMC1>;
0d17c8651188816 Andre Przywara 2022-07-08  455  			reset-names = "ahb";
0d17c8651188816 Andre Przywara 2022-07-08  456  			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  457  			pinctrl-names = "default";
0d17c8651188816 Andre Przywara 2022-07-08  458  			pinctrl-0 = <&mmc1_pins>;
0d17c8651188816 Andre Przywara 2022-07-08  459  			status = "disabled";
0d17c8651188816 Andre Przywara 2022-07-08  460  			max-frequency = <150000000>;
0d17c8651188816 Andre Przywara 2022-07-08  461  			cap-sd-highspeed;
0d17c8651188816 Andre Przywara 2022-07-08  462  			cap-mmc-highspeed;
0d17c8651188816 Andre Przywara 2022-07-08  463  			mmc-ddr-3_3v;
0d17c8651188816 Andre Przywara 2022-07-08  464  			cap-sdio-irq;
0d17c8651188816 Andre Przywara 2022-07-08  465  			#address-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  466  			#size-cells = <0>;
0d17c8651188816 Andre Przywara 2022-07-08  467  		};
0d17c8651188816 Andre Przywara 2022-07-08  468  
0d17c8651188816 Andre Przywara 2022-07-08  469  		mmc2: mmc@4022000 {
0d17c8651188816 Andre Przywara 2022-07-08  470  			compatible = "allwinner,sun50i-h616-emmc",
0d17c8651188816 Andre Przywara 2022-07-08  471  				     "allwinner,sun50i-a100-emmc";
0d17c8651188816 Andre Przywara 2022-07-08  472  			reg = <0x04022000 0x1000>;
0d17c8651188816 Andre Przywara 2022-07-08  473  			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
0d17c8651188816 Andre Przywara 2022-07-08  474  			clock-names = "ahb", "mmc";
0d17c8651188816 Andre Przywara 2022-07-08  475  			resets = <&ccu RST_BUS_MMC2>;
0d17c8651188816 Andre Przywara 2022-07-08  476  			reset-names = "ahb";
0d17c8651188816 Andre Przywara 2022-07-08  477  			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  478  			pinctrl-names = "default";
0d17c8651188816 Andre Przywara 2022-07-08  479  			pinctrl-0 = <&mmc2_pins>;
0d17c8651188816 Andre Przywara 2022-07-08  480  			status = "disabled";
0d17c8651188816 Andre Przywara 2022-07-08  481  			max-frequency = <150000000>;
0d17c8651188816 Andre Przywara 2022-07-08  482  			cap-sd-highspeed;
0d17c8651188816 Andre Przywara 2022-07-08  483  			cap-mmc-highspeed;
0d17c8651188816 Andre Przywara 2022-07-08  484  			mmc-ddr-3_3v;
0d17c8651188816 Andre Przywara 2022-07-08  485  			cap-sdio-irq;
0d17c8651188816 Andre Przywara 2022-07-08  486  			#address-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  487  			#size-cells = <0>;
0d17c8651188816 Andre Przywara 2022-07-08  488  		};
0d17c8651188816 Andre Przywara 2022-07-08  489  
0d17c8651188816 Andre Przywara 2022-07-08  490  		uart0: serial@5000000 {
0d17c8651188816 Andre Przywara 2022-07-08  491  			compatible = "snps,dw-apb-uart";
0d17c8651188816 Andre Przywara 2022-07-08  492  			reg = <0x05000000 0x400>;
0d17c8651188816 Andre Przywara 2022-07-08  493  			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  494  			reg-shift = <2>;
0d17c8651188816 Andre Przywara 2022-07-08  495  			reg-io-width = <4>;
0d17c8651188816 Andre Przywara 2022-07-08  496  			clocks = <&ccu CLK_BUS_UART0>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  497  			dmas = <&dma 14>, <&dma 14>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  498  			dma-names = "tx", "rx";
0d17c8651188816 Andre Przywara 2022-07-08  499  			resets = <&ccu RST_BUS_UART0>;
0d17c8651188816 Andre Przywara 2022-07-08  500  			status = "disabled";
0d17c8651188816 Andre Przywara 2022-07-08  501  		};
0d17c8651188816 Andre Przywara 2022-07-08  502  
0d17c8651188816 Andre Przywara 2022-07-08  503  		uart1: serial@5000400 {
0d17c8651188816 Andre Przywara 2022-07-08  504  			compatible = "snps,dw-apb-uart";
0d17c8651188816 Andre Przywara 2022-07-08  505  			reg = <0x05000400 0x400>;
0d17c8651188816 Andre Przywara 2022-07-08  506  			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  507  			reg-shift = <2>;
0d17c8651188816 Andre Przywara 2022-07-08  508  			reg-io-width = <4>;
0d17c8651188816 Andre Przywara 2022-07-08  509  			clocks = <&ccu CLK_BUS_UART1>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  510  			dmas = <&dma 15>, <&dma 15>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  511  			dma-names = "tx", "rx";
0d17c8651188816 Andre Przywara 2022-07-08  512  			resets = <&ccu RST_BUS_UART1>;
0d17c8651188816 Andre Przywara 2022-07-08  513  			status = "disabled";
0d17c8651188816 Andre Przywara 2022-07-08  514  		};
0d17c8651188816 Andre Przywara 2022-07-08  515  
0d17c8651188816 Andre Przywara 2022-07-08  516  		uart2: serial@5000800 {
0d17c8651188816 Andre Przywara 2022-07-08  517  			compatible = "snps,dw-apb-uart";
0d17c8651188816 Andre Przywara 2022-07-08  518  			reg = <0x05000800 0x400>;
0d17c8651188816 Andre Przywara 2022-07-08  519  			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  520  			reg-shift = <2>;
0d17c8651188816 Andre Przywara 2022-07-08  521  			reg-io-width = <4>;
0d17c8651188816 Andre Przywara 2022-07-08  522  			clocks = <&ccu CLK_BUS_UART2>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  523  			dmas = <&dma 16>, <&dma 16>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  524  			dma-names = "tx", "rx";
0d17c8651188816 Andre Przywara 2022-07-08  525  			resets = <&ccu RST_BUS_UART2>;
0d17c8651188816 Andre Przywara 2022-07-08  526  			status = "disabled";
0d17c8651188816 Andre Przywara 2022-07-08  527  		};
0d17c8651188816 Andre Przywara 2022-07-08  528  
0d17c8651188816 Andre Przywara 2022-07-08  529  		uart3: serial@5000c00 {
0d17c8651188816 Andre Przywara 2022-07-08  530  			compatible = "snps,dw-apb-uart";
0d17c8651188816 Andre Przywara 2022-07-08  531  			reg = <0x05000c00 0x400>;
0d17c8651188816 Andre Przywara 2022-07-08  532  			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  533  			reg-shift = <2>;
0d17c8651188816 Andre Przywara 2022-07-08  534  			reg-io-width = <4>;
0d17c8651188816 Andre Przywara 2022-07-08  535  			clocks = <&ccu CLK_BUS_UART3>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  536  			dmas = <&dma 17>, <&dma 17>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  537  			dma-names = "tx", "rx";
0d17c8651188816 Andre Przywara 2022-07-08  538  			resets = <&ccu RST_BUS_UART3>;
0d17c8651188816 Andre Przywara 2022-07-08  539  			status = "disabled";
0d17c8651188816 Andre Przywara 2022-07-08  540  		};
0d17c8651188816 Andre Przywara 2022-07-08  541  
0d17c8651188816 Andre Przywara 2022-07-08  542  		uart4: serial@5001000 {
0d17c8651188816 Andre Przywara 2022-07-08  543  			compatible = "snps,dw-apb-uart";
0d17c8651188816 Andre Przywara 2022-07-08  544  			reg = <0x05001000 0x400>;
0d17c8651188816 Andre Przywara 2022-07-08  545  			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  546  			reg-shift = <2>;
0d17c8651188816 Andre Przywara 2022-07-08  547  			reg-io-width = <4>;
0d17c8651188816 Andre Przywara 2022-07-08  548  			clocks = <&ccu CLK_BUS_UART4>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  549  			dmas = <&dma 18>, <&dma 18>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  550  			dma-names = "tx", "rx";
0d17c8651188816 Andre Przywara 2022-07-08  551  			resets = <&ccu RST_BUS_UART4>;
0d17c8651188816 Andre Przywara 2022-07-08  552  			status = "disabled";
0d17c8651188816 Andre Przywara 2022-07-08  553  		};
0d17c8651188816 Andre Przywara 2022-07-08  554  
0d17c8651188816 Andre Przywara 2022-07-08  555  		uart5: serial@5001400 {
0d17c8651188816 Andre Przywara 2022-07-08  556  			compatible = "snps,dw-apb-uart";
0d17c8651188816 Andre Przywara 2022-07-08  557  			reg = <0x05001400 0x400>;
0d17c8651188816 Andre Przywara 2022-07-08  558  			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  559  			reg-shift = <2>;
0d17c8651188816 Andre Przywara 2022-07-08  560  			reg-io-width = <4>;
0d17c8651188816 Andre Przywara 2022-07-08  561  			clocks = <&ccu CLK_BUS_UART5>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  562  			dmas = <&dma 19>, <&dma 19>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  563  			dma-names = "tx", "rx";
0d17c8651188816 Andre Przywara 2022-07-08  564  			resets = <&ccu RST_BUS_UART5>;
0d17c8651188816 Andre Przywara 2022-07-08  565  			status = "disabled";
0d17c8651188816 Andre Przywara 2022-07-08  566  		};
0d17c8651188816 Andre Przywara 2022-07-08  567  
0d17c8651188816 Andre Przywara 2022-07-08  568  		i2c0: i2c@5002000 {
0d17c8651188816 Andre Przywara 2022-07-08  569  			compatible = "allwinner,sun50i-h616-i2c",
0d17c8651188816 Andre Przywara 2022-07-08  570  				     "allwinner,sun8i-v536-i2c",
0d17c8651188816 Andre Przywara 2022-07-08  571  				     "allwinner,sun6i-a31-i2c";
0d17c8651188816 Andre Przywara 2022-07-08  572  			reg = <0x05002000 0x400>;
0d17c8651188816 Andre Przywara 2022-07-08  573  			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  574  			clocks = <&ccu CLK_BUS_I2C0>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  575  			dmas = <&dma 43>, <&dma 43>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  576  			dma-names = "rx", "tx";
0d17c8651188816 Andre Przywara 2022-07-08  577  			resets = <&ccu RST_BUS_I2C0>;
0d17c8651188816 Andre Przywara 2022-07-08  578  			pinctrl-names = "default";
0d17c8651188816 Andre Przywara 2022-07-08  579  			pinctrl-0 = <&i2c0_pins>;
0d17c8651188816 Andre Przywara 2022-07-08  580  			status = "disabled";
0d17c8651188816 Andre Przywara 2022-07-08  581  			#address-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  582  			#size-cells = <0>;
0d17c8651188816 Andre Przywara 2022-07-08  583  		};
0d17c8651188816 Andre Przywara 2022-07-08  584  
0d17c8651188816 Andre Przywara 2022-07-08  585  		i2c1: i2c@5002400 {
0d17c8651188816 Andre Przywara 2022-07-08  586  			compatible = "allwinner,sun50i-h616-i2c",
0d17c8651188816 Andre Przywara 2022-07-08  587  				     "allwinner,sun8i-v536-i2c",
0d17c8651188816 Andre Przywara 2022-07-08  588  				     "allwinner,sun6i-a31-i2c";
0d17c8651188816 Andre Przywara 2022-07-08  589  			reg = <0x05002400 0x400>;
0d17c8651188816 Andre Przywara 2022-07-08  590  			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  591  			clocks = <&ccu CLK_BUS_I2C1>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  592  			dmas = <&dma 44>, <&dma 44>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  593  			dma-names = "rx", "tx";
0d17c8651188816 Andre Przywara 2022-07-08  594  			resets = <&ccu RST_BUS_I2C1>;
0d17c8651188816 Andre Przywara 2022-07-08  595  			status = "disabled";
0d17c8651188816 Andre Przywara 2022-07-08  596  			#address-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  597  			#size-cells = <0>;
0d17c8651188816 Andre Przywara 2022-07-08  598  		};
0d17c8651188816 Andre Przywara 2022-07-08  599  
0d17c8651188816 Andre Przywara 2022-07-08  600  		i2c2: i2c@5002800 {
0d17c8651188816 Andre Przywara 2022-07-08  601  			compatible = "allwinner,sun50i-h616-i2c",
0d17c8651188816 Andre Przywara 2022-07-08  602  				     "allwinner,sun8i-v536-i2c",
0d17c8651188816 Andre Przywara 2022-07-08  603  				     "allwinner,sun6i-a31-i2c";
0d17c8651188816 Andre Przywara 2022-07-08  604  			reg = <0x05002800 0x400>;
0d17c8651188816 Andre Przywara 2022-07-08  605  			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  606  			clocks = <&ccu CLK_BUS_I2C2>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  607  			dmas = <&dma 45>, <&dma 45>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  608  			dma-names = "rx", "tx";
0d17c8651188816 Andre Przywara 2022-07-08  609  			resets = <&ccu RST_BUS_I2C2>;
0d17c8651188816 Andre Przywara 2022-07-08  610  			status = "disabled";
0d17c8651188816 Andre Przywara 2022-07-08  611  			#address-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  612  			#size-cells = <0>;
0d17c8651188816 Andre Przywara 2022-07-08  613  		};
0d17c8651188816 Andre Przywara 2022-07-08  614  
0d17c8651188816 Andre Przywara 2022-07-08  615  		i2c3: i2c@5002c00 {
0d17c8651188816 Andre Przywara 2022-07-08  616  			compatible = "allwinner,sun50i-h616-i2c",
0d17c8651188816 Andre Przywara 2022-07-08  617  				     "allwinner,sun8i-v536-i2c",
0d17c8651188816 Andre Przywara 2022-07-08  618  				     "allwinner,sun6i-a31-i2c";
0d17c8651188816 Andre Przywara 2022-07-08  619  			reg = <0x05002c00 0x400>;
0d17c8651188816 Andre Przywara 2022-07-08  620  			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  621  			clocks = <&ccu CLK_BUS_I2C3>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  622  			dmas = <&dma 46>, <&dma 46>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  623  			dma-names = "rx", "tx";
0d17c8651188816 Andre Przywara 2022-07-08  624  			resets = <&ccu RST_BUS_I2C3>;
0d17c8651188816 Andre Przywara 2022-07-08  625  			status = "disabled";
0d17c8651188816 Andre Przywara 2022-07-08  626  			#address-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  627  			#size-cells = <0>;
0d17c8651188816 Andre Przywara 2022-07-08  628  		};
0d17c8651188816 Andre Przywara 2022-07-08  629  
0d17c8651188816 Andre Przywara 2022-07-08  630  		i2c4: i2c@5003000 {
0d17c8651188816 Andre Przywara 2022-07-08  631  			compatible = "allwinner,sun50i-h616-i2c",
0d17c8651188816 Andre Przywara 2022-07-08  632  				     "allwinner,sun8i-v536-i2c",
0d17c8651188816 Andre Przywara 2022-07-08  633  				     "allwinner,sun6i-a31-i2c";
0d17c8651188816 Andre Przywara 2022-07-08  634  			reg = <0x05003000 0x400>;
0d17c8651188816 Andre Przywara 2022-07-08  635  			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  636  			clocks = <&ccu CLK_BUS_I2C4>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  637  			dmas = <&dma 47>, <&dma 47>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  638  			dma-names = "rx", "tx";
0d17c8651188816 Andre Przywara 2022-07-08  639  			resets = <&ccu RST_BUS_I2C4>;
0d17c8651188816 Andre Przywara 2022-07-08  640  			status = "disabled";
0d17c8651188816 Andre Przywara 2022-07-08  641  			#address-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  642  			#size-cells = <0>;
0d17c8651188816 Andre Przywara 2022-07-08  643  		};
0d17c8651188816 Andre Przywara 2022-07-08  644  
0d17c8651188816 Andre Przywara 2022-07-08  645  		spi0: spi@5010000 {
0d17c8651188816 Andre Przywara 2022-07-08  646  			compatible = "allwinner,sun50i-h616-spi",
0d17c8651188816 Andre Przywara 2022-07-08  647  				     "allwinner,sun8i-h3-spi";
0d17c8651188816 Andre Przywara 2022-07-08  648  			reg = <0x05010000 0x1000>;
0d17c8651188816 Andre Przywara 2022-07-08  649  			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  650  			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
0d17c8651188816 Andre Przywara 2022-07-08  651  			clock-names = "ahb", "mod";
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  652  			dmas = <&dma 22>, <&dma 22>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  653  			dma-names = "rx", "tx";
0d17c8651188816 Andre Przywara 2022-07-08  654  			resets = <&ccu RST_BUS_SPI0>;
0d17c8651188816 Andre Przywara 2022-07-08  655  			status = "disabled";
0d17c8651188816 Andre Przywara 2022-07-08  656  			#address-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  657  			#size-cells = <0>;
0d17c8651188816 Andre Przywara 2022-07-08  658  		};
0d17c8651188816 Andre Przywara 2022-07-08  659  
0d17c8651188816 Andre Przywara 2022-07-08  660  		spi1: spi@5011000 {
0d17c8651188816 Andre Przywara 2022-07-08  661  			compatible = "allwinner,sun50i-h616-spi",
0d17c8651188816 Andre Przywara 2022-07-08  662  				     "allwinner,sun8i-h3-spi";
0d17c8651188816 Andre Przywara 2022-07-08  663  			reg = <0x05011000 0x1000>;
0d17c8651188816 Andre Przywara 2022-07-08  664  			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  665  			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
0d17c8651188816 Andre Przywara 2022-07-08  666  			clock-names = "ahb", "mod";
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  667  			dmas = <&dma 23>, <&dma 23>;
238f65fc31f79fe Chen-Yu Tsai   2024-01-28  668  			dma-names = "rx", "tx";
0d17c8651188816 Andre Przywara 2022-07-08  669  			resets = <&ccu RST_BUS_SPI1>;
0d17c8651188816 Andre Przywara 2022-07-08  670  			status = "disabled";
0d17c8651188816 Andre Przywara 2022-07-08  671  			#address-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  672  			#size-cells = <0>;
0d17c8651188816 Andre Przywara 2022-07-08  673  		};
0d17c8651188816 Andre Przywara 2022-07-08  674  
0d17c8651188816 Andre Przywara 2022-07-08  675  		emac0: ethernet@5020000 {
0d17c8651188816 Andre Przywara 2022-07-08  676  			compatible = "allwinner,sun50i-h616-emac0",
0d17c8651188816 Andre Przywara 2022-07-08  677  				     "allwinner,sun50i-a64-emac";
0d17c8651188816 Andre Przywara 2022-07-08  678  			reg = <0x05020000 0x10000>;
0d17c8651188816 Andre Przywara 2022-07-08  679  			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0d17c8651188816 Andre Przywara 2022-07-08  680  			interrupt-names = "macirq";
0d17c8651188816 Andre Przywara 2022-07-08  681  			clocks = <&ccu CLK_BUS_EMAC0>;
0d17c8651188816 Andre Przywara 2022-07-08  682  			clock-names = "stmmaceth";
0d17c8651188816 Andre Przywara 2022-07-08  683  			resets = <&ccu RST_BUS_EMAC0>;
0d17c8651188816 Andre Przywara 2022-07-08  684  			reset-names = "stmmaceth";
0d17c8651188816 Andre Przywara 2022-07-08  685  			syscon = <&syscon>;
0d17c8651188816 Andre Przywara 2022-07-08  686  			status = "disabled";
0d17c8651188816 Andre Przywara 2022-07-08  687  
0d17c8651188816 Andre Przywara 2022-07-08  688  			mdio0: mdio {
0d17c8651188816 Andre Przywara 2022-07-08  689  				compatible = "snps,dwmac-mdio";
0d17c8651188816 Andre Przywara 2022-07-08  690  				#address-cells = <1>;
0d17c8651188816 Andre Przywara 2022-07-08  691  				#size-cells = <0>;
0d17c8651188816 Andre Przywara 2022-07-08  692  			};
0d17c8651188816 Andre Przywara 2022-07-08  693  		};
0d17c8651188816 Andre Przywara 2022-07-08  694  
59678cc9cc54e55 Chris Morgan   2024-06-05  695  		gpadc: adc@5070000 {
59678cc9cc54e55 Chris Morgan   2024-06-05  696  			compatible = "allwinner,sun50i-h616-gpadc",
59678cc9cc54e55 Chris Morgan   2024-06-05  697  				     "allwinner,sun20i-d1-gpadc";
59678cc9cc54e55 Chris Morgan   2024-06-05  698  			reg = <0x05070000 0x400>;
59678cc9cc54e55 Chris Morgan   2024-06-05  699  			clocks = <&ccu CLK_BUS_GPADC>;
59678cc9cc54e55 Chris Morgan   2024-06-05  700  			resets = <&ccu RST_BUS_GPADC>;
59678cc9cc54e55 Chris Morgan   2024-06-05  701  			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
59678cc9cc54e55 Chris Morgan   2024-06-05  702  			status = "disabled";
59678cc9cc54e55 Chris Morgan   2024-06-05  703  			#io-channel-cells = <1>;
59678cc9cc54e55 Chris Morgan   2024-06-05  704  		};
59678cc9cc54e55 Chris Morgan   2024-06-05  705  
f4318af40544b8e Martin Botka   2024-02-19  706  		ths: thermal-sensor@5070400 {
f4318af40544b8e Martin Botka   2024-02-19  707  			compatible = "allwinner,sun50i-h616-ths";
f4318af40544b8e Martin Botka   2024-02-19  708  			reg = <0x05070400 0x400>;
f4318af40544b8e Martin Botka   2024-02-19  709  			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
f4318af40544b8e Martin Botka   2024-02-19  710  			clocks = <&ccu CLK_BUS_THS>;
f4318af40544b8e Martin Botka   2024-02-19  711  			clock-names = "bus";
f4318af40544b8e Martin Botka   2024-02-19  712  			resets = <&ccu RST_BUS_THS>;
f4318af40544b8e Martin Botka   2024-02-19  713  			nvmem-cells = <&ths_calibration>;
f4318af40544b8e Martin Botka   2024-02-19  714  			nvmem-cell-names = "calibration";
f4318af40544b8e Martin Botka   2024-02-19  715  			allwinner,sram = <&syscon>;
f4318af40544b8e Martin Botka   2024-02-19  716  			#thermal-sensor-cells = <1>;
f4318af40544b8e Martin Botka   2024-02-19  717  		};
f4318af40544b8e Martin Botka   2024-02-19  718  
048ed5efbc4eec8 James McGregor 2024-04-26  719  		lradc: lradc@5070800 {
048ed5efbc4eec8 James McGregor 2024-04-26  720  			compatible = "allwinner,sun50i-h616-lradc",
048ed5efbc4eec8 James McGregor 2024-04-26  721  				     "allwinner,sun50i-r329-lradc";
048ed5efbc4eec8 James McGregor 2024-04-26  722  			reg = <0x05070800 0x400>;
048ed5efbc4eec8 James McGregor 2024-04-26  723  			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
048ed5efbc4eec8 James McGregor 2024-04-26  724  			clocks = <&ccu CLK_BUS_KEYADC>;
048ed5efbc4eec8 James McGregor 2024-04-26  725  			resets = <&ccu RST_BUS_KEYADC>;
048ed5efbc4eec8 James McGregor 2024-04-26  726  			status = "disabled";
048ed5efbc4eec8 James McGregor 2024-04-26  727  		};
048ed5efbc4eec8 James McGregor 2024-04-26  728  
3eef85034c96f61 Ryan Walklin   2024-10-23  729  		spdif: spdif@5093000 {
3eef85034c96f61 Ryan Walklin   2024-10-23  730  			compatible = "allwinner,sun50i-h616-spdif";
3eef85034c96f61 Ryan Walklin   2024-10-23  731  			reg = <0x05093000 0x400>;
3eef85034c96f61 Ryan Walklin   2024-10-23  732  			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
3eef85034c96f61 Ryan Walklin   2024-10-23  733  			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
3eef85034c96f61 Ryan Walklin   2024-10-23  734  			clock-names = "apb", "spdif";
3eef85034c96f61 Ryan Walklin   2024-10-23  735  			resets = <&ccu RST_BUS_SPDIF>;
3eef85034c96f61 Ryan Walklin   2024-10-23  736  			dmas = <&dma 2>;
3eef85034c96f61 Ryan Walklin   2024-10-23  737  			dma-names = "tx";
3eef85034c96f61 Ryan Walklin   2024-10-23  738  			pinctrl-names = "default";
3eef85034c96f61 Ryan Walklin   2024-10-23  739  			pinctrl-0 = <&spdif_tx_pin>;
3eef85034c96f61 Ryan Walklin   2024-10-23  740  			#sound-dai-cells = <0>;
3eef85034c96f61 Ryan Walklin   2024-10-23  741  			status = "disabled";
3eef85034c96f61 Ryan Walklin   2024-10-23  742  		};
3eef85034c96f61 Ryan Walklin   2024-10-23  743  
3eef85034c96f61 Ryan Walklin   2024-10-23  744  		codec: codec@5096000 {
3eef85034c96f61 Ryan Walklin   2024-10-23  745  			#sound-dai-cells = <0>;
3eef85034c96f61 Ryan Walklin   2024-10-23  746  			compatible = "allwinner,sun50i-h616-codec";
3eef85034c96f61 Ryan Walklin   2024-10-23  747  			reg = <0x05096000 0x31c>;
3eef85034c96f61 Ryan Walklin   2024-10-23  748  			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
3eef85034c96f61 Ryan Walklin   2024-10-23  749  			clocks = <&ccu CLK_BUS_AUDIO_CODEC>,
3eef85034c96f61 Ryan Walklin   2024-10-23  750  				 <&ccu CLK_AUDIO_CODEC_1X>;
3eef85034c96f61 Ryan Walklin   2024-10-23  751  			clock-names = "apb", "codec";
3eef85034c96f61 Ryan Walklin   2024-10-23  752  			resets = <&ccu RST_BUS_AUDIO_CODEC>;
3eef85034c96f61 Ryan Walklin   2024-10-23  753  			dmas = <&dma 6>;
3eef85034c96f61 Ryan Walklin   2024-10-23  754  			dma-names = "tx";
3eef85034c96f61 Ryan Walklin   2024-10-23  755  			status = "disabled";
3eef85034c96f61 Ryan Walklin   2024-10-23  756  		};
3eef85034c96f61 Ryan Walklin   2024-10-23  757  
f40cf244c3feb4e Andre Przywara 2022-10-31  758  		usbotg: usb@5100000 {
f40cf244c3feb4e Andre Przywara 2022-10-31  759  			compatible = "allwinner,sun50i-h616-musb",
f40cf244c3feb4e Andre Przywara 2022-10-31  760  				     "allwinner,sun8i-h3-musb";
f40cf244c3feb4e Andre Przywara 2022-10-31  761  			reg = <0x05100000 0x0400>;
f40cf244c3feb4e Andre Przywara 2022-10-31  762  			clocks = <&ccu CLK_BUS_OTG>;
f40cf244c3feb4e Andre Przywara 2022-10-31  763  			resets = <&ccu RST_BUS_OTG>;
f40cf244c3feb4e Andre Przywara 2022-10-31  764  			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
f40cf244c3feb4e Andre Przywara 2022-10-31  765  			interrupt-names = "mc";
f40cf244c3feb4e Andre Przywara 2022-10-31  766  			phys = <&usbphy 0>;
f40cf244c3feb4e Andre Przywara 2022-10-31  767  			phy-names = "usb";
f40cf244c3feb4e Andre Przywara 2022-10-31  768  			extcon = <&usbphy 0>;
f40cf244c3feb4e Andre Przywara 2022-10-31  769  			status = "disabled";
f40cf244c3feb4e Andre Przywara 2022-10-31  770  		};
f40cf244c3feb4e Andre Przywara 2022-10-31  771  
f40cf244c3feb4e Andre Przywara 2022-10-31  772  		usbphy: phy@5100400 {
f40cf244c3feb4e Andre Przywara 2022-10-31  773  			compatible = "allwinner,sun50i-h616-usb-phy";
f40cf244c3feb4e Andre Przywara 2022-10-31  774  			reg = <0x05100400 0x24>,
f40cf244c3feb4e Andre Przywara 2022-10-31  775  			      <0x05101800 0x14>,
f40cf244c3feb4e Andre Przywara 2022-10-31  776  			      <0x05200800 0x14>,
f40cf244c3feb4e Andre Przywara 2022-10-31  777  			      <0x05310800 0x14>,
f40cf244c3feb4e Andre Przywara 2022-10-31  778  			      <0x05311800 0x14>;
f40cf244c3feb4e Andre Przywara 2022-10-31  779  			reg-names = "phy_ctrl",
f40cf244c3feb4e Andre Przywara 2022-10-31  780  				    "pmu0",
f40cf244c3feb4e Andre Przywara 2022-10-31  781  				    "pmu1",
f40cf244c3feb4e Andre Przywara 2022-10-31  782  				    "pmu2",
f40cf244c3feb4e Andre Przywara 2022-10-31  783  				    "pmu3";
f40cf244c3feb4e Andre Przywara 2022-10-31  784  			clocks = <&ccu CLK_USB_PHY0>,
f40cf244c3feb4e Andre Przywara 2022-10-31  785  				 <&ccu CLK_USB_PHY1>,
f40cf244c3feb4e Andre Przywara 2022-10-31  786  				 <&ccu CLK_USB_PHY2>,
f40cf244c3feb4e Andre Przywara 2022-10-31  787  				 <&ccu CLK_USB_PHY3>,
f40cf244c3feb4e Andre Przywara 2022-10-31  788  				 <&ccu CLK_BUS_EHCI2>;
f40cf244c3feb4e Andre Przywara 2022-10-31  789  			clock-names = "usb0_phy",
f40cf244c3feb4e Andre Przywara 2022-10-31  790  				      "usb1_phy",
f40cf244c3feb4e Andre Przywara 2022-10-31  791  				      "usb2_phy",
f40cf244c3feb4e Andre Przywara 2022-10-31  792  				      "usb3_phy",
f40cf244c3feb4e Andre Przywara 2022-10-31  793  				      "pmu2_clk";
f40cf244c3feb4e Andre Przywara 2022-10-31  794  			resets = <&ccu RST_USB_PHY0>,
f40cf244c3feb4e Andre Przywara 2022-10-31  795  				 <&ccu RST_USB_PHY1>,
f40cf244c3feb4e Andre Przywara 2022-10-31  796  				 <&ccu RST_USB_PHY2>,
f40cf244c3feb4e Andre Przywara 2022-10-31  797  				 <&ccu RST_USB_PHY3>;
f40cf244c3feb4e Andre Przywara 2022-10-31  798  			reset-names = "usb0_reset",
f40cf244c3feb4e Andre Przywara 2022-10-31  799  				      "usb1_reset",
f40cf244c3feb4e Andre Przywara 2022-10-31  800  				      "usb2_reset",
f40cf244c3feb4e Andre Przywara 2022-10-31  801  				      "usb3_reset";
f40cf244c3feb4e Andre Przywara 2022-10-31  802  			status = "disabled";
f40cf244c3feb4e Andre Przywara 2022-10-31  803  			#phy-cells = <1>;
f40cf244c3feb4e Andre Przywara 2022-10-31  804  		};
f40cf244c3feb4e Andre Przywara 2022-10-31  805  
f40cf244c3feb4e Andre Przywara 2022-10-31  806  		ehci0: usb@5101000 {
f40cf244c3feb4e Andre Przywara 2022-10-31  807  			compatible = "allwinner,sun50i-h616-ehci",
f40cf244c3feb4e Andre Przywara 2022-10-31  808  				     "generic-ehci";
f40cf244c3feb4e Andre Przywara 2022-10-31  809  			reg = <0x05101000 0x100>;
f40cf244c3feb4e Andre Przywara 2022-10-31  810  			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
f40cf244c3feb4e Andre Przywara 2022-10-31  811  			clocks = <&ccu CLK_BUS_OHCI0>,
f40cf244c3feb4e Andre Przywara 2022-10-31  812  				 <&ccu CLK_BUS_EHCI0>,
f40cf244c3feb4e Andre Przywara 2022-10-31  813  				 <&ccu CLK_USB_OHCI0>;
f40cf244c3feb4e Andre Przywara 2022-10-31  814  			resets = <&ccu RST_BUS_OHCI0>,
f40cf244c3feb4e Andre Przywara 2022-10-31  815  				 <&ccu RST_BUS_EHCI0>;
f40cf244c3feb4e Andre Przywara 2022-10-31  816  			phys = <&usbphy 0>;
f40cf244c3feb4e Andre Przywara 2022-10-31  817  			phy-names = "usb";
f40cf244c3feb4e Andre Przywara 2022-10-31  818  			status = "disabled";
f40cf244c3feb4e Andre Przywara 2022-10-31  819  		};
f40cf244c3feb4e Andre Przywara 2022-10-31  820  
f40cf244c3feb4e Andre Przywara 2022-10-31  821  		ohci0: usb@5101400 {
f40cf244c3feb4e Andre Przywara 2022-10-31  822  			compatible = "allwinner,sun50i-h616-ohci",
f40cf244c3feb4e Andre Przywara 2022-10-31  823  				     "generic-ohci";
f40cf244c3feb4e Andre Przywara 2022-10-31  824  			reg = <0x05101400 0x100>;
f40cf244c3feb4e Andre Przywara 2022-10-31  825  			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
f40cf244c3feb4e Andre Przywara 2022-10-31  826  			clocks = <&ccu CLK_BUS_OHCI0>,
f40cf244c3feb4e Andre Przywara 2022-10-31  827  				 <&ccu CLK_USB_OHCI0>;
f40cf244c3feb4e Andre Przywara 2022-10-31  828  			resets = <&ccu RST_BUS_OHCI0>;
f40cf244c3feb4e Andre Przywara 2022-10-31  829  			phys = <&usbphy 0>;
f40cf244c3feb4e Andre Przywara 2022-10-31  830  			phy-names = "usb";
f40cf244c3feb4e Andre Przywara 2022-10-31  831  			status = "disabled";
f40cf244c3feb4e Andre Przywara 2022-10-31  832  		};
f40cf244c3feb4e Andre Przywara 2022-10-31  833  
f40cf244c3feb4e Andre Przywara 2022-10-31  834  		ehci1: usb@5200000 {
f40cf244c3feb4e Andre Przywara 2022-10-31  835  			compatible = "allwinner,sun50i-h616-ehci",
f40cf244c3feb4e Andre Przywara 2022-10-31  836  				     "generic-ehci";
f40cf244c3feb4e Andre Przywara 2022-10-31  837  			reg = <0x05200000 0x100>;
f40cf244c3feb4e Andre Przywara 2022-10-31  838  			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
f40cf244c3feb4e Andre Przywara 2022-10-31  839  			clocks = <&ccu CLK_BUS_OHCI1>,
f40cf244c3feb4e Andre Przywara 2022-10-31  840  				 <&ccu CLK_BUS_EHCI1>,
f40cf244c3feb4e Andre Przywara 2022-10-31  841  				 <&ccu CLK_USB_OHCI1>;
f40cf244c3feb4e Andre Przywara 2022-10-31  842  			resets = <&ccu RST_BUS_OHCI1>,
f40cf244c3feb4e Andre Przywara 2022-10-31  843  				 <&ccu RST_BUS_EHCI1>;
f40cf244c3feb4e Andre Przywara 2022-10-31  844  			phys = <&usbphy 1>;
f40cf244c3feb4e Andre Przywara 2022-10-31  845  			phy-names = "usb";
f40cf244c3feb4e Andre Przywara 2022-10-31  846  			status = "disabled";
f40cf244c3feb4e Andre Przywara 2022-10-31  847  		};
f40cf244c3feb4e Andre Przywara 2022-10-31  848  
f40cf244c3feb4e Andre Przywara 2022-10-31  849  		ohci1: usb@5200400 {
f40cf244c3feb4e Andre Przywara 2022-10-31  850  			compatible = "allwinner,sun50i-h616-ohci",
f40cf244c3feb4e Andre Przywara 2022-10-31  851  				     "generic-ohci";
f40cf244c3feb4e Andre Przywara 2022-10-31  852  			reg = <0x05200400 0x100>;
f40cf244c3feb4e Andre Przywara 2022-10-31  853  			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
f40cf244c3feb4e Andre Przywara 2022-10-31  854  			clocks = <&ccu CLK_BUS_OHCI1>,
f40cf244c3feb4e Andre Przywara 2022-10-31  855  				 <&ccu CLK_USB_OHCI1>;
f40cf244c3feb4e Andre Przywara 2022-10-31  856  			resets = <&ccu RST_BUS_OHCI1>;
f40cf244c3feb4e Andre Przywara 2022-10-31  857  			phys = <&usbphy 1>;
f40cf244c3feb4e Andre Przywara 2022-10-31  858  			phy-names = "usb";
f40cf244c3feb4e Andre Przywara 2022-10-31  859  			status = "disabled";
f40cf244c3feb4e Andre Przywara 2022-10-31  860  		};
f40cf244c3feb4e Andre Przywara 2022-10-31  861  
f40cf244c3feb4e Andre Przywara 2022-10-31  862  		ehci2: usb@5310000 {
f40cf244c3feb4e Andre Przywara 2022-10-31  863  			compatible = "allwinner,sun50i-h616-ehci",
f40cf244c3feb4e Andre Przywara 2022-10-31  864  				     "generic-ehci";
f40cf244c3feb4e Andre Przywara 2022-10-31  865  			reg = <0x05310000 0x100>;
f40cf244c3feb4e Andre Przywara 2022-10-31  866  			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
f40cf244c3feb4e Andre Przywara 2022-10-31  867  			clocks = <&ccu CLK_BUS_OHCI2>,
f40cf244c3feb4e Andre Przywara 2022-10-31  868  				 <&ccu CLK_BUS_EHCI2>,
f40cf244c3feb4e Andre Przywara 2022-10-31  869  				 <&ccu CLK_USB_OHCI2>;
f40cf244c3feb4e Andre Przywara 2022-10-31  870  			resets = <&ccu RST_BUS_OHCI2>,
f40cf244c3feb4e Andre Przywara 2022-10-31  871  				 <&ccu RST_BUS_EHCI2>;
f40cf244c3feb4e Andre Przywara 2022-10-31  872  			phys = <&usbphy 2>;
f40cf244c3feb4e Andre Przywara 2022-10-31  873  			phy-names = "usb";
f40cf244c3feb4e Andre Przywara 2022-10-31  874  			status = "disabled";
f40cf244c3feb4e Andre Przywara 2022-10-31  875  		};
f40cf244c3feb4e Andre Przywara 2022-10-31  876  
f40cf244c3feb4e Andre Przywara 2022-10-31  877  		ohci2: usb@5310400 {
f40cf244c3feb4e Andre Przywara 2022-10-31  878  			compatible = "allwinner,sun50i-h616-ohci",
f40cf244c3feb4e Andre Przywara 2022-10-31  879  				     "generic-ohci";
f40cf244c3feb4e Andre Przywara 2022-10-31  880  			reg = <0x05310400 0x100>;
f40cf244c3feb4e Andre Przywara 2022-10-31  881  			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
f40cf244c3feb4e Andre Przywara 2022-10-31  882  			clocks = <&ccu CLK_BUS_OHCI2>,
f40cf244c3feb4e Andre Przywara 2022-10-31  883  				 <&ccu CLK_USB_OHCI2>;
f40cf244c3feb4e Andre Przywara 2022-10-31  884  			resets = <&ccu RST_BUS_OHCI2>;
f40cf244c3feb4e Andre Przywara 2022-10-31  885  			phys = <&usbphy 2>;
f40cf244c3feb4e Andre Przywara 2022-10-31  886  			phy-names = "usb";
f40cf244c3feb4e Andre Przywara 2022-10-31  887  			status = "disabled";
f40cf244c3feb4e Andre Przywara 2022-10-31  888  		};
f40cf244c3feb4e Andre Przywara 2022-10-31  889  
f40cf244c3feb4e Andre Przywara 2022-10-31  890  		ehci3: usb@5311000 {
f40cf244c3feb4e Andre Przywara 2022-10-31  891  			compatible = "allwinner,sun50i-h616-ehci",
f40cf244c3feb4e Andre Przywara 2022-10-31  892  				     "generic-ehci";
f40cf244c3feb4e Andre Przywara 2022-10-31  893  			reg = <0x05311000 0x100>;
f40cf244c3feb4e Andre Przywara 2022-10-31  894  			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
f40cf244c3feb4e Andre Przywara 2022-10-31  895  			clocks = <&ccu CLK_BUS_OHCI3>,
f40cf244c3feb4e Andre Przywara 2022-10-31  896  				 <&ccu CLK_BUS_EHCI3>,
f40cf244c3feb4e Andre Przywara 2022-10-31  897  				 <&ccu CLK_USB_OHCI3>;
f40cf244c3feb4e Andre Przywara 2022-10-31  898  			resets = <&ccu RST_BUS_OHCI3>,
f40cf244c3feb4e Andre Przywara 2022-10-31  899  				 <&ccu RST_BUS_EHCI3>;
f40cf244c3feb4e Andre Przywara 2022-10-31  900  			phys = <&usbphy 3>;
f40cf244c3feb4e Andre Przywara 2022-10-31  901  			phy-names = "usb";
f40cf244c3feb4e Andre Przywara 2022-10-31  902  			status = "disabled";
f40cf244c3feb4e Andre Przywara 2022-10-31  903  		};
f40cf244c3feb4e Andre Przywara 2022-10-31  904  
f40cf244c3feb4e Andre Przywara 2022-10-31  905  		ohci3: usb@5311400 {
f40cf244c3feb4e Andre Przywara 2022-10-31  906  			compatible = "allwinner,sun50i-h616-ohci",
f40cf244c3feb4e Andre Przywara 2022-10-31  907  				     "generic-ohci";
f40cf244c3feb4e Andre Przywara 2022-10-31  908  			reg = <0x05311400 0x100>;
f40cf244c3feb4e Andre Przywara 2022-10-31  909  			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
f40cf244c3feb4e Andre Przywara 2022-10-31  910  			clocks = <&ccu CLK_BUS_OHCI3>,
f40cf244c3feb4e Andre Przywara 2022-10-31  911  				 <&ccu CLK_USB_OHCI3>;
f40cf244c3feb4e Andre Przywara 2022-10-31  912  			resets = <&ccu RST_BUS_OHCI3>;
f40cf244c3feb4e Andre Przywara 2022-10-31  913  			phys = <&usbphy 3>;
f40cf244c3feb4e Andre Przywara 2022-10-31  914  			phy-names = "usb";
f40cf244c3feb4e Andre Przywara 2022-10-31  915  			status = "disabled";
f40cf244c3feb4e Andre Przywara 2022-10-31  916  		};
f40cf244c3feb4e Andre Przywara 2022-10-31  917  
cddf223e627003e Chris Morgan   2025-05-07  918  		tcon_top: tcon-top@6510000 {
cddf223e627003e Chris Morgan   2025-05-07  919  			compatible = "allwinner,sun50i-h616-tcon-top",
cddf223e627003e Chris Morgan   2025-05-07  920  				     "allwinner,sun50i-h6-tcon-top";
cddf223e627003e Chris Morgan   2025-05-07  921  			reg = <0x06510000 0x1000>;
cddf223e627003e Chris Morgan   2025-05-07  922  			clocks = <&ccu CLK_BUS_TCON_TOP>,
cddf223e627003e Chris Morgan   2025-05-07  923  				 <&ccu CLK_TCON_TV0>;
cddf223e627003e Chris Morgan   2025-05-07  924  			clock-names = "bus", "tcon-tv0";
cddf223e627003e Chris Morgan   2025-05-07  925  			clock-output-names = "tcon-top-tv0";
cddf223e627003e Chris Morgan   2025-05-07  926  			#clock-cells = <1>;
cddf223e627003e Chris Morgan   2025-05-07  927  			resets = <&ccu RST_BUS_TCON_TOP>;
cddf223e627003e Chris Morgan   2025-05-07  928  
cddf223e627003e Chris Morgan   2025-05-07  929  			ports {
cddf223e627003e Chris Morgan   2025-05-07  930  				#address-cells = <1>;
cddf223e627003e Chris Morgan   2025-05-07  931  				#size-cells = <0>;
cddf223e627003e Chris Morgan   2025-05-07  932  
cddf223e627003e Chris Morgan   2025-05-07 @933  				tcon_top_mixer0_in: port@0 {
cddf223e627003e Chris Morgan   2025-05-07  934  					#address-cells = <1>;
cddf223e627003e Chris Morgan   2025-05-07  935  					#size-cells = <0>;
cddf223e627003e Chris Morgan   2025-05-07  936  					reg = <0>;
cddf223e627003e Chris Morgan   2025-05-07  937  
cddf223e627003e Chris Morgan   2025-05-07  938  					tcon_top_mixer0_in_mixer0: endpoint@0 {
cddf223e627003e Chris Morgan   2025-05-07  939  						reg = <0>;
cddf223e627003e Chris Morgan   2025-05-07  940  						remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
cddf223e627003e Chris Morgan   2025-05-07  941  					};
cddf223e627003e Chris Morgan   2025-05-07  942  				};
cddf223e627003e Chris Morgan   2025-05-07  943  
cddf223e627003e Chris Morgan   2025-05-07  944  				tcon_top_mixer0_out: port@1 {
cddf223e627003e Chris Morgan   2025-05-07  945  					#address-cells = <1>;
cddf223e627003e Chris Morgan   2025-05-07  946  					#size-cells = <0>;
cddf223e627003e Chris Morgan   2025-05-07  947  					reg = <1>;
cddf223e627003e Chris Morgan   2025-05-07  948  
cddf223e627003e Chris Morgan   2025-05-07  949  					tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
cddf223e627003e Chris Morgan   2025-05-07  950  						reg = <0>;
cddf223e627003e Chris Morgan   2025-05-07  951  						remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
cddf223e627003e Chris Morgan   2025-05-07  952  					};
cddf223e627003e Chris Morgan   2025-05-07  953  
cddf223e627003e Chris Morgan   2025-05-07  954  					tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
cddf223e627003e Chris Morgan   2025-05-07  955  						reg = <2>;
cddf223e627003e Chris Morgan   2025-05-07  956  						remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
cddf223e627003e Chris Morgan   2025-05-07  957  					};
cddf223e627003e Chris Morgan   2025-05-07  958  				};
cddf223e627003e Chris Morgan   2025-05-07  959  
cddf223e627003e Chris Morgan   2025-05-07  960  				tcon_top_hdmi_in: port@4 {
cddf223e627003e Chris Morgan   2025-05-07  961  					#address-cells = <1>;
cddf223e627003e Chris Morgan   2025-05-07  962  					#size-cells = <0>;
cddf223e627003e Chris Morgan   2025-05-07  963  					reg = <4>;
cddf223e627003e Chris Morgan   2025-05-07  964  
cddf223e627003e Chris Morgan   2025-05-07  965  					tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
cddf223e627003e Chris Morgan   2025-05-07  966  						reg = <0>;
cddf223e627003e Chris Morgan   2025-05-07  967  						remote-endpoint = <&tcon_tv0_out_tcon_top>;
cddf223e627003e Chris Morgan   2025-05-07  968  					};
cddf223e627003e Chris Morgan   2025-05-07  969  				};
cddf223e627003e Chris Morgan   2025-05-07  970  
cddf223e627003e Chris Morgan   2025-05-07  971  				tcon_top_hdmi_out: port@5 {
cddf223e627003e Chris Morgan   2025-05-07  972  					reg = <5>;
cddf223e627003e Chris Morgan   2025-05-07  973  
cddf223e627003e Chris Morgan   2025-05-07  974  					tcon_top_hdmi_out_hdmi: endpoint {
cddf223e627003e Chris Morgan   2025-05-07  975  						/* placeholder for HDMI  - remote-endpoint = <&hdmi_in_tcon_top>;*/
cddf223e627003e Chris Morgan   2025-05-07  976  					};
cddf223e627003e Chris Morgan   2025-05-07  977  				};
cddf223e627003e Chris Morgan   2025-05-07  978  			};
cddf223e627003e Chris Morgan   2025-05-07  979  		};
cddf223e627003e Chris Morgan   2025-05-07  980  
cddf223e627003e Chris Morgan   2025-05-07  981  		tcon_lcd0: lcd-controller@6511000 {
cddf223e627003e Chris Morgan   2025-05-07  982  			compatible = "allwinner,sun50i-h616-tcon-lcd",
cddf223e627003e Chris Morgan   2025-05-07  983  				     "allwinner,sun8i-r40-tcon-lcd";
cddf223e627003e Chris Morgan   2025-05-07  984  			reg = <0x06511000 0x1000>;
cddf223e627003e Chris Morgan   2025-05-07  985  			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
cddf223e627003e Chris Morgan   2025-05-07  986  			clocks = <&ccu CLK_BUS_TCON_LCD0>, <&ccu CLK_TCON_LCD0>;
cddf223e627003e Chris Morgan   2025-05-07  987  			clock-names = "ahb", "tcon-ch0";
cddf223e627003e Chris Morgan   2025-05-07  988  			clock-output-names = "tcon-data-clock";
cddf223e627003e Chris Morgan   2025-05-07  989  			#clock-cells = <0>;
cddf223e627003e Chris Morgan   2025-05-07  990  			resets = <&ccu RST_BUS_TCON_LCD0>, <&ccu RST_BUS_LVDS>;
cddf223e627003e Chris Morgan   2025-05-07  991  			reset-names = "lcd", "lvds";
cddf223e627003e Chris Morgan   2025-05-07  992  			status = "disabled";
cddf223e627003e Chris Morgan   2025-05-07  993  
cddf223e627003e Chris Morgan   2025-05-07  994  			ports {
cddf223e627003e Chris Morgan   2025-05-07  995  				#address-cells = <1>;
cddf223e627003e Chris Morgan   2025-05-07  996  				#size-cells = <0>;
cddf223e627003e Chris Morgan   2025-05-07  997  
cddf223e627003e Chris Morgan   2025-05-07 @998  				tcon_lcd0_in: port@0 {

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH V9 00/24] drm: sun4i: add Display Engine 3.3 (DE33) support

[Corentin Labbe]

Le Wed, May 07, 2025 at 04:13:38PM -0500, Rob Herring a écrit :
> On Wed, May 7, 2025 at 3:22 PM Chris Morgan <macroalpha82@gmail.com> wrote:
> >
> > From: Chris Morgan <macromorgan@hotmail.com>
> >
> > I've spoken with Ryan and he agreed to let me take over this series to
> > get the display engine working on the Allwinner H616. I've taken his
> > previous patch series for Display Engine 3.3 and combined it with the
> > LCD controller patch series. I've also fixed a few additional bugs and
> > made some changes to the device tree bindings.
> >
> > Changes since V8:
> >  - Combined the DE33 [1] series and the LCD [2] series to better track
> >    all patches necessary to output to an LCD display for the Allwinner
> >    H700.
> >  - Added a required LVDS reset as requested here [3].
> >  - Added compatible strings with a fallback for
> >    allwinner,sun50i-h616-display-engine, allwinner,sun50i-h616-tcon-top,
> >    and allwinner,sun50i-h616-sram-c.
> >  - Added binding documentation for the LCD controller.
> >  - Renamed the de3_sram device tree node to de33_sram.
> >  - Corrected the LVDS reset for the LCD controller binding.
> >  - Removed the PWM pins from the pincontroller bindings, as PWM is not
> >    yet supported.
> >  - Reordered the patches so that a binding or a device tree node is not
> >    referenced before it is defined.
> >
> > [1] https://lore.kernel.org/linux-sunxi/20250310092345.31708-1-ryan@testtoast.com/
> > [2] https://lore.kernel.org/linux-sunxi/20250216092827.15444-1-ryan@testtoast.com/
> > [3] https://lore.kernel.org/linux-sunxi/38669808.XM6RcZxFsP@jernej-laptop/
> >
> > Chris Morgan (24):
> >   dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset
> >   clk: sunxi-ng: h616: Add LVDS reset for LCD TCON
> >   drm: sun4i: de2/de3: add mixer version enum
> >   drm: sun4i: de2/de3: refactor mixer initialisation
> >   drm: sun4i: de2/de3: add generic blender register reference function
> >   drm: sun4i: de2/de3: use generic register reference function for layer
> >     configuration
> >   dt-bindings: allwinner: add H616 DE33 bus binding
> >   dt-bindings: allwinner: add H616 DE33 clock binding
> >   dt-bindings: allwinner: add H616 DE33 mixer binding
> >   clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support
> >   drm: sun4i: de33: vi_scaler: add Display Engine 3.3 (DE33) support
> >   drm: sun4i: de33: mixer: add Display Engine 3.3 (DE33) support
> >   drm: sun4i: de33: mixer: add mixer configuration for the H616
> >   dt-bindings: allwinner: Add TCON_TOP and TCON_LCD clock/reset defines
> >   dt-bindings: display: sun4i: Add compatible strings for H616 DE
> >   dt-bindings: display: sun4i: Add compatible strings for H616 TCON TOP
> >   dt-bindings: sram: sunxi-sram: Add H616 SRAM C compatible
> >   dt-bindings: display: Add R40 and H616 display engine compatibles
> >   drm/sun4i: tcon: Add support for R40 LCD
> >   arm64: dts: allwinner: h616: add display engine, bus and mixer nodes
> >   arm64: dts: allwinner: h616: Add TCON nodes to H616 DTSI
> >   arm64: dts: allwinner: h616: add LCD and LVDS pins
> >   arm64: dts: allwinner: rg35xx: Add GPIO backlight control
> >   arm64: dts: allwinner: rg35xx: Enable LCD output
> 
> What's the base for this series? It didn't apply for me (using b4).
> 
> Rob
> 

I tested it on top of linux-next next-20250508 and revert "arm64: dts: allwinner: h616: Add Mali GPU node"

Re: [PATCH V9 00/24] drm: sun4i: add Display Engine 3.3 (DE33) support

[Chris Morgan]

On Thu, May 08, 2025 at 09:26:24AM +0200, Krzysztof Kozlowski wrote:
> On Wed, May 07, 2025 at 03:19:19PM GMT, Chris Morgan wrote:
> > From: Chris Morgan <macromorgan@hotmail.com>
> > 
> > I've spoken with Ryan and he agreed to let me take over this series to
> > get the display engine working on the Allwinner H616. I've taken his
> > previous patch series for Display Engine 3.3 and combined it with the
> > LCD controller patch series. I've also fixed a few additional bugs and
> > made some changes to the device tree bindings.
> > 
> > Changes since V8:
> >  - Combined the DE33 [1] series and the LCD [2] series to better track
> >    all patches necessary to output to an LCD display for the Allwinner
> >    H700.
> 
> You have here three or four different subsystems. This does not make it
> easier, but it makes it a huge patchbomb with unspecific or complex
> base.
> 
> Such combination makes no sense, because anyway it will have to be split
> per subsystem. You just know made it difficult for maintainers to review
> and apply, because they cannot apply entire set.
> 
> Best regards,
> Krzysztof
> 

I apologize, please ignore this series then. I'll break it up more
among subsystem lines and note that they are all related in the notes.

Thank you.

Re: [PATCH V9 01/24] dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset

[Andre Przywara]

On Wed,  7 May 2025 15:19:20 -0500
Chris Morgan <macroalpha82@gmail.com> wrote:

> From: Chris Morgan <macromorgan@hotmail.com>
> 
> Add the required LVDS reset binding for the LCD TCON.
> 
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Ryan Walklin <ryan@testtoast.com>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
>  include/dt-bindings/reset/sun50i-h616-ccu.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h
> index 81b1eba2a7f7..ba626f7015b5 100644
> --- a/include/dt-bindings/reset/sun50i-h616-ccu.h
> +++ b/include/dt-bindings/reset/sun50i-h616-ccu.h
> @@ -69,5 +69,6 @@
>  #define RST_BUS_GPADC		60
>  #define RST_BUS_TCON_LCD0	61
>  #define RST_BUS_TCON_LCD1	62
> +#define RST_BUS_LVDS		63
>  
>  #endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */

Re: [PATCH V9 02/24] clk: sunxi-ng: h616: Add LVDS reset for LCD TCON

[Andre Przywara]

On Wed,  7 May 2025 15:19:21 -0500
Chris Morgan <macroalpha82@gmail.com> wrote:

Hi,

despite the slightly ill fate of this series, I was wondering if we could
get the non-controversial clock parts for instance already merged, to
reduce the number of patches and mitigate the churn with dependencies?

> From: Chris Morgan <macromorgan@hotmail.com>
> 
> Add the required LVDS reset for the LCD TCON. Note that while this
> reset is exposed for the T507, H616, and H700 only the H700 has
> an LCD controller.
> 
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Ryan Walklin <ryan@testtoast.com>

Matches the T507 manual:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
>  drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> index daa462c7d477..955c614830fa 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> @@ -1094,6 +1094,7 @@ static const struct ccu_reset_map sun50i_h616_ccu_resets[] = {
>  	[RST_BUS_TCON_LCD1]	= { 0xb7c, BIT(17) },
>  	[RST_BUS_TCON_TV0]	= { 0xb9c, BIT(16) },
>  	[RST_BUS_TCON_TV1]	= { 0xb9c, BIT(17) },
> +	[RST_BUS_LVDS]		= { 0xbac, BIT(16) },
>  	[RST_BUS_TVE_TOP]	= { 0xbbc, BIT(16) },
>  	[RST_BUS_TVE0]		= { 0xbbc, BIT(17) },
>  	[RST_BUS_HDCP]		= { 0xc4c, BIT(16) },

Re: [PATCH V9 02/24] clk: sunxi-ng: h616: Add LVDS reset for LCD TCON

[Chen-Yu Tsai]

On Fri, May 9, 2025 at 11:14 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> On Wed,  7 May 2025 15:19:21 -0500
> Chris Morgan <macroalpha82@gmail.com> wrote:
>
> Hi,
>
> despite the slightly ill fate of this series, I was wondering if we could
> get the non-controversial clock parts for instance already merged, to
> reduce the number of patches and mitigate the churn with dependencies?

Sure. Are we expecting any of the DT bits to go in this cycle?
If not I won't have to split the DT header patch on a separate
branch.

ChenYu

> > From: Chris Morgan <macromorgan@hotmail.com>
> >
> > Add the required LVDS reset for the LCD TCON. Note that while this
> > reset is exposed for the T507, H616, and H700 only the H700 has
> > an LCD controller.
> >
> > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> > Signed-off-by: Ryan Walklin <ryan@testtoast.com>
>
> Matches the T507 manual:
>
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
>
> Cheers,
> Andre
>
> > ---
> >  drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> > index daa462c7d477..955c614830fa 100644
> > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> > @@ -1094,6 +1094,7 @@ static const struct ccu_reset_map sun50i_h616_ccu_resets[] = {
> >       [RST_BUS_TCON_LCD1]     = { 0xb7c, BIT(17) },
> >       [RST_BUS_TCON_TV0]      = { 0xb9c, BIT(16) },
> >       [RST_BUS_TCON_TV1]      = { 0xb9c, BIT(17) },
> > +     [RST_BUS_LVDS]          = { 0xbac, BIT(16) },
> >       [RST_BUS_TVE_TOP]       = { 0xbbc, BIT(16) },
> >       [RST_BUS_TVE0]          = { 0xbbc, BIT(17) },
> >       [RST_BUS_HDCP]          = { 0xc4c, BIT(16) },
>
>

Re: [PATCH V9 23/24] arm64: dts: allwinner: rg35xx: Add GPIO backlight control

[Andre Przywara]

On Wed,  7 May 2025 15:19:42 -0500
Chris Morgan <macroalpha82@gmail.com> wrote:

Hi Chris,

> From: Chris Morgan <macromorgan@hotmail.com>
> 
> The LCD backlight for this device can be exposed as a simple GPIO-
> controlled device. It would be more accurately modelled using PWM to
> enable brightness control, however the PWM driver design for the H616 is
> not yet upstreamed.

I don't think this is right then: First there should be no notion of a
"driver being upstreamed" in a *DT* patch, as "the driver" is a Linux
speciality, which the DT itself doesn't care about.
And secondly we should not chicken out and go with an interim solution.

So I guess we need to wait for the PWM binding to appear.

Cheers,
Andre

> Add a GPIO backlight node to the DTS.
> 
> Signed-off-by: Ryan Walklin <ryan@testtoast.com>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> ---
>  .../boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
> index 7e17ca07892d..95f2ae04bd95 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
> @@ -21,6 +21,12 @@ aliases {
>  		serial0 = &uart0;
>  	};
>  
> +	backlight: backlight {
> +		compatible = "gpio-backlight";
> +		gpios = <&pio 3 28 GPIO_ACTIVE_HIGH>; // PD28
> +		default-on;
> +	};
> +
>  	battery: battery {
>  		compatible = "simple-battery";
>  		constant-charge-current-max-microamp = <1024000>;

Re: [PATCH V9 02/24] clk: sunxi-ng: h616: Add LVDS reset for LCD TCON

[Andre Przywara]

On Fri, 9 May 2025 23:29:50 +0900
Chen-Yu Tsai <wens@csie.org> wrote:

> On Fri, May 9, 2025 at 11:14 PM Andre Przywara <andre.przywara@arm.com> wrote:
> >
> > On Wed,  7 May 2025 15:19:21 -0500
> > Chris Morgan <macroalpha82@gmail.com> wrote:
> >
> > Hi,
> >
> > despite the slightly ill fate of this series, I was wondering if we could
> > get the non-controversial clock parts for instance already merged, to
> > reduce the number of patches and mitigate the churn with dependencies?  
> 
> Sure. Are we expecting any of the DT bits to go in this cycle?
> If not I won't have to split the DT header patch on a separate
> branch.

I don't think so, the DT wouldn't make much sense on its own anyway. But
I guess it would help if the bindings / binding headers would go in
already?

Cheers,
Andre

> 
> > > From: Chris Morgan <macromorgan@hotmail.com>
> > >
> > > Add the required LVDS reset for the LCD TCON. Note that while this
> > > reset is exposed for the T507, H616, and H700 only the H700 has
> > > an LCD controller.
> > >
> > > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> > > Signed-off-by: Ryan Walklin <ryan@testtoast.com>  
> >
> > Matches the T507 manual:
> >
> > Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> >
> > Cheers,
> > Andre
> >  
> > > ---
> > >  drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> > > index daa462c7d477..955c614830fa 100644
> > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> > > @@ -1094,6 +1094,7 @@ static const struct ccu_reset_map sun50i_h616_ccu_resets[] = {
> > >       [RST_BUS_TCON_LCD1]     = { 0xb7c, BIT(17) },
> > >       [RST_BUS_TCON_TV0]      = { 0xb9c, BIT(16) },
> > >       [RST_BUS_TCON_TV1]      = { 0xb9c, BIT(17) },
> > > +     [RST_BUS_LVDS]          = { 0xbac, BIT(16) },
> > >       [RST_BUS_TVE_TOP]       = { 0xbbc, BIT(16) },
> > >       [RST_BUS_TVE0]          = { 0xbbc, BIT(17) },
> > >       [RST_BUS_HDCP]          = { 0xc4c, BIT(16) },  
> >
> >  
> 

Re: [PATCH V9 23/24] arm64: dts: allwinner: rg35xx: Add GPIO backlight control

[Chris Morgan]

On Fri, May 09, 2025 at 03:32:04PM +0100, Andre Przywara wrote:
> On Wed,  7 May 2025 15:19:42 -0500
> Chris Morgan <macroalpha82@gmail.com> wrote:
> 
> Hi Chris,
> 
> > From: Chris Morgan <macromorgan@hotmail.com>
> > 
> > The LCD backlight for this device can be exposed as a simple GPIO-
> > controlled device. It would be more accurately modelled using PWM to
> > enable brightness control, however the PWM driver design for the H616 is
> > not yet upstreamed.
> 
> I don't think this is right then: First there should be no notion of a
> "driver being upstreamed" in a *DT* patch, as "the driver" is a Linux
> speciality, which the DT itself doesn't care about.
> And secondly we should not chicken out and go with an interim solution.
> 
> So I guess we need to wait for the PWM binding to appear.
> 
> Cheers,
> Andre

Okay, so then I can drop the backlight (and might as well drop the
LCD bindings as well) until the PWM is upstreamed. I just figured
"something" for now is okay, but we can wait.

This is the specific series I'm tracking [1]... adding support for the
H616 would just require a little bit of boilerplate code and a new
compatible string once that gets upstreamed.

[1] https://lore.kernel.org/linux-sunxi/20250427142500.151925-3-privatesub2@gmail.com/

Thank you,
Chris

> 
> > Add a GPIO backlight node to the DTS.
> > 
> > Signed-off-by: Ryan Walklin <ryan@testtoast.com>
> > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> > ---
> >  .../boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts | 6 ++++++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
> > index 7e17ca07892d..95f2ae04bd95 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
> > @@ -21,6 +21,12 @@ aliases {
> >  		serial0 = &uart0;
> >  	};
> >  
> > +	backlight: backlight {
> > +		compatible = "gpio-backlight";
> > +		gpios = <&pio 3 28 GPIO_ACTIVE_HIGH>; // PD28
> > +		default-on;
> > +	};
> > +
> >  	battery: battery {
> >  		compatible = "simple-battery";
> >  		constant-charge-current-max-microamp = <1024000>;
> 

Re: [PATCH V9 02/24] clk: sunxi-ng: h616: Add LVDS reset for LCD TCON

[Chris Morgan]

On Fri, May 09, 2025 at 05:31:40PM +0100, Andre Przywara wrote:
> On Fri, 9 May 2025 23:29:50 +0900
> Chen-Yu Tsai <wens@csie.org> wrote:
> 
> > On Fri, May 9, 2025 at 11:14 PM Andre Przywara <andre.przywara@arm.com> wrote:
> > >
> > > On Wed,  7 May 2025 15:19:21 -0500
> > > Chris Morgan <macroalpha82@gmail.com> wrote:
> > >
> > > Hi,
> > >
> > > despite the slightly ill fate of this series, I was wondering if we could
> > > get the non-controversial clock parts for instance already merged, to
> > > reduce the number of patches and mitigate the churn with dependencies?  
> > 
> > Sure. Are we expecting any of the DT bits to go in this cycle?
> > If not I won't have to split the DT header patch on a separate
> > branch.
> 
> I don't think so, the DT wouldn't make much sense on its own anyway. But
> I guess it would help if the bindings / binding headers would go in
> already?
> 
> Cheers,
> Andre

I erred in combining everything into a large patch series, so I'm going
to resubmit with things broken out by subsystem/in-order. Do you just
want me to resubmit these two patches by themselves or can you take
them now since they're the first 2? I won't need them until I add the
LCD bindings into the sun50i-h616.dtsi file which will be towards the
end of the commit chain.

Thank you,
Chris.

> 
> > 
> > > > From: Chris Morgan <macromorgan@hotmail.com>
> > > >
> > > > Add the required LVDS reset for the LCD TCON. Note that while this
> > > > reset is exposed for the T507, H616, and H700 only the H700 has
> > > > an LCD controller.
> > > >
> > > > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> > > > Signed-off-by: Ryan Walklin <ryan@testtoast.com>  
> > >
> > > Matches the T507 manual:
> > >
> > > Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> > >
> > > Cheers,
> > > Andre
> > >  
> > > > ---
> > > >  drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 1 +
> > > >  1 file changed, 1 insertion(+)
> > > >
> > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> > > > index daa462c7d477..955c614830fa 100644
> > > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> > > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> > > > @@ -1094,6 +1094,7 @@ static const struct ccu_reset_map sun50i_h616_ccu_resets[] = {
> > > >       [RST_BUS_TCON_LCD1]     = { 0xb7c, BIT(17) },
> > > >       [RST_BUS_TCON_TV0]      = { 0xb9c, BIT(16) },
> > > >       [RST_BUS_TCON_TV1]      = { 0xb9c, BIT(17) },
> > > > +     [RST_BUS_LVDS]          = { 0xbac, BIT(16) },
> > > >       [RST_BUS_TVE_TOP]       = { 0xbbc, BIT(16) },
> > > >       [RST_BUS_TVE0]          = { 0xbbc, BIT(17) },
> > > >       [RST_BUS_HDCP]          = { 0xc4c, BIT(16) },  
> > >
> > >  
> > 
> 

Re: (subset) [PATCH V9 00/24] drm: sun4i: add Display Engine 3.3 (DE33) support

[Chen-Yu Tsai]

On Wed, 07 May 2025 15:19:19 -0500, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
> 
> I've spoken with Ryan and he agreed to let me take over this series to
> get the display engine working on the Allwinner H616. I've taken his
> previous patch series for Display Engine 3.3 and combined it with the
> LCD controller patch series. I've also fixed a few additional bugs and
> made some changes to the device tree bindings.
> 
> [...]

Applied to sunxi/clk-for-6.16 in local tree, thanks!

[01/24] dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset
        commit: 20fb4ac9cda06527cf60c5ec7dda7c463c9c81be
[02/24] clk: sunxi-ng: h616: Add LVDS reset for LCD TCON
        commit: 390e4cfe87cb99c80614235cbc4651c3b315a9c9

Best regards,
-- 
Chen-Yu Tsai <wens@csie.org>