From: kernel test robot <lkp@intel.com>
To: oe-kbuild@lists.linux.dev
Cc: lkp@intel.com
Subject: Re: [PATCH 6/8] dts: arm64: amlogic: add S7 pinctrl node
Date: Thu, 15 May 2025 06:01:59 +0800 [thread overview]
Message-ID: <202505150552.R7XPfaCE-lkp@intel.com> (raw)
::::::
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
::::::
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20250514-s6-s7-pinctrl-v1-6-39d368cad250@amlogic.com>
References: <20250514-s6-s7-pinctrl-v1-6-39d368cad250@amlogic.com>
TO: Xianwei Zhao via B4 Relay <devnull+xianwei.zhao.amlogic.com@kernel.org>
TO: Linus Walleij <linus.walleij@linaro.org>
TO: Rob Herring <robh@kernel.org>
TO: Krzysztof Kozlowski <krzk@kernel.org>
TO: Conor Dooley <conor+dt@kernel.org>
TO: Neil Armstrong <neil.armstrong@linaro.org>
TO: Kevin Hilman <khilman@baylibre.com>
TO: Jerome Brunet <jbrunet@baylibre.com>
TO: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
CC: linux-amlogic@lists.infradead.org
CC: linux-gpio@vger.kernel.org
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: Xianwei Zhao <xianwei.zhao@amlogic.com>
Hi Xianwei,
kernel test robot noticed the following build warnings:
[auto build test WARNING on aa94665adc28f3fdc3de2979ac1e98bae961d6ca]
url: https://github.com/intel-lab-lkp/linux/commits/Xianwei-Zhao-via-B4-Relay/dt-bindings-pinctl-amlogic-pinctrl-a4-Add-compatible-string-for-S7/20250514-150438
base: aa94665adc28f3fdc3de2979ac1e98bae961d6ca
patch link: https://lore.kernel.org/r/20250514-s6-s7-pinctrl-v1-6-39d368cad250%40amlogic.com
patch subject: [PATCH 6/8] dts: arm64: amlogic: add S7 pinctrl node
:::::: branch date: 15 hours ago
:::::: commit date: 15 hours ago
config: arm64-randconfig-002-20250514 (https://download.01.org/0day-ci/archive/20250515/202505150552.R7XPfaCE-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 8.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250515/202505150552.R7XPfaCE-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202505150552.R7XPfaCE-lkp@intel.com/
dtcheck warnings: (new ones prefixed by >>)
>> arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi:99.29-177.6: Warning (unit_address_vs_reg): /soc/bus@fe000000/pinctrl: node has a reg or ranges property, but no unit name
>> arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi:99.29-177.6: Warning (simple_bus_reg): /soc/bus@fe000000/pinctrl: simple-bus unit address format error, expected "4000"
vim +99 arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
1b753fcfcff8ad Xianwei Zhao 2025-03-17 10
1b753fcfcff8ad Xianwei Zhao 2025-03-17 11 / {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 12 cpus {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 13 #address-cells = <2>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 14 #size-cells = <0>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 15
1b753fcfcff8ad Xianwei Zhao 2025-03-17 16 cpu0: cpu@0 {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 17 device_type = "cpu";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 18 compatible = "arm,cortex-a55";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 19 reg = <0x0 0x0>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 20 enable-method = "psci";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 21 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 22
1b753fcfcff8ad Xianwei Zhao 2025-03-17 23 cpu1: cpu@100 {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 24 device_type = "cpu";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 25 compatible = "arm,cortex-a55";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 26 reg = <0x0 0x100>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 27 enable-method = "psci";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 28 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 29
1b753fcfcff8ad Xianwei Zhao 2025-03-17 30 cpu2: cpu@200 {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 31 device_type = "cpu";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 32 compatible = "arm,cortex-a55";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 33 reg = <0x0 0x200>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 34 enable-method = "psci";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 35 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 36
1b753fcfcff8ad Xianwei Zhao 2025-03-17 37 cpu3: cpu@300 {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 38 device_type = "cpu";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 39 compatible = "arm,cortex-a55";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 40 reg = <0x0 0x300>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 41 enable-method = "psci";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 42 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 43
1b753fcfcff8ad Xianwei Zhao 2025-03-17 44 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 45
1b753fcfcff8ad Xianwei Zhao 2025-03-17 46 timer {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 47 compatible = "arm,armv8-timer";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1b753fcfcff8ad Xianwei Zhao 2025-03-17 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1b753fcfcff8ad Xianwei Zhao 2025-03-17 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1b753fcfcff8ad Xianwei Zhao 2025-03-17 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 52 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 53
1b753fcfcff8ad Xianwei Zhao 2025-03-17 54 psci {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 55 compatible = "arm,psci-1.0";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 56 method = "smc";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 57 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 58
1b753fcfcff8ad Xianwei Zhao 2025-03-17 59 xtal: xtal-clk {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 60 compatible = "fixed-clock";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 61 clock-frequency = <24000000>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 62 clock-output-names = "xtal";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 63 #clock-cells = <0>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 64 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 65
1b753fcfcff8ad Xianwei Zhao 2025-03-17 66 soc {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 67 compatible = "simple-bus";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 68 #address-cells = <2>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 69 #size-cells = <2>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 70 ranges;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 71
1b753fcfcff8ad Xianwei Zhao 2025-03-17 72 gic: interrupt-controller@fff01000 {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 73 compatible = "arm,gic-400";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 74 #interrupt-cells = <3>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 75 #address-cells = <0>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 76 interrupt-controller;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 77 reg = <0x0 0xfff01000 0 0x1000>,
1b753fcfcff8ad Xianwei Zhao 2025-03-17 78 <0x0 0xfff02000 0 0x0100>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 79 interrupts = <GIC_PPI 9 0xf04>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 80 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 81
1b753fcfcff8ad Xianwei Zhao 2025-03-17 82 apb: bus@fe000000 {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 83 compatible = "simple-bus";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 84 reg = <0x0 0xfe000000 0x0 0x480000>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 85 #address-cells = <2>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 86 #size-cells = <2>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 87 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 88
1b753fcfcff8ad Xianwei Zhao 2025-03-17 89 uart_b: serial@7a000 {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 90 compatible = "amlogic,s7-uart",
1b753fcfcff8ad Xianwei Zhao 2025-03-17 91 "amlogic,meson-s4-uart";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 92 reg = <0x0 0x7a000 0x0 0x18>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 93 interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 94 clocks = <&xtal>, <&xtal>, <&xtal>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 95 clock-names = "xtal", "pclk", "baud";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 96 status = "disabled";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 97 };
7eae48bf5844ec Xianwei Zhao 2025-05-14 98
7eae48bf5844ec Xianwei Zhao 2025-05-14 @99 periphs_pinctrl: pinctrl {
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
next reply other threads:[~2025-05-14 22:02 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-14 22:01 kernel test robot [this message]
-- strict thread matches above, loose matches on Subject: below --
2025-05-14 7:01 [PATCH 0/8] Add support for Amlogic S7/S7D/S6 pinctrl Xianwei Zhao
2025-05-14 7:01 ` [PATCH 6/8] dts: arm64: amlogic: add S7 pinctrl node Xianwei Zhao
2025-05-14 7:01 ` Xianwei Zhao via B4 Relay
2025-05-14 7:01 ` Xianwei Zhao via B4 Relay
2025-05-14 13:10 ` Rob Herring
2025-05-14 13:10 ` Rob Herring
2025-05-15 3:04 ` Xianwei Zhao
2025-05-15 3:04 ` Xianwei Zhao
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