* Re: [PATCH 6/8] dts: arm64: amlogic: add S7 pinctrl node
@ 2025-05-14 22:01 kernel test robot
0 siblings, 0 replies; 8+ messages in thread
From: kernel test robot @ 2025-05-14 22:01 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp
::::::
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
::::::
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20250514-s6-s7-pinctrl-v1-6-39d368cad250@amlogic.com>
References: <20250514-s6-s7-pinctrl-v1-6-39d368cad250@amlogic.com>
TO: Xianwei Zhao via B4 Relay <devnull+xianwei.zhao.amlogic.com@kernel.org>
TO: Linus Walleij <linus.walleij@linaro.org>
TO: Rob Herring <robh@kernel.org>
TO: Krzysztof Kozlowski <krzk@kernel.org>
TO: Conor Dooley <conor+dt@kernel.org>
TO: Neil Armstrong <neil.armstrong@linaro.org>
TO: Kevin Hilman <khilman@baylibre.com>
TO: Jerome Brunet <jbrunet@baylibre.com>
TO: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
CC: linux-amlogic@lists.infradead.org
CC: linux-gpio@vger.kernel.org
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: Xianwei Zhao <xianwei.zhao@amlogic.com>
Hi Xianwei,
kernel test robot noticed the following build warnings:
[auto build test WARNING on aa94665adc28f3fdc3de2979ac1e98bae961d6ca]
url: https://github.com/intel-lab-lkp/linux/commits/Xianwei-Zhao-via-B4-Relay/dt-bindings-pinctl-amlogic-pinctrl-a4-Add-compatible-string-for-S7/20250514-150438
base: aa94665adc28f3fdc3de2979ac1e98bae961d6ca
patch link: https://lore.kernel.org/r/20250514-s6-s7-pinctrl-v1-6-39d368cad250%40amlogic.com
patch subject: [PATCH 6/8] dts: arm64: amlogic: add S7 pinctrl node
:::::: branch date: 15 hours ago
:::::: commit date: 15 hours ago
config: arm64-randconfig-002-20250514 (https://download.01.org/0day-ci/archive/20250515/202505150552.R7XPfaCE-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 8.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250515/202505150552.R7XPfaCE-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202505150552.R7XPfaCE-lkp@intel.com/
dtcheck warnings: (new ones prefixed by >>)
>> arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi:99.29-177.6: Warning (unit_address_vs_reg): /soc/bus@fe000000/pinctrl: node has a reg or ranges property, but no unit name
>> arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi:99.29-177.6: Warning (simple_bus_reg): /soc/bus@fe000000/pinctrl: simple-bus unit address format error, expected "4000"
vim +99 arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
1b753fcfcff8ad Xianwei Zhao 2025-03-17 10
1b753fcfcff8ad Xianwei Zhao 2025-03-17 11 / {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 12 cpus {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 13 #address-cells = <2>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 14 #size-cells = <0>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 15
1b753fcfcff8ad Xianwei Zhao 2025-03-17 16 cpu0: cpu@0 {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 17 device_type = "cpu";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 18 compatible = "arm,cortex-a55";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 19 reg = <0x0 0x0>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 20 enable-method = "psci";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 21 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 22
1b753fcfcff8ad Xianwei Zhao 2025-03-17 23 cpu1: cpu@100 {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 24 device_type = "cpu";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 25 compatible = "arm,cortex-a55";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 26 reg = <0x0 0x100>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 27 enable-method = "psci";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 28 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 29
1b753fcfcff8ad Xianwei Zhao 2025-03-17 30 cpu2: cpu@200 {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 31 device_type = "cpu";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 32 compatible = "arm,cortex-a55";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 33 reg = <0x0 0x200>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 34 enable-method = "psci";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 35 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 36
1b753fcfcff8ad Xianwei Zhao 2025-03-17 37 cpu3: cpu@300 {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 38 device_type = "cpu";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 39 compatible = "arm,cortex-a55";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 40 reg = <0x0 0x300>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 41 enable-method = "psci";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 42 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 43
1b753fcfcff8ad Xianwei Zhao 2025-03-17 44 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 45
1b753fcfcff8ad Xianwei Zhao 2025-03-17 46 timer {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 47 compatible = "arm,armv8-timer";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1b753fcfcff8ad Xianwei Zhao 2025-03-17 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1b753fcfcff8ad Xianwei Zhao 2025-03-17 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1b753fcfcff8ad Xianwei Zhao 2025-03-17 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 52 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 53
1b753fcfcff8ad Xianwei Zhao 2025-03-17 54 psci {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 55 compatible = "arm,psci-1.0";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 56 method = "smc";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 57 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 58
1b753fcfcff8ad Xianwei Zhao 2025-03-17 59 xtal: xtal-clk {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 60 compatible = "fixed-clock";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 61 clock-frequency = <24000000>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 62 clock-output-names = "xtal";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 63 #clock-cells = <0>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 64 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 65
1b753fcfcff8ad Xianwei Zhao 2025-03-17 66 soc {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 67 compatible = "simple-bus";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 68 #address-cells = <2>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 69 #size-cells = <2>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 70 ranges;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 71
1b753fcfcff8ad Xianwei Zhao 2025-03-17 72 gic: interrupt-controller@fff01000 {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 73 compatible = "arm,gic-400";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 74 #interrupt-cells = <3>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 75 #address-cells = <0>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 76 interrupt-controller;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 77 reg = <0x0 0xfff01000 0 0x1000>,
1b753fcfcff8ad Xianwei Zhao 2025-03-17 78 <0x0 0xfff02000 0 0x0100>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 79 interrupts = <GIC_PPI 9 0xf04>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 80 };
1b753fcfcff8ad Xianwei Zhao 2025-03-17 81
1b753fcfcff8ad Xianwei Zhao 2025-03-17 82 apb: bus@fe000000 {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 83 compatible = "simple-bus";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 84 reg = <0x0 0xfe000000 0x0 0x480000>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 85 #address-cells = <2>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 86 #size-cells = <2>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 87 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 88
1b753fcfcff8ad Xianwei Zhao 2025-03-17 89 uart_b: serial@7a000 {
1b753fcfcff8ad Xianwei Zhao 2025-03-17 90 compatible = "amlogic,s7-uart",
1b753fcfcff8ad Xianwei Zhao 2025-03-17 91 "amlogic,meson-s4-uart";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 92 reg = <0x0 0x7a000 0x0 0x18>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 93 interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 94 clocks = <&xtal>, <&xtal>, <&xtal>;
1b753fcfcff8ad Xianwei Zhao 2025-03-17 95 clock-names = "xtal", "pclk", "baud";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 96 status = "disabled";
1b753fcfcff8ad Xianwei Zhao 2025-03-17 97 };
7eae48bf5844ec Xianwei Zhao 2025-05-14 98
7eae48bf5844ec Xianwei Zhao 2025-05-14 @99 periphs_pinctrl: pinctrl {
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 0/8] Add support for Amlogic S7/S7D/S6 pinctrl
@ 2025-05-14 7:01 Xianwei Zhao
2025-05-14 7:01 ` Xianwei Zhao via B4 Relay
0 siblings, 1 reply; 8+ messages in thread
From: Xianwei Zhao @ 2025-05-14 7:01 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl
Cc: linux-amlogic, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel, Xianwei Zhao
In some Amlogic SoCs, to save register space or due to some
abnormal arrangements, two sets of pins share one mux register.
A group starting from pin0 is the main pin group, which acquires
the register address through DTS and has management permissions,
but the register bit offset is undetermined.
Another GPIO group as a subordinate group. Some pins mux use share
register and bit offset from bit0 . But this group do not have
register management permissions.
In SoC S7 and S7D, GPIOX(16~19) mux share with GPIOCC mux register.
In SoC S6, GPIOX(16~19) mux share with GPIOCC mux register, and GPIOD(6)
mux share with GPIOF mux register.
Add S7/S7D/S6 pinctrl compatible string and device node.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
Xianwei Zhao (8):
dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S7
dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S7D
dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S6
pinctrl: meson: a4: remove special data processing
pinctrl: meson: support amlogic S6/S7/S7D SoC
dts: arm64: amlogic: add S7 pinctrl node
dts: arm64: amlogic: add S7D pinctrl node
dts: arm64: amlogic: add S6 pinctrl node
.../bindings/pinctrl/amlogic,pinctrl-a4.yaml | 9 +-
arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi | 97 ++++++++++++++++++
arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 81 +++++++++++++++
arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi | 90 +++++++++++++++++
drivers/pinctrl/meson/pinctrl-amlogic-a4.c | 111 ++++++++++++++++-----
5 files changed, 363 insertions(+), 25 deletions(-)
---
base-commit: aa94665adc28f3fdc3de2979ac1e98bae961d6ca
change-id: 20250514-s6-s7-pinctrl-af1ebda88a4e
Best regards,
--
Xianwei Zhao <xianwei.zhao@amlogic.com>
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 6/8] dts: arm64: amlogic: add S7 pinctrl node
2025-05-14 7:01 [PATCH 0/8] Add support for Amlogic S7/S7D/S6 pinctrl Xianwei Zhao
2025-05-14 7:01 ` Xianwei Zhao via B4 Relay
@ 2025-05-14 7:01 ` Xianwei Zhao via B4 Relay
0 siblings, 0 replies; 8+ messages in thread
From: Xianwei Zhao @ 2025-05-14 7:01 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl
Cc: linux-amlogic, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel, Xianwei Zhao
Add pinctrl device to support Amlogic S7.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 81 +++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
index f0c172681bd1..924f10aff269 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
/ {
cpus {
@@ -94,6 +95,86 @@ uart_b: serial@7a000 {
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+ periphs_pinctrl: pinctrl {
+ compatible = "amlogic,pinctrl-s7";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>;
+
+ gpioz: gpio@c0 {
+ reg = <0 0xc0 0 0x20>, <0 0x18 0 0x8>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 13>;
+ };
+
+ gpiox: gpio@100 {
+ reg = <0 0x100 0 0x30>, <0 0xc 0 0x8>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>;
+ };
+
+ gpioh: gpio@140 {
+ reg = <0 0x140 0 0x20>, <0 0x2c 0 0x8>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 12>;
+ };
+
+ gpiod: gpio@180 {
+ reg = <0 0x180 0 0x20>, <0 0x40 0 0x8>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 12>;
+ };
+
+ gpioe: gpio@1c0 {
+ reg = <0 0x1c0 0 0x20>, <0 0x48 0 0x4>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>;
+ };
+
+ gpioc: gpio@200 {
+ reg = <0 0x200 0 0x20>, <0 0x24 0 0x4>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>;
+ };
+
+ gpiob: gpio@240 {
+ reg = <0 0x240 0 0x20>, <0 0x0 0 0x8>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>;
+ };
+
+ test_n: gpio@2c0 {
+ reg = <0 0x2c0 0 0x20>;
+ reg-names = "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges =
+ <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>;
+ };
+
+ gpiocc: gpio@300 {
+ reg = <0 0x300 0 0x20>, <0 0x14 0 0x4>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>;
+ };
+ };
};
};
};
--
2.37.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 6/8] dts: arm64: amlogic: add S7 pinctrl node
@ 2025-05-14 7:01 ` Xianwei Zhao via B4 Relay
0 siblings, 0 replies; 8+ messages in thread
From: Xianwei Zhao via B4 Relay @ 2025-05-14 7:01 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl
Cc: linux-amlogic, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel, Xianwei Zhao
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Add pinctrl device to support Amlogic S7.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 81 +++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
index f0c172681bd1..924f10aff269 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
/ {
cpus {
@@ -94,6 +95,86 @@ uart_b: serial@7a000 {
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+ periphs_pinctrl: pinctrl {
+ compatible = "amlogic,pinctrl-s7";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>;
+
+ gpioz: gpio@c0 {
+ reg = <0 0xc0 0 0x20>, <0 0x18 0 0x8>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 13>;
+ };
+
+ gpiox: gpio@100 {
+ reg = <0 0x100 0 0x30>, <0 0xc 0 0x8>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>;
+ };
+
+ gpioh: gpio@140 {
+ reg = <0 0x140 0 0x20>, <0 0x2c 0 0x8>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 12>;
+ };
+
+ gpiod: gpio@180 {
+ reg = <0 0x180 0 0x20>, <0 0x40 0 0x8>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 12>;
+ };
+
+ gpioe: gpio@1c0 {
+ reg = <0 0x1c0 0 0x20>, <0 0x48 0 0x4>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>;
+ };
+
+ gpioc: gpio@200 {
+ reg = <0 0x200 0 0x20>, <0 0x24 0 0x4>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>;
+ };
+
+ gpiob: gpio@240 {
+ reg = <0 0x240 0 0x20>, <0 0x0 0 0x8>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>;
+ };
+
+ test_n: gpio@2c0 {
+ reg = <0 0x2c0 0 0x20>;
+ reg-names = "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges =
+ <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>;
+ };
+
+ gpiocc: gpio@300 {
+ reg = <0 0x300 0 0x20>, <0 0x14 0 0x4>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>;
+ };
+ };
};
};
};
--
2.37.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 6/8] dts: arm64: amlogic: add S7 pinctrl node
@ 2025-05-14 7:01 ` Xianwei Zhao via B4 Relay
0 siblings, 0 replies; 8+ messages in thread
From: Xianwei Zhao via B4 Relay @ 2025-05-14 7:01 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl
Cc: linux-amlogic, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel, Xianwei Zhao
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Add pinctrl device to support Amlogic S7.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 81 +++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
index f0c172681bd1..924f10aff269 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
/ {
cpus {
@@ -94,6 +95,86 @@ uart_b: serial@7a000 {
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+ periphs_pinctrl: pinctrl {
+ compatible = "amlogic,pinctrl-s7";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>;
+
+ gpioz: gpio@c0 {
+ reg = <0 0xc0 0 0x20>, <0 0x18 0 0x8>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 13>;
+ };
+
+ gpiox: gpio@100 {
+ reg = <0 0x100 0 0x30>, <0 0xc 0 0x8>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>;
+ };
+
+ gpioh: gpio@140 {
+ reg = <0 0x140 0 0x20>, <0 0x2c 0 0x8>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 12>;
+ };
+
+ gpiod: gpio@180 {
+ reg = <0 0x180 0 0x20>, <0 0x40 0 0x8>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 12>;
+ };
+
+ gpioe: gpio@1c0 {
+ reg = <0 0x1c0 0 0x20>, <0 0x48 0 0x4>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>;
+ };
+
+ gpioc: gpio@200 {
+ reg = <0 0x200 0 0x20>, <0 0x24 0 0x4>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>;
+ };
+
+ gpiob: gpio@240 {
+ reg = <0 0x240 0 0x20>, <0 0x0 0 0x8>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>;
+ };
+
+ test_n: gpio@2c0 {
+ reg = <0 0x2c0 0 0x20>;
+ reg-names = "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges =
+ <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>;
+ };
+
+ gpiocc: gpio@300 {
+ reg = <0 0x300 0 0x20>, <0 0x14 0 0x4>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>;
+ };
+ };
};
};
};
--
2.37.1
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http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 6/8] dts: arm64: amlogic: add S7 pinctrl node
2025-05-14 7:01 ` Xianwei Zhao via B4 Relay
@ 2025-05-14 13:10 ` Rob Herring
-1 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2025-05-14 13:10 UTC (permalink / raw)
To: Xianwei Zhao
Cc: Linus Walleij, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, linux-amlogic,
linux-gpio, devicetree, linux-kernel, linux-arm-kernel
On Wed, May 14, 2025 at 03:01:33PM +0800, Xianwei Zhao wrote:
> Add pinctrl device to support Amlogic S7.
>
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
> ---
> arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 81 +++++++++++++++++++++++++++++
> 1 file changed, 81 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
> index f0c172681bd1..924f10aff269 100644
> --- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
> @@ -6,6 +6,7 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
>
> / {
> cpus {
> @@ -94,6 +95,86 @@ uart_b: serial@7a000 {
> clock-names = "xtal", "pclk", "baud";
> status = "disabled";
> };
> +
> + periphs_pinctrl: pinctrl {
If you have non-boolean ranges, then this should have a unit address
(@4000).
> + compatible = "amlogic,pinctrl-s7";
> + #address-cells = <2>;
> + #size-cells = <2>;
Doesn't look like you need 64-bits of address and size. 1 cell is
enough.
> + ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>;
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^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 6/8] dts: arm64: amlogic: add S7 pinctrl node
@ 2025-05-14 13:10 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2025-05-14 13:10 UTC (permalink / raw)
To: Xianwei Zhao
Cc: Linus Walleij, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, linux-amlogic,
linux-gpio, devicetree, linux-kernel, linux-arm-kernel
On Wed, May 14, 2025 at 03:01:33PM +0800, Xianwei Zhao wrote:
> Add pinctrl device to support Amlogic S7.
>
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
> ---
> arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 81 +++++++++++++++++++++++++++++
> 1 file changed, 81 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
> index f0c172681bd1..924f10aff269 100644
> --- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
> @@ -6,6 +6,7 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
>
> / {
> cpus {
> @@ -94,6 +95,86 @@ uart_b: serial@7a000 {
> clock-names = "xtal", "pclk", "baud";
> status = "disabled";
> };
> +
> + periphs_pinctrl: pinctrl {
If you have non-boolean ranges, then this should have a unit address
(@4000).
> + compatible = "amlogic,pinctrl-s7";
> + #address-cells = <2>;
> + #size-cells = <2>;
Doesn't look like you need 64-bits of address and size. 1 cell is
enough.
> + ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>;
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 6/8] dts: arm64: amlogic: add S7 pinctrl node
2025-05-14 13:10 ` Rob Herring
@ 2025-05-15 3:04 ` Xianwei Zhao
-1 siblings, 0 replies; 8+ messages in thread
From: Xianwei Zhao @ 2025-05-15 3:04 UTC (permalink / raw)
To: Rob Herring
Cc: Linus Walleij, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, linux-amlogic,
linux-gpio, devicetree, linux-kernel, linux-arm-kernel
Hi Rob,
Thanks for your reply.
On 2025/5/14 21:10, Rob Herring wrote:
> [ EXTERNAL EMAIL ]
>
> On Wed, May 14, 2025 at 03:01:33PM +0800, Xianwei Zhao wrote:
>> Add pinctrl device to support Amlogic S7.
>>
>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>> ---
>> arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 81 +++++++++++++++++++++++++++++
>> 1 file changed, 81 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
>> index f0c172681bd1..924f10aff269 100644
>> --- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
>> @@ -6,6 +6,7 @@
>> #include <dt-bindings/interrupt-controller/irq.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
>>
>> / {
>> cpus {
>> @@ -94,6 +95,86 @@ uart_b: serial@7a000 {
>> clock-names = "xtal", "pclk", "baud";
>> status = "disabled";
>> };
>> +
>> + periphs_pinctrl: pinctrl {
>
> If you have non-boolean ranges, then this should have a unit address
> (@4000).
>
Will add a unit address for node.
>> + compatible = "amlogic,pinctrl-s7";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>
> Doesn't look like you need 64-bits of address and size. 1 cell is
> enough.
>
Krzysztof raised this question in the definition of binding stage.
https://lore.kernel.org/all/012cfaca-e8f5-4614-9393-a4a46a797adb@amlogic.com/
>> + ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>;
>
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http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 6/8] dts: arm64: amlogic: add S7 pinctrl node
@ 2025-05-15 3:04 ` Xianwei Zhao
0 siblings, 0 replies; 8+ messages in thread
From: Xianwei Zhao @ 2025-05-15 3:04 UTC (permalink / raw)
To: Rob Herring
Cc: Linus Walleij, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, linux-amlogic,
linux-gpio, devicetree, linux-kernel, linux-arm-kernel
Hi Rob,
Thanks for your reply.
On 2025/5/14 21:10, Rob Herring wrote:
> [ EXTERNAL EMAIL ]
>
> On Wed, May 14, 2025 at 03:01:33PM +0800, Xianwei Zhao wrote:
>> Add pinctrl device to support Amlogic S7.
>>
>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>> ---
>> arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 81 +++++++++++++++++++++++++++++
>> 1 file changed, 81 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
>> index f0c172681bd1..924f10aff269 100644
>> --- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
>> @@ -6,6 +6,7 @@
>> #include <dt-bindings/interrupt-controller/irq.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
>>
>> / {
>> cpus {
>> @@ -94,6 +95,86 @@ uart_b: serial@7a000 {
>> clock-names = "xtal", "pclk", "baud";
>> status = "disabled";
>> };
>> +
>> + periphs_pinctrl: pinctrl {
>
> If you have non-boolean ranges, then this should have a unit address
> (@4000).
>
Will add a unit address for node.
>> + compatible = "amlogic,pinctrl-s7";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>
> Doesn't look like you need 64-bits of address and size. 1 cell is
> enough.
>
Krzysztof raised this question in the definition of binding stage.
https://lore.kernel.org/all/012cfaca-e8f5-4614-9393-a4a46a797adb@amlogic.com/
>> + ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>;
>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-05-15 3:07 UTC | newest]
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2025-05-14 7:01 [PATCH 0/8] Add support for Amlogic S7/S7D/S6 pinctrl Xianwei Zhao
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2025-05-14 7:01 ` Xianwei Zhao via B4 Relay
2025-05-14 7:01 ` Xianwei Zhao via B4 Relay
2025-05-14 13:10 ` Rob Herring
2025-05-14 13:10 ` Rob Herring
2025-05-15 3:04 ` Xianwei Zhao
2025-05-15 3:04 ` Xianwei Zhao
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