From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Fabiano Rosas" <farosas@suse.de>,
"Laurent Vivier" <lvivier@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>
Subject: [PATCH v3 24/28] test/qtest/hace: Update source data and digest data type to 64-bit
Date: Thu, 15 May 2025 16:09:56 +0800 [thread overview]
Message-ID: <20250515081008.583578-25-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250515081008.583578-1-jamin_lin@aspeedtech.com>
Currently, the hash data source and digest result buffer addresses are set to
32-bit. However, the AST2700 CPU is a 64-bit Cortex-A35 architecture, and its
DRAM base address is also 64-bit.
To support AST2700, update the hash data source address and digest result buffer
address to use 64-bit addressing.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
tests/qtest/aspeed-hace-utils.h | 20 ++++-----
tests/qtest/aspeed-hace-utils.c | 72 ++++++++++++++++-----------------
2 files changed, 46 insertions(+), 46 deletions(-)
diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-utils.h
index f4440561de..0382570fa2 100644
--- a/tests/qtest/aspeed-hace-utils.h
+++ b/tests/qtest/aspeed-hace-utils.h
@@ -51,25 +51,25 @@ struct AspeedMasks {
};
void aspeed_test_md5(const char *machine, const uint32_t base,
- const uint32_t src_addr);
+ const uint64_t src_addr);
void aspeed_test_sha256(const char *machine, const uint32_t base,
- const uint32_t src_addr);
+ const uint64_t src_addr);
void aspeed_test_sha384(const char *machine, const uint32_t base,
- const uint32_t src_addr);
+ const uint64_t src_addr);
void aspeed_test_sha512(const char *machine, const uint32_t base,
- const uint32_t src_addr);
+ const uint64_t src_addr);
void aspeed_test_sha256_sg(const char *machine, const uint32_t base,
- const uint32_t src_addr);
+ const uint64_t src_addr);
void aspeed_test_sha384_sg(const char *machine, const uint32_t base,
- const uint32_t src_addr);
+ const uint64_t src_addr);
void aspeed_test_sha512_sg(const char *machine, const uint32_t base,
- const uint32_t src_addr);
+ const uint64_t src_addr);
void aspeed_test_sha256_accum(const char *machine, const uint32_t base,
- const uint32_t src_addr);
+ const uint64_t src_addr);
void aspeed_test_sha384_accum(const char *machine, const uint32_t base,
- const uint32_t src_addr);
+ const uint64_t src_addr);
void aspeed_test_sha512_accum(const char *machine, const uint32_t base,
- const uint32_t src_addr);
+ const uint64_t src_addr);
void aspeed_test_addresses(const char *machine, const uint32_t base,
const struct AspeedMasks *expected);
diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-utils.c
index dad90ee81c..1b54870dd4 100644
--- a/tests/qtest/aspeed-hace-utils.c
+++ b/tests/qtest/aspeed-hace-utils.c
@@ -153,22 +153,22 @@ static const uint8_t test_result_accum_sha256[32] = {
0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c,
0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad};
-static void write_regs(QTestState *s, uint32_t base, uint32_t src,
- uint32_t length, uint32_t out, uint32_t method)
+static void write_regs(QTestState *s, uint32_t base, uint64_t src,
+ uint32_t length, uint64_t out, uint32_t method)
{
- qtest_writel(s, base + HACE_HASH_SRC, src);
- qtest_writel(s, base + HACE_HASH_DIGEST, out);
+ qtest_writel(s, base + HACE_HASH_SRC, extract64(src, 0, 32));
+ qtest_writel(s, base + HACE_HASH_DIGEST, extract64(out, 0, 32));
qtest_writel(s, base + HACE_HASH_DATA_LEN, length);
qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method);
}
void aspeed_test_md5(const char *machine, const uint32_t base,
- const uint32_t src_addr)
+ const uint64_t src_addr)
{
QTestState *s = qtest_init(machine);
- uint32_t digest_addr = src_addr + 0x010000;
+ uint64_t digest_addr = src_addr + 0x010000;
uint8_t digest[16] = {0};
/* Check engine is idle, no busy or irq bits set */
@@ -198,11 +198,11 @@ void aspeed_test_md5(const char *machine, const uint32_t base,
}
void aspeed_test_sha256(const char *machine, const uint32_t base,
- const uint32_t src_addr)
+ const uint64_t src_addr)
{
QTestState *s = qtest_init(machine);
- const uint32_t digest_addr = src_addr + 0x10000;
+ const uint64_t digest_addr = src_addr + 0x10000;
uint8_t digest[32] = {0};
/* Check engine is idle, no busy or irq bits set */
@@ -232,11 +232,11 @@ void aspeed_test_sha256(const char *machine, const uint32_t base,
}
void aspeed_test_sha384(const char *machine, const uint32_t base,
- const uint32_t src_addr)
+ const uint64_t src_addr)
{
QTestState *s = qtest_init(machine);
- const uint32_t digest_addr = src_addr + 0x10000;
+ const uint64_t digest_addr = src_addr + 0x10000;
uint8_t digest[48] = {0};
/* Check engine is idle, no busy or irq bits set */
@@ -266,11 +266,11 @@ void aspeed_test_sha384(const char *machine, const uint32_t base,
}
void aspeed_test_sha512(const char *machine, const uint32_t base,
- const uint32_t src_addr)
+ const uint64_t src_addr)
{
QTestState *s = qtest_init(machine);
- const uint32_t digest_addr = src_addr + 0x10000;
+ const uint64_t digest_addr = src_addr + 0x10000;
uint8_t digest[64] = {0};
/* Check engine is idle, no busy or irq bits set */
@@ -300,14 +300,14 @@ void aspeed_test_sha512(const char *machine, const uint32_t base,
}
void aspeed_test_sha256_sg(const char *machine, const uint32_t base,
- const uint32_t src_addr)
+ const uint64_t src_addr)
{
QTestState *s = qtest_init(machine);
- const uint32_t src_addr_1 = src_addr + 0x10000;
- const uint32_t src_addr_2 = src_addr + 0x20000;
- const uint32_t src_addr_3 = src_addr + 0x30000;
- const uint32_t digest_addr = src_addr + 0x40000;
+ const uint64_t src_addr_1 = src_addr + 0x10000;
+ const uint64_t src_addr_2 = src_addr + 0x20000;
+ const uint64_t src_addr_3 = src_addr + 0x30000;
+ const uint64_t digest_addr = src_addr + 0x40000;
uint8_t digest[32] = {0};
struct AspeedSgList array[] = {
{ cpu_to_le32(sizeof(test_vector_sg1)),
@@ -351,14 +351,14 @@ void aspeed_test_sha256_sg(const char *machine, const uint32_t base,
}
void aspeed_test_sha384_sg(const char *machine, const uint32_t base,
- const uint32_t src_addr)
+ const uint64_t src_addr)
{
QTestState *s = qtest_init(machine);
- const uint32_t src_addr_1 = src_addr + 0x10000;
- const uint32_t src_addr_2 = src_addr + 0x20000;
- const uint32_t src_addr_3 = src_addr + 0x30000;
- const uint32_t digest_addr = src_addr + 0x40000;
+ const uint64_t src_addr_1 = src_addr + 0x10000;
+ const uint64_t src_addr_2 = src_addr + 0x20000;
+ const uint64_t src_addr_3 = src_addr + 0x30000;
+ const uint64_t digest_addr = src_addr + 0x40000;
uint8_t digest[48] = {0};
struct AspeedSgList array[] = {
{ cpu_to_le32(sizeof(test_vector_sg1)),
@@ -402,14 +402,14 @@ void aspeed_test_sha384_sg(const char *machine, const uint32_t base,
}
void aspeed_test_sha512_sg(const char *machine, const uint32_t base,
- const uint32_t src_addr)
+ const uint64_t src_addr)
{
QTestState *s = qtest_init(machine);
- const uint32_t src_addr_1 = src_addr + 0x10000;
- const uint32_t src_addr_2 = src_addr + 0x20000;
- const uint32_t src_addr_3 = src_addr + 0x30000;
- const uint32_t digest_addr = src_addr + 0x40000;
+ const uint64_t src_addr_1 = src_addr + 0x10000;
+ const uint64_t src_addr_2 = src_addr + 0x20000;
+ const uint64_t src_addr_3 = src_addr + 0x30000;
+ const uint64_t digest_addr = src_addr + 0x40000;
uint8_t digest[64] = {0};
struct AspeedSgList array[] = {
{ cpu_to_le32(sizeof(test_vector_sg1)),
@@ -453,12 +453,12 @@ void aspeed_test_sha512_sg(const char *machine, const uint32_t base,
}
void aspeed_test_sha256_accum(const char *machine, const uint32_t base,
- const uint32_t src_addr)
+ const uint64_t src_addr)
{
QTestState *s = qtest_init(machine);
- const uint32_t buffer_addr = src_addr + 0x10000;
- const uint32_t digest_addr = src_addr + 0x40000;
+ const uint64_t buffer_addr = src_addr + 0x10000;
+ const uint64_t digest_addr = src_addr + 0x40000;
uint8_t digest[32] = {0};
struct AspeedSgList array[] = {
{ cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST),
@@ -494,12 +494,12 @@ void aspeed_test_sha256_accum(const char *machine, const uint32_t base,
}
void aspeed_test_sha384_accum(const char *machine, const uint32_t base,
- const uint32_t src_addr)
+ const uint64_t src_addr)
{
QTestState *s = qtest_init(machine);
- const uint32_t buffer_addr = src_addr + 0x10000;
- const uint32_t digest_addr = src_addr + 0x40000;
+ const uint64_t buffer_addr = src_addr + 0x10000;
+ const uint64_t digest_addr = src_addr + 0x40000;
uint8_t digest[48] = {0};
struct AspeedSgList array[] = {
{ cpu_to_le32(sizeof(test_vector_accum_384) | SG_LIST_LEN_LAST),
@@ -535,12 +535,12 @@ void aspeed_test_sha384_accum(const char *machine, const uint32_t base,
}
void aspeed_test_sha512_accum(const char *machine, const uint32_t base,
- const uint32_t src_addr)
+ const uint64_t src_addr)
{
QTestState *s = qtest_init(machine);
- const uint32_t buffer_addr = src_addr + 0x10000;
- const uint32_t digest_addr = src_addr + 0x40000;
+ const uint64_t buffer_addr = src_addr + 0x10000;
+ const uint64_t digest_addr = src_addr + 0x40000;
uint8_t digest[64] = {0};
struct AspeedSgList array[] = {
{ cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST),
--
2.43.0
next prev parent reply other threads:[~2025-05-15 8:14 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-15 8:09 [PATCH v3 00/28] Fix incorrect hash results on AST2700 Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 01/28] hw/misc/aspeed_hace: Remove unused code for better readability Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 02/28] hw/misc/aspeed_hace: Improve readability and consistency in variable naming Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 03/28] hw/misc/aspeed_hace: Ensure HASH_IRQ is always set to prevent firmware hang Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 04/28] hw/misc/aspeed_hace: Extract direct mode hash buffer setup into helper function Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 05/28] hw/misc/aspeed_hace: Extract SG-mode " Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 06/28] hw/misc/aspeed_hace: Extract digest write and iov unmap " Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 07/28] hw/misc/aspeed_hace: Extract non-accumulation hash execution " Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 08/28] hw/misc/aspeed_hace: Extract accumulation-mode " Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 09/28] hw/misc/aspeed_hace: Introduce 64-bit hash source address " Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 10/28] hw/misc/aspeed_hace: Rename R_HASH_DEST to R_HASH_DIGEST and introduce 64-bit hash digest address helper Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 11/28] hw/misc/aspeed_hace: Support accumulative mode for direct access mode Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 12/28] hw/misc/aspeed_hace: Move register size to instance class and dynamically allocate regs Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 13/28] hw/misc/aspeed_hace: Add support for source, digest, key buffer 64 bit addresses Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 14/28] hw/misc/aspeed_hace: Support DMA 64 bits dram address Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 15/28] hw/misc/aspeed_hace: Add trace-events for better debugging Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 16/28] hw/misc/aspeed_hace: Support to dump plaintext and digest " Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 17/28] tests/qtest: Reorder aspeed test list Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 18/28] test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 19/28] test/qtest/hace: Specify explicit array sizes for test vectors and hash results Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 20/28] test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 21/28] test/qtest/hace: Add SHA-384 test cases for ASPEED HACE model Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 22/28] test/qtest/hace: Add SHA-384 tests for AST2600 Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 23/28] test/qtest/hace: Add tests for AST1030 Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via [this message]
2025-05-15 8:09 ` [PATCH v3 25/28] test/qtest/hace: Support 64-bit source and digest addresses for AST2700 Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 26/28] test/qtest/hace: Support to test upper 32 bits of digest and source addresses Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 27/28] test/qtest/hace: Support to validate 64-bit hmac key buffer addresses Jamin Lin via
2025-05-15 8:10 ` [PATCH v3 28/28] test/qtest/hace: Add tests for AST2700 Jamin Lin via
2025-05-20 14:58 ` [PATCH v3 00/28] Fix incorrect hash results on AST2700 Fabiano Rosas
2025-05-23 7:17 ` Cédric Le Goater
2025-05-23 8:10 ` Cédric Le Goater
2025-05-29 7:29 ` Michael Tokarev
2025-05-29 7:38 ` Cédric Le Goater
2025-05-29 7:40 ` Jamin Lin
2025-05-29 7:45 ` Michael Tokarev
2025-05-29 12:17 ` Cédric Le Goater
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