All of lore.kernel.org
 help / color / mirror / Atom feed
From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Steven Lee" <steven_lee@aspeedtech.com>,
	"Troy Lee" <leetroy@gmail.com>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Joel Stanley" <joel@jms.id.au>,
	"Fabiano Rosas" <farosas@suse.de>,
	"Laurent Vivier" <lvivier@redhat.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>
Subject: [PATCH v3 04/28] hw/misc/aspeed_hace: Extract direct mode hash buffer setup into helper function
Date: Thu, 15 May 2025 16:09:36 +0800	[thread overview]
Message-ID: <20250515081008.583578-5-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250515081008.583578-1-jamin_lin@aspeedtech.com>

To improve code readability and maintainability of do_hash_operation(), this
commit introduces a new helper function: hash_prepare_direct_iov().
This function encapsulates the logic for setting up the I/O vector (iov)
in direct mode (non-scatter-gather).

No functional changes are introduced.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/misc/aspeed_hace.c | 42 ++++++++++++++++++++++++++++++++----------
 1 file changed, 32 insertions(+), 10 deletions(-)

diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 1256926d22..42c6f29f82 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -142,6 +142,31 @@ static bool has_padding(AspeedHACEState *s, struct iovec *iov,
     return false;
 }
 
+static int hash_prepare_direct_iov(AspeedHACEState *s, struct iovec *iov)
+{
+    uint32_t src;
+    void *haddr;
+    hwaddr plen;
+    int iov_idx;
+
+    plen = s->regs[R_HASH_SRC_LEN];
+    src = s->regs[R_HASH_SRC];
+    haddr = address_space_map(&s->dram_as, src, &plen, false,
+                              MEMTXATTRS_UNSPECIFIED);
+    if (haddr == NULL) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Unable to map address, addr=0x%x, "
+                      "plen=0x%" HWADDR_PRIx "\n",
+                      __func__, src, plen);
+        return -1;
+    }
+
+    iov[0].iov_base = haddr;
+    iov[0].iov_len = plen;
+    iov_idx = 1;
+
+    return iov_idx;
+}
 static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
                               bool acc_mode)
 {
@@ -169,6 +194,7 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
         }
     }
 
+    /* Prepares the iov for hashing operations based on the selected mode */
     if (sg_mode) {
         for (iov_idx = 0; !(len & SG_LIST_LEN_LAST); iov_idx++) {
             if (iov_idx == ASPEED_HACE_MAX_SG) {
@@ -211,17 +237,13 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
             }
         }
     } else {
-        plen = s->regs[R_HASH_SRC_LEN];
+        iov_idx = hash_prepare_direct_iov(s, iov);
+    }
 
-        haddr = address_space_map(&s->dram_as, s->regs[R_HASH_SRC],
-                                  &plen, false, MEMTXATTRS_UNSPECIFIED);
-        if (haddr == NULL) {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__);
-            return;
-        }
-        iov[0].iov_base = haddr;
-        iov[0].iov_len = plen;
-        iov_idx = 1;
+    if (iov_idx <= 0) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Failed to prepare iov\n", __func__);
+         return;
     }
 
     if (acc_mode) {
-- 
2.43.0


  parent reply	other threads:[~2025-05-15  8:11 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-15  8:09 [PATCH v3 00/28] Fix incorrect hash results on AST2700 Jamin Lin via
2025-05-15  8:09 ` Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 01/28] hw/misc/aspeed_hace: Remove unused code for better readability Jamin Lin via
2025-05-15  8:09   ` Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 02/28] hw/misc/aspeed_hace: Improve readability and consistency in variable naming Jamin Lin via
2025-05-15  8:09   ` Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 03/28] hw/misc/aspeed_hace: Ensure HASH_IRQ is always set to prevent firmware hang Jamin Lin via
2025-05-15  8:09 ` Jamin Lin via [this message]
2025-05-15  8:09 ` [PATCH v3 05/28] hw/misc/aspeed_hace: Extract SG-mode hash buffer setup into helper function Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 06/28] hw/misc/aspeed_hace: Extract digest write and iov unmap " Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 07/28] hw/misc/aspeed_hace: Extract non-accumulation hash execution " Jamin Lin via
2025-05-15  8:09   ` Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 08/28] hw/misc/aspeed_hace: Extract accumulation-mode " Jamin Lin via
2025-05-15  8:09   ` Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 09/28] hw/misc/aspeed_hace: Introduce 64-bit hash source address " Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 10/28] hw/misc/aspeed_hace: Rename R_HASH_DEST to R_HASH_DIGEST and introduce 64-bit hash digest address helper Jamin Lin via
2025-05-15  8:09   ` Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 11/28] hw/misc/aspeed_hace: Support accumulative mode for direct access mode Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 12/28] hw/misc/aspeed_hace: Move register size to instance class and dynamically allocate regs Jamin Lin via
2025-05-15  8:09   ` Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 13/28] hw/misc/aspeed_hace: Add support for source, digest, key buffer 64 bit addresses Jamin Lin via
2025-05-15  8:09   ` Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 14/28] hw/misc/aspeed_hace: Support DMA 64 bits dram address Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 15/28] hw/misc/aspeed_hace: Add trace-events for better debugging Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 16/28] hw/misc/aspeed_hace: Support to dump plaintext and digest " Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 17/28] tests/qtest: Reorder aspeed test list Jamin Lin via
2025-05-15  8:09   ` Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 18/28] test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases Jamin Lin via
2025-05-15  8:09   ` Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 19/28] test/qtest/hace: Specify explicit array sizes for test vectors and hash results Jamin Lin via
2025-05-15  8:09   ` Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 20/28] test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations Jamin Lin via
2025-05-15  8:09   ` Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 21/28] test/qtest/hace: Add SHA-384 test cases for ASPEED HACE model Jamin Lin via
2025-05-15  8:09   ` Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 22/28] test/qtest/hace: Add SHA-384 tests for AST2600 Jamin Lin via
2025-05-15  8:09   ` Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 23/28] test/qtest/hace: Add tests for AST1030 Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 24/28] test/qtest/hace: Update source data and digest data type to 64-bit Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 25/28] test/qtest/hace: Support 64-bit source and digest addresses for AST2700 Jamin Lin via
2025-05-15  8:09   ` Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 26/28] test/qtest/hace: Support to test upper 32 bits of digest and source addresses Jamin Lin via
2025-05-15  8:09   ` Jamin Lin via
2025-05-15  8:09 ` [PATCH v3 27/28] test/qtest/hace: Support to validate 64-bit hmac key buffer addresses Jamin Lin via
2025-05-15  8:10 ` [PATCH v3 28/28] test/qtest/hace: Add tests for AST2700 Jamin Lin via
2025-05-20 14:58 ` [PATCH v3 00/28] Fix incorrect hash results on AST2700 Fabiano Rosas
2025-05-23  7:17 ` Cédric Le Goater
2025-05-23  8:10 ` Cédric Le Goater
2025-05-29  7:29 ` Michael Tokarev
2025-05-29  7:38   ` Cédric Le Goater
2025-05-29  7:40     ` Jamin Lin
2025-05-29  7:45       ` Michael Tokarev
2025-05-29 12:17         ` Cédric Le Goater

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20250515081008.583578-5-jamin_lin@aspeedtech.com \
    --to=qemu-devel@nongnu.org \
    --cc=andrew@codeconstruct.com.au \
    --cc=clg@kaod.org \
    --cc=farosas@suse.de \
    --cc=jamin_lin@aspeedtech.com \
    --cc=joel@jms.id.au \
    --cc=leetroy@gmail.com \
    --cc=lvivier@redhat.com \
    --cc=pbonzini@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=steven_lee@aspeedtech.com \
    --cc=troy_lee@aspeedtech.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.