* [PATCH v4 0/4] Add SpacemiT K1 USB3.0 host controller support
@ 2025-05-26 14:40 ` Ze Huang
0 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-05-26 14:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: linux-usb, devicetree, linux-riscv, spacemit, linux-kernel,
Ze Huang
The USB 3.0 controller found in the SpacemiT K1 SoC[1] supports both USB3.0
Host and USB2.0 Dual-Role Device (DRD). The PHY interfaces required for the
K1 USB subsystem — PIPE3 (for USB 3.0) and UTMI+ (for USB 2.0) — have
already been supported in a separate patchset [2].
This controller is compatible with DesignWare Core USB 3 (DWC3) driver.
However, constraints in the snps,dwc3 binding limit the ability to extend
properties to describe hardware variations. The existing generic DWC3 driver,
dwc3-of-simple, still functions as a glue layer.
To address this and promote trasition to flattened dwc node, this patch
introduces dwc3-common, building upon prior work that exposed the DWC3 core
driver [3].
This patchset is based on usb-next (6.15-rc6) and has been tested on BananaPi and Jupiter development boards.
Link: https://developer.spacemit.com/documentation?token=AjHDwrW78igAAEkiHracBI9HnTb [1]
Link: https://lore.kernel.org/linux-riscv/20250418-b4-k1-usb3-phy-v2-v2-0-b69e02da84eb@whut.edu.cn [2]
Link: https://lore.kernel.org/all/20250414-dwc3-refactor-v7-3-f015b358722d@oss.qualcomm.com [3]
Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
Changes in v4:
- dt-bindings spacemit,k1-dwc:
- reorder properties
- add properties of phys & phy-names
- add usb hub nodes in example dt
- add support for spacemit,k1-mbus
- dwc3 generic plat driver:
- rename dwc3-common.c to dwc3-generic-plat.c
- use SYSTEM_SLEEP_PM_OPS macros and drop PM guards
- dts:
- reorder dts properties of usb dwc3 node
- move "dr_mode" of dwc3 from dtsi to dts
- Link to v3: https://lore.kernel.org/r/20250518-b4-k1-dwc3-v3-v3-0-7609c8baa2a6@whut.edu.cn
Changes in v3:
- introduce dwc3-common for generic dwc3 hardware
- fix warnings in usb host dt-bindings
- fix errors in dts
- Link to v2: https://lore.kernel.org/r/20250428-b4-k1-dwc3-v2-v1-0-7cb061abd619@whut.edu.cn
Changes in v2:
- dt-bindings:
- add missing 'maxItems'
- remove 'status' property in exmaple
- fold dwc3 node into parent
- drop dwc3 glue driver and use snps,dwc3 driver directly
- rename dts nodes and reorder properties to fit coding style
- Link to v1: https://lore.kernel.org/all/20250407-b4-k1-usb3-v3-2-v1-0-bf0bcc41c9ba@whut.edu.cn
---
Ze Huang (4):
dt-bindings: usb: dwc3: add support for SpacemiT K1
dt-bindings: soc: spacemit: Add K1 MBUS controller
usb: dwc3: add generic driver to support flattened DT
riscv: dts: spacemit: add usb3.0 support for K1
.../bindings/soc/spacemit/spacemit,k1-mbus.yaml | 55 ++++++
.../devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 116 +++++++++++++
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 51 ++++++
arch/riscv/boot/dts/spacemit/k1.dtsi | 67 ++++++++
drivers/usb/dwc3/Kconfig | 9 +
drivers/usb/dwc3/Makefile | 1 +
drivers/usb/dwc3/dwc3-generic-plat.c | 189 +++++++++++++++++++++
7 files changed, 488 insertions(+)
---
base-commit: ab6dc9a6c721c2eed867c157447764ae68ff9b7e
change-id: 20250517-b4-k1-dwc3-v3-5208a002728a
Best regards,
--
Ze Huang <huangze@whut.edu.cn>
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH v4 1/4] dt-bindings: usb: dwc3: add support for SpacemiT K1
2025-05-26 14:40 ` Ze Huang
@ 2025-05-26 14:40 ` Ze Huang
-1 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-05-26 14:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: linux-usb, devicetree, linux-riscv, spacemit, linux-kernel,
Ze Huang
Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded
in the SpacemiT K1 SoC. The controller is based on the Synopsys
DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0
DRD mode.
Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
.../devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 116 +++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..bba3fc1c020500383b1256a97648be3f626c7602
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/spacemit,k1-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 SuperSpeed DWC3 USB SoC Controller
+
+maintainers:
+ - Ze Huang <huangze9015@gmail.com>
+
+description: |
+ The SpacemiT K1 embeds a DWC3 USB IP Core which supports Host functions
+ for USB 3.0 and DRD for USB 2.0.
+
+ Key features:
+ - USB3.0 SuperSpeed and USB2.0 High/Full/Low-Speed support
+ - Supports low-power modes (USB2.0 suspend, USB3.0 U1/U2/U3)
+ - Internal DMA controller and flexible endpoint FIFO sizing
+
+ Communication Interface:
+ - Use of PIPE3 (125MHz) interface for USB3.0 PHY
+ - Use of UTMI+ (30/60MHz) interface for USB2.0 PHY
+
+allOf:
+ - $ref: snps,dwc3-common.yaml#
+
+properties:
+ compatible:
+ const: spacemit,k1-dwc3
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: usbdrd30
+
+ interconnects:
+ maxItems: 1
+ description:
+ On SpacemiT K1, USB performs DMA through bus other than parent DT node.
+ The 'interconnects' property explicitly describes this path, ensuring
+ correct address translation.
+
+ interconnect-names:
+ const: dma-mem
+
+ interrupts:
+ maxItems: 1
+
+ phys:
+ items:
+ - description: phandle to USB2/HS PHY
+ - description: phandle to USB3/SS PHY
+
+ phy-names:
+ items:
+ - const: usb2-phy
+ - const: usb3-phy
+
+ resets:
+ maxItems: 1
+
+ vbus-supply:
+ description: A phandle to the regulator supplying the VBUS voltage.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interconnects
+ - interconnect-names
+ - interrupts
+ - phys
+ - phy-names
+ - resets
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ usb@c0a00000 {
+ compatible = "spacemit,k1-dwc3";
+ reg = <0xc0a00000 0x10000>;
+ clocks = <&syscon_apmu 16>;
+ clock-names = "usbdrd30";
+ interconnects = <&mbus0>;
+ interconnect-names = "dma-mem";
+ interrupts = <125>;
+ phys = <&usb2phy>, <&usb3phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ resets = <&syscon_apmu 8>;
+ vbus-supply = <&usb3_vbus>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hub_2_0: hub@1 {
+ compatible = "usb2109,2817";
+ reg = <1>;
+ vdd-supply = <&usb3_vhub>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&gpio 3 28 1>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb2109,817";
+ reg = <2>;
+ vdd-supply = <&usb3_vhub>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpio 3 28 1>;
+ };
+ };
--
2.49.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH v4 1/4] dt-bindings: usb: dwc3: add support for SpacemiT K1
@ 2025-05-26 14:40 ` Ze Huang
0 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-05-26 14:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: linux-usb, devicetree, linux-riscv, spacemit, linux-kernel,
Ze Huang
Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded
in the SpacemiT K1 SoC. The controller is based on the Synopsys
DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0
DRD mode.
Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
.../devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 116 +++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..bba3fc1c020500383b1256a97648be3f626c7602
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/spacemit,k1-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 SuperSpeed DWC3 USB SoC Controller
+
+maintainers:
+ - Ze Huang <huangze9015@gmail.com>
+
+description: |
+ The SpacemiT K1 embeds a DWC3 USB IP Core which supports Host functions
+ for USB 3.0 and DRD for USB 2.0.
+
+ Key features:
+ - USB3.0 SuperSpeed and USB2.0 High/Full/Low-Speed support
+ - Supports low-power modes (USB2.0 suspend, USB3.0 U1/U2/U3)
+ - Internal DMA controller and flexible endpoint FIFO sizing
+
+ Communication Interface:
+ - Use of PIPE3 (125MHz) interface for USB3.0 PHY
+ - Use of UTMI+ (30/60MHz) interface for USB2.0 PHY
+
+allOf:
+ - $ref: snps,dwc3-common.yaml#
+
+properties:
+ compatible:
+ const: spacemit,k1-dwc3
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: usbdrd30
+
+ interconnects:
+ maxItems: 1
+ description:
+ On SpacemiT K1, USB performs DMA through bus other than parent DT node.
+ The 'interconnects' property explicitly describes this path, ensuring
+ correct address translation.
+
+ interconnect-names:
+ const: dma-mem
+
+ interrupts:
+ maxItems: 1
+
+ phys:
+ items:
+ - description: phandle to USB2/HS PHY
+ - description: phandle to USB3/SS PHY
+
+ phy-names:
+ items:
+ - const: usb2-phy
+ - const: usb3-phy
+
+ resets:
+ maxItems: 1
+
+ vbus-supply:
+ description: A phandle to the regulator supplying the VBUS voltage.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interconnects
+ - interconnect-names
+ - interrupts
+ - phys
+ - phy-names
+ - resets
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ usb@c0a00000 {
+ compatible = "spacemit,k1-dwc3";
+ reg = <0xc0a00000 0x10000>;
+ clocks = <&syscon_apmu 16>;
+ clock-names = "usbdrd30";
+ interconnects = <&mbus0>;
+ interconnect-names = "dma-mem";
+ interrupts = <125>;
+ phys = <&usb2phy>, <&usb3phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ resets = <&syscon_apmu 8>;
+ vbus-supply = <&usb3_vbus>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hub_2_0: hub@1 {
+ compatible = "usb2109,2817";
+ reg = <1>;
+ vdd-supply = <&usb3_vhub>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&gpio 3 28 1>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb2109,817";
+ reg = <2>;
+ vdd-supply = <&usb3_vhub>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpio 3 28 1>;
+ };
+ };
--
2.49.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [PATCH v4 1/4] dt-bindings: usb: dwc3: add support for SpacemiT K1
2025-05-26 14:40 ` Ze Huang
@ 2025-05-27 6:47 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 40+ messages in thread
From: Krzysztof Kozlowski @ 2025-05-27 6:47 UTC (permalink / raw)
To: Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On Mon, May 26, 2025 at 10:40:17PM GMT, Ze Huang wrote:
> Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded
> in the SpacemiT K1 SoC. The controller is based on the Synopsys
> DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0
> DRD mode.
>
> Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> ---
> .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 116 +++++++++++++++++++++
> 1 file changed, 116 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: usb: dwc3: add support for SpacemiT K1
@ 2025-05-27 6:47 ` Krzysztof Kozlowski
0 siblings, 0 replies; 40+ messages in thread
From: Krzysztof Kozlowski @ 2025-05-27 6:47 UTC (permalink / raw)
To: Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On Mon, May 26, 2025 at 10:40:17PM GMT, Ze Huang wrote:
> Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded
> in the SpacemiT K1 SoC. The controller is based on the Synopsys
> DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0
> DRD mode.
>
> Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> ---
> .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 116 +++++++++++++++++++++
> 1 file changed, 116 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: usb: dwc3: add support for SpacemiT K1
2025-05-26 14:40 ` Ze Huang
@ 2025-05-27 6:53 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 40+ messages in thread
From: Krzysztof Kozlowski @ 2025-05-27 6:53 UTC (permalink / raw)
To: Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On Mon, May 26, 2025 at 10:40:17PM GMT, Ze Huang wrote:
> +
> + interconnects:
> + maxItems: 1
> + description:
> + On SpacemiT K1, USB performs DMA through bus other than parent DT node.
> + The 'interconnects' property explicitly describes this path, ensuring
> + correct address translation.
This does not seem write. You mixed DMA with interconnects.
> +
> + interconnect-names:
> + const: dma-mem
_______________________________________________
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^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: usb: dwc3: add support for SpacemiT K1
@ 2025-05-27 6:53 ` Krzysztof Kozlowski
0 siblings, 0 replies; 40+ messages in thread
From: Krzysztof Kozlowski @ 2025-05-27 6:53 UTC (permalink / raw)
To: Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On Mon, May 26, 2025 at 10:40:17PM GMT, Ze Huang wrote:
> +
> + interconnects:
> + maxItems: 1
> + description:
> + On SpacemiT K1, USB performs DMA through bus other than parent DT node.
> + The 'interconnects' property explicitly describes this path, ensuring
> + correct address translation.
This does not seem write. You mixed DMA with interconnects.
> +
> + interconnect-names:
> + const: dma-mem
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v4 2/4] dt-bindings: soc: spacemit: Add K1 MBUS controller
2025-05-26 14:40 ` Ze Huang
@ 2025-05-26 14:40 ` Ze Huang
-1 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-05-26 14:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: linux-usb, devicetree, linux-riscv, spacemit, linux-kernel,
Ze Huang
Some devices on the SpacemiT K1 SoC perform DMA through a memory bus
(MBUS) that is not their immediate parent in the device tree. This bus
uses a different address mapping than the CPU.
To express this topology properly, devices are expected to use the
interconnects with name "dma-mem" to reference the MBUS controller.
Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
.../bindings/soc/spacemit/spacemit,k1-mbus.yaml | 55 ++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..533cf99dff689cf55a159118c32a676054294ffa
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-mbus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT Memory Bus controller
+
+maintainers:
+ - Ze Huang <huangze9015@gmail.com>
+
+description: |
+ On the SpacemiT K1 SoC, some devices do not perform DMA through their
+ immediate parent node in the device tree. Instead, they access memory
+ through a separate memory bus (MBUS) that uses a different address
+ mapping from the CPU.
+
+ To correctly describe the DMA path, such devices must reference the MBUS
+ controller through an interconnect with the reserved name "dma-mem".
+
+properties:
+ compatible:
+ const: spacemit,k1-mbus
+
+ reg:
+ maxItems: 1
+
+ dma-ranges:
+ maxItems: 1
+
+ "#address-cells": true
+
+ "#size-cells": true
+
+ "#interconnect-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - dma-ranges
+ - "#interconnect-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ dram-controller@0 {
+ compatible = "spacemit,k1-mbus";
+ reg = <0x00000000 0x80000000>;
+ dma-ranges = <0x00000000 0x00000000 0x80000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interconnect-cells = <0>;
+ };
--
2.49.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH v4 2/4] dt-bindings: soc: spacemit: Add K1 MBUS controller
@ 2025-05-26 14:40 ` Ze Huang
0 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-05-26 14:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: linux-usb, devicetree, linux-riscv, spacemit, linux-kernel,
Ze Huang
Some devices on the SpacemiT K1 SoC perform DMA through a memory bus
(MBUS) that is not their immediate parent in the device tree. This bus
uses a different address mapping than the CPU.
To express this topology properly, devices are expected to use the
interconnects with name "dma-mem" to reference the MBUS controller.
Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
.../bindings/soc/spacemit/spacemit,k1-mbus.yaml | 55 ++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..533cf99dff689cf55a159118c32a676054294ffa
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-mbus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT Memory Bus controller
+
+maintainers:
+ - Ze Huang <huangze9015@gmail.com>
+
+description: |
+ On the SpacemiT K1 SoC, some devices do not perform DMA through their
+ immediate parent node in the device tree. Instead, they access memory
+ through a separate memory bus (MBUS) that uses a different address
+ mapping from the CPU.
+
+ To correctly describe the DMA path, such devices must reference the MBUS
+ controller through an interconnect with the reserved name "dma-mem".
+
+properties:
+ compatible:
+ const: spacemit,k1-mbus
+
+ reg:
+ maxItems: 1
+
+ dma-ranges:
+ maxItems: 1
+
+ "#address-cells": true
+
+ "#size-cells": true
+
+ "#interconnect-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - dma-ranges
+ - "#interconnect-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ dram-controller@0 {
+ compatible = "spacemit,k1-mbus";
+ reg = <0x00000000 0x80000000>;
+ dma-ranges = <0x00000000 0x00000000 0x80000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interconnect-cells = <0>;
+ };
--
2.49.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [PATCH v4 2/4] dt-bindings: soc: spacemit: Add K1 MBUS controller
2025-05-26 14:40 ` Ze Huang
@ 2025-05-27 6:51 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 40+ messages in thread
From: Krzysztof Kozlowski @ 2025-05-27 6:51 UTC (permalink / raw)
To: Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote:
> Some devices on the SpacemiT K1 SoC perform DMA through a memory bus
> (MBUS) that is not their immediate parent in the device tree. This bus
> uses a different address mapping than the CPU.
>
> To express this topology properly, devices are expected to use the
> interconnects with name "dma-mem" to reference the MBUS controller.
I don't get it, sorry. Devices performing DMA through foo-bar should use
dmas property for foo-bar DMA controller. Interconnects is not for that.
>
> Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> ---
> .../bindings/soc/spacemit/spacemit,k1-mbus.yaml | 55 ++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..533cf99dff689cf55a159118c32a676054294ffa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml
> @@ -0,0 +1,55 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-mbus.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SpacemiT Memory Bus controller
> +
> +maintainers:
> + - Ze Huang <huangze9015@gmail.com>
> +
> +description: |
> + On the SpacemiT K1 SoC, some devices do not perform DMA through their
> + immediate parent node in the device tree. Instead, they access memory
> + through a separate memory bus (MBUS) that uses a different address
> + mapping from the CPU.
> +
> + To correctly describe the DMA path, such devices must reference the MBUS
> + controller through an interconnect with the reserved name "dma-mem".
> +
> +properties:
> + compatible:
> + const: spacemit,k1-mbus
> +
> + reg:
> + maxItems: 1
> +
> + dma-ranges:
> + maxItems: 1
> +
> + "#address-cells": true
> +
> + "#size-cells": true
No improvements.
> +
> + "#interconnect-cells":
> + const: 0
This is not a interconnect provider, but DMA controller, according to
youro description.
> +
> +required:
> + - compatible
> + - reg
> + - dma-ranges
> + - "#interconnect-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + dram-controller@0 {
Either dma-controller or memory-controller, decide what is this.
> + compatible = "spacemit,k1-mbus";
> + reg = <0x00000000 0x80000000>;
> + dma-ranges = <0x00000000 0x00000000 0x80000000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
Nothing improved.
> + #interconnect-cells = <0>;
> + };
>
> --
> 2.49.0
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v4 2/4] dt-bindings: soc: spacemit: Add K1 MBUS controller
@ 2025-05-27 6:51 ` Krzysztof Kozlowski
0 siblings, 0 replies; 40+ messages in thread
From: Krzysztof Kozlowski @ 2025-05-27 6:51 UTC (permalink / raw)
To: Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote:
> Some devices on the SpacemiT K1 SoC perform DMA through a memory bus
> (MBUS) that is not their immediate parent in the device tree. This bus
> uses a different address mapping than the CPU.
>
> To express this topology properly, devices are expected to use the
> interconnects with name "dma-mem" to reference the MBUS controller.
I don't get it, sorry. Devices performing DMA through foo-bar should use
dmas property for foo-bar DMA controller. Interconnects is not for that.
>
> Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> ---
> .../bindings/soc/spacemit/spacemit,k1-mbus.yaml | 55 ++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..533cf99dff689cf55a159118c32a676054294ffa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml
> @@ -0,0 +1,55 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-mbus.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SpacemiT Memory Bus controller
> +
> +maintainers:
> + - Ze Huang <huangze9015@gmail.com>
> +
> +description: |
> + On the SpacemiT K1 SoC, some devices do not perform DMA through their
> + immediate parent node in the device tree. Instead, they access memory
> + through a separate memory bus (MBUS) that uses a different address
> + mapping from the CPU.
> +
> + To correctly describe the DMA path, such devices must reference the MBUS
> + controller through an interconnect with the reserved name "dma-mem".
> +
> +properties:
> + compatible:
> + const: spacemit,k1-mbus
> +
> + reg:
> + maxItems: 1
> +
> + dma-ranges:
> + maxItems: 1
> +
> + "#address-cells": true
> +
> + "#size-cells": true
No improvements.
> +
> + "#interconnect-cells":
> + const: 0
This is not a interconnect provider, but DMA controller, according to
youro description.
> +
> +required:
> + - compatible
> + - reg
> + - dma-ranges
> + - "#interconnect-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + dram-controller@0 {
Either dma-controller or memory-controller, decide what is this.
> + compatible = "spacemit,k1-mbus";
> + reg = <0x00000000 0x80000000>;
> + dma-ranges = <0x00000000 0x00000000 0x80000000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
Nothing improved.
> + #interconnect-cells = <0>;
> + };
>
> --
> 2.49.0
>
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v4 2/4] dt-bindings: soc: spacemit: Add K1 MBUS controller
2025-05-27 6:51 ` Krzysztof Kozlowski
@ 2025-05-27 11:13 ` Ze Huang
-1 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-05-27 11:13 UTC (permalink / raw)
To: Krzysztof Kozlowski, Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On Tue, May 27, 2025 at 08:51:19AM +0200, Krzysztof Kozlowski wrote:
> On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote:
> > Some devices on the SpacemiT K1 SoC perform DMA through a memory bus
> > (MBUS) that is not their immediate parent in the device tree. This bus
> > uses a different address mapping than the CPU.
> >
> > To express this topology properly, devices are expected to use the
> > interconnects with name "dma-mem" to reference the MBUS controller.
>
> I don't get it, sorry. Devices performing DMA through foo-bar should use
> dmas property for foo-bar DMA controller. Interconnects is not for that.
>
Hi Krzysztof,
Sorry for not clarifying this earlier - let me provide some context.
The purpose of this node is to describe the address translation used for DMA
device to memory transactions. I’m using the "interconnects" property with the
reserved name "dma-mem" [1] in consumer devices to express this relationship.
The actual translation is handled by the `of_translate_dma_address()` [2].
This support was introduced in the series linked in [3].
This setup is similar to what we see on platforms like Allwinner sun5i,
sun8i-r40, and NVIDIA Tegra. [4][5]
I considered reusing the existing Allwinner MBUS driver and bindings.
However, the Allwinner MBUS includes additional functionality such as
bandwidth monitoring and frequency control - features that are either
absent or undocumented on the SpacemiT K1 SoC.
For this reason, I opted to introduce a minimal binding that only expresses
the required DMA mapping relationship.
Let me know if this makes sense or if you'd like me to adjust further.
Thanks!
Ze
Link: https://elixir.bootlin.com/linux/v6.15/source/Documentation/devicetree/bindings/interconnect/interconnect.txt#L60 [1]
Link: https://elixir.bootlin.com/linux/v6.15/source/drivers/of/address.c#L635 [2]
Link: https://lore.kernel.org/all/cover.f8909884585996f28d97f4ef95efbcab19527dc4.1554108995.git-series.maxime.ripard@bootlin.com/ [3]
Link: https://elixir.bootlin.com/linux/v6.15/source/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi#L328 [4]
Link: https://elixir.bootlin.com/linux/v6.15/source/arch/arm64/boot/dts/nvidia/tegra234.dtsi#L3052 [5]
>
> >
> > Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> > ---
> > .../bindings/soc/spacemit/spacemit,k1-mbus.yaml | 55 ++++++++++++++++++++++
> > 1 file changed, 55 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..533cf99dff689cf55a159118c32a676054294ffa
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml
> > @@ -0,0 +1,55 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-mbus.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: SpacemiT Memory Bus controller
> > +
> > +maintainers:
> > + - Ze Huang <huangze9015@gmail.com>
> > +
> > +description: |
> > + On the SpacemiT K1 SoC, some devices do not perform DMA through their
> > + immediate parent node in the device tree. Instead, they access memory
> > + through a separate memory bus (MBUS) that uses a different address
> > + mapping from the CPU.
> > +
> > + To correctly describe the DMA path, such devices must reference the MBUS
> > + controller through an interconnect with the reserved name "dma-mem".
> > +
> > +properties:
> > + compatible:
> > + const: spacemit,k1-mbus
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + dma-ranges:
> > + maxItems: 1
> > +
> > + "#address-cells": true
> > +
> > + "#size-cells": true
>
> No improvements.
>
>
> > +
> > + "#interconnect-cells":
> > + const: 0
>
> This is not a interconnect provider, but DMA controller, according to
> youro description.
>
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - dma-ranges
> > + - "#interconnect-cells"
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + dram-controller@0 {
>
> Either dma-controller or memory-controller, decide what is this.
>
I think memory-controller is better.
>
> > + compatible = "spacemit,k1-mbus";
> > + reg = <0x00000000 0x80000000>;
> > + dma-ranges = <0x00000000 0x00000000 0x80000000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
>
> Nothing improved.
>
The #address-cells and #size-cells properties are included here to satisfy
`make dt_binding_check` and `make CHECK_DTBS`.
Without them, warnings will be triggered during validation.
dram-controller@0: dma-ranges: [[0], [0], [0], [2147483648]] is too long
>
> > + #interconnect-cells = <0>;
> > + };
> >
> > --
> > 2.49.0
> >
>
>
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v4 2/4] dt-bindings: soc: spacemit: Add K1 MBUS controller
@ 2025-05-27 11:13 ` Ze Huang
0 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-05-27 11:13 UTC (permalink / raw)
To: Krzysztof Kozlowski, Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On Tue, May 27, 2025 at 08:51:19AM +0200, Krzysztof Kozlowski wrote:
> On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote:
> > Some devices on the SpacemiT K1 SoC perform DMA through a memory bus
> > (MBUS) that is not their immediate parent in the device tree. This bus
> > uses a different address mapping than the CPU.
> >
> > To express this topology properly, devices are expected to use the
> > interconnects with name "dma-mem" to reference the MBUS controller.
>
> I don't get it, sorry. Devices performing DMA through foo-bar should use
> dmas property for foo-bar DMA controller. Interconnects is not for that.
>
Hi Krzysztof,
Sorry for not clarifying this earlier - let me provide some context.
The purpose of this node is to describe the address translation used for DMA
device to memory transactions. I’m using the "interconnects" property with the
reserved name "dma-mem" [1] in consumer devices to express this relationship.
The actual translation is handled by the `of_translate_dma_address()` [2].
This support was introduced in the series linked in [3].
This setup is similar to what we see on platforms like Allwinner sun5i,
sun8i-r40, and NVIDIA Tegra. [4][5]
I considered reusing the existing Allwinner MBUS driver and bindings.
However, the Allwinner MBUS includes additional functionality such as
bandwidth monitoring and frequency control - features that are either
absent or undocumented on the SpacemiT K1 SoC.
For this reason, I opted to introduce a minimal binding that only expresses
the required DMA mapping relationship.
Let me know if this makes sense or if you'd like me to adjust further.
Thanks!
Ze
Link: https://elixir.bootlin.com/linux/v6.15/source/Documentation/devicetree/bindings/interconnect/interconnect.txt#L60 [1]
Link: https://elixir.bootlin.com/linux/v6.15/source/drivers/of/address.c#L635 [2]
Link: https://lore.kernel.org/all/cover.f8909884585996f28d97f4ef95efbcab19527dc4.1554108995.git-series.maxime.ripard@bootlin.com/ [3]
Link: https://elixir.bootlin.com/linux/v6.15/source/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi#L328 [4]
Link: https://elixir.bootlin.com/linux/v6.15/source/arch/arm64/boot/dts/nvidia/tegra234.dtsi#L3052 [5]
>
> >
> > Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> > ---
> > .../bindings/soc/spacemit/spacemit,k1-mbus.yaml | 55 ++++++++++++++++++++++
> > 1 file changed, 55 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..533cf99dff689cf55a159118c32a676054294ffa
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml
> > @@ -0,0 +1,55 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-mbus.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: SpacemiT Memory Bus controller
> > +
> > +maintainers:
> > + - Ze Huang <huangze9015@gmail.com>
> > +
> > +description: |
> > + On the SpacemiT K1 SoC, some devices do not perform DMA through their
> > + immediate parent node in the device tree. Instead, they access memory
> > + through a separate memory bus (MBUS) that uses a different address
> > + mapping from the CPU.
> > +
> > + To correctly describe the DMA path, such devices must reference the MBUS
> > + controller through an interconnect with the reserved name "dma-mem".
> > +
> > +properties:
> > + compatible:
> > + const: spacemit,k1-mbus
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + dma-ranges:
> > + maxItems: 1
> > +
> > + "#address-cells": true
> > +
> > + "#size-cells": true
>
> No improvements.
>
>
> > +
> > + "#interconnect-cells":
> > + const: 0
>
> This is not a interconnect provider, but DMA controller, according to
> youro description.
>
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - dma-ranges
> > + - "#interconnect-cells"
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + dram-controller@0 {
>
> Either dma-controller or memory-controller, decide what is this.
>
I think memory-controller is better.
>
> > + compatible = "spacemit,k1-mbus";
> > + reg = <0x00000000 0x80000000>;
> > + dma-ranges = <0x00000000 0x00000000 0x80000000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
>
> Nothing improved.
>
The #address-cells and #size-cells properties are included here to satisfy
`make dt_binding_check` and `make CHECK_DTBS`.
Without them, warnings will be triggered during validation.
dram-controller@0: dma-ranges: [[0], [0], [0], [2147483648]] is too long
>
> > + #interconnect-cells = <0>;
> > + };
> >
> > --
> > 2.49.0
> >
>
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v4 2/4] dt-bindings: soc: spacemit: Add K1 MBUS controller
2025-05-27 11:13 ` Ze Huang
@ 2025-05-27 16:25 ` Rob Herring
-1 siblings, 0 replies; 40+ messages in thread
From: Rob Herring @ 2025-05-27 16:25 UTC (permalink / raw)
To: Ze Huang
Cc: Krzysztof Kozlowski, Greg Kroah-Hartman, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On Tue, May 27, 2025 at 07:13:05PM +0800, Ze Huang wrote:
> On Tue, May 27, 2025 at 08:51:19AM +0200, Krzysztof Kozlowski wrote:
> > On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote:
> > > Some devices on the SpacemiT K1 SoC perform DMA through a memory bus
> > > (MBUS) that is not their immediate parent in the device tree. This bus
> > > uses a different address mapping than the CPU.
> > >
> > > To express this topology properly, devices are expected to use the
> > > interconnects with name "dma-mem" to reference the MBUS controller.
> >
> > I don't get it, sorry. Devices performing DMA through foo-bar should use
> > dmas property for foo-bar DMA controller. Interconnects is not for that.
> >
>
> Hi Krzysztof,
>
> Sorry for not clarifying this earlier - let me provide some context.
>
> The purpose of this node is to describe the address translation used for DMA
> device to memory transactions. I’m using the "interconnects" property with the
> reserved name "dma-mem" [1] in consumer devices to express this relationship.
> The actual translation is handled by the `of_translate_dma_address()` [2].
> This support was introduced in the series linked in [3].
>
> This setup is similar to what we see on platforms like Allwinner sun5i,
> sun8i-r40, and NVIDIA Tegra. [4][5]
>
> I considered reusing the existing Allwinner MBUS driver and bindings.
> However, the Allwinner MBUS includes additional functionality such as
> bandwidth monitoring and frequency control - features that are either
> absent or undocumented on the SpacemiT K1 SoC.
The interconnect binding is for when you have those software controls.
If you only have address translation, then 'dma-ranges' in a parent node
is all you need.
Rob
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 2/4] dt-bindings: soc: spacemit: Add K1 MBUS controller
@ 2025-05-27 16:25 ` Rob Herring
0 siblings, 0 replies; 40+ messages in thread
From: Rob Herring @ 2025-05-27 16:25 UTC (permalink / raw)
To: Ze Huang
Cc: Krzysztof Kozlowski, Greg Kroah-Hartman, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On Tue, May 27, 2025 at 07:13:05PM +0800, Ze Huang wrote:
> On Tue, May 27, 2025 at 08:51:19AM +0200, Krzysztof Kozlowski wrote:
> > On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote:
> > > Some devices on the SpacemiT K1 SoC perform DMA through a memory bus
> > > (MBUS) that is not their immediate parent in the device tree. This bus
> > > uses a different address mapping than the CPU.
> > >
> > > To express this topology properly, devices are expected to use the
> > > interconnects with name "dma-mem" to reference the MBUS controller.
> >
> > I don't get it, sorry. Devices performing DMA through foo-bar should use
> > dmas property for foo-bar DMA controller. Interconnects is not for that.
> >
>
> Hi Krzysztof,
>
> Sorry for not clarifying this earlier - let me provide some context.
>
> The purpose of this node is to describe the address translation used for DMA
> device to memory transactions. I’m using the "interconnects" property with the
> reserved name "dma-mem" [1] in consumer devices to express this relationship.
> The actual translation is handled by the `of_translate_dma_address()` [2].
> This support was introduced in the series linked in [3].
>
> This setup is similar to what we see on platforms like Allwinner sun5i,
> sun8i-r40, and NVIDIA Tegra. [4][5]
>
> I considered reusing the existing Allwinner MBUS driver and bindings.
> However, the Allwinner MBUS includes additional functionality such as
> bandwidth monitoring and frequency control - features that are either
> absent or undocumented on the SpacemiT K1 SoC.
The interconnect binding is for when you have those software controls.
If you only have address translation, then 'dma-ranges' in a parent node
is all you need.
Rob
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 2/4] dt-bindings: soc: spacemit: Add K1 MBUS controller
2025-05-27 16:25 ` Rob Herring
@ 2025-05-27 16:41 ` Ze Huang
-1 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-05-27 16:41 UTC (permalink / raw)
To: Rob Herring
Cc: Krzysztof Kozlowski, Greg Kroah-Hartman, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On 5/28/25 12:25 AM, Rob Herring wrote:
> On Tue, May 27, 2025 at 07:13:05PM +0800, Ze Huang wrote:
>> On Tue, May 27, 2025 at 08:51:19AM +0200, Krzysztof Kozlowski wrote:
>>> On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote:
>>>> Some devices on the SpacemiT K1 SoC perform DMA through a memory bus
>>>> (MBUS) that is not their immediate parent in the device tree. This bus
>>>> uses a different address mapping than the CPU.
>>>>
>>>> To express this topology properly, devices are expected to use the
>>>> interconnects with name "dma-mem" to reference the MBUS controller.
>>> I don't get it, sorry. Devices performing DMA through foo-bar should use
>>> dmas property for foo-bar DMA controller. Interconnects is not for that.
>>>
>> Hi Krzysztof,
>>
>> Sorry for not clarifying this earlier - let me provide some context.
>>
>> The purpose of this node is to describe the address translation used for DMA
>> device to memory transactions. I’m using the "interconnects" property with the
>> reserved name "dma-mem" [1] in consumer devices to express this relationship.
>> The actual translation is handled by the `of_translate_dma_address()` [2].
>> This support was introduced in the series linked in [3].
>>
>> This setup is similar to what we see on platforms like Allwinner sun5i,
>> sun8i-r40, and NVIDIA Tegra. [4][5]
>>
>> I considered reusing the existing Allwinner MBUS driver and bindings.
>> However, the Allwinner MBUS includes additional functionality such as
>> bandwidth monitoring and frequency control - features that are either
>> absent or undocumented on the SpacemiT K1 SoC.
> The interconnect binding is for when you have those software controls.
> If you only have address translation, then 'dma-ranges' in a parent node
> is all you need.
>
> Rob
Different devices on the SoC may have distinct DMA address translations.
A common dma-ranges in the parent node may not represent this accurately.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 2/4] dt-bindings: soc: spacemit: Add K1 MBUS controller
@ 2025-05-27 16:41 ` Ze Huang
0 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-05-27 16:41 UTC (permalink / raw)
To: Rob Herring
Cc: Krzysztof Kozlowski, Greg Kroah-Hartman, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On 5/28/25 12:25 AM, Rob Herring wrote:
> On Tue, May 27, 2025 at 07:13:05PM +0800, Ze Huang wrote:
>> On Tue, May 27, 2025 at 08:51:19AM +0200, Krzysztof Kozlowski wrote:
>>> On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote:
>>>> Some devices on the SpacemiT K1 SoC perform DMA through a memory bus
>>>> (MBUS) that is not their immediate parent in the device tree. This bus
>>>> uses a different address mapping than the CPU.
>>>>
>>>> To express this topology properly, devices are expected to use the
>>>> interconnects with name "dma-mem" to reference the MBUS controller.
>>> I don't get it, sorry. Devices performing DMA through foo-bar should use
>>> dmas property for foo-bar DMA controller. Interconnects is not for that.
>>>
>> Hi Krzysztof,
>>
>> Sorry for not clarifying this earlier - let me provide some context.
>>
>> The purpose of this node is to describe the address translation used for DMA
>> device to memory transactions. I’m using the "interconnects" property with the
>> reserved name "dma-mem" [1] in consumer devices to express this relationship.
>> The actual translation is handled by the `of_translate_dma_address()` [2].
>> This support was introduced in the series linked in [3].
>>
>> This setup is similar to what we see on platforms like Allwinner sun5i,
>> sun8i-r40, and NVIDIA Tegra. [4][5]
>>
>> I considered reusing the existing Allwinner MBUS driver and bindings.
>> However, the Allwinner MBUS includes additional functionality such as
>> bandwidth monitoring and frequency control - features that are either
>> absent or undocumented on the SpacemiT K1 SoC.
> The interconnect binding is for when you have those software controls.
> If you only have address translation, then 'dma-ranges' in a parent node
> is all you need.
>
> Rob
Different devices on the SoC may have distinct DMA address translations.
A common dma-ranges in the parent node may not represent this accurately.
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 2/4] dt-bindings: soc: spacemit: Add K1 MBUS controller
2025-05-27 16:41 ` Ze Huang
@ 2025-05-27 17:12 ` Rob Herring
-1 siblings, 0 replies; 40+ messages in thread
From: Rob Herring @ 2025-05-27 17:12 UTC (permalink / raw)
To: Ze Huang
Cc: Krzysztof Kozlowski, Greg Kroah-Hartman, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On Tue, May 27, 2025 at 11:42 AM Ze Huang <huangze@whut.edu.cn> wrote:
>
> On 5/28/25 12:25 AM, Rob Herring wrote:
> > On Tue, May 27, 2025 at 07:13:05PM +0800, Ze Huang wrote:
> >> On Tue, May 27, 2025 at 08:51:19AM +0200, Krzysztof Kozlowski wrote:
> >>> On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote:
> >>>> Some devices on the SpacemiT K1 SoC perform DMA through a memory bus
> >>>> (MBUS) that is not their immediate parent in the device tree. This bus
> >>>> uses a different address mapping than the CPU.
> >>>>
> >>>> To express this topology properly, devices are expected to use the
> >>>> interconnects with name "dma-mem" to reference the MBUS controller.
> >>> I don't get it, sorry. Devices performing DMA through foo-bar should use
> >>> dmas property for foo-bar DMA controller. Interconnects is not for that.
> >>>
> >> Hi Krzysztof,
> >>
> >> Sorry for not clarifying this earlier - let me provide some context.
> >>
> >> The purpose of this node is to describe the address translation used for DMA
> >> device to memory transactions. I’m using the "interconnects" property with the
> >> reserved name "dma-mem" [1] in consumer devices to express this relationship.
> >> The actual translation is handled by the `of_translate_dma_address()` [2].
> >> This support was introduced in the series linked in [3].
> >>
> >> This setup is similar to what we see on platforms like Allwinner sun5i,
> >> sun8i-r40, and NVIDIA Tegra. [4][5]
> >>
> >> I considered reusing the existing Allwinner MBUS driver and bindings.
> >> However, the Allwinner MBUS includes additional functionality such as
> >> bandwidth monitoring and frequency control - features that are either
> >> absent or undocumented on the SpacemiT K1 SoC.
> > The interconnect binding is for when you have those software controls.
> > If you only have address translation, then 'dma-ranges' in a parent node
> > is all you need.
> >
> > Rob
>
> Different devices on the SoC may have distinct DMA address translations.
> A common dma-ranges in the parent node may not represent this accurately.
That is solved with different parent bus nodes which would be a more
accurate representation of the h/w. If the address translation is
different then, the devices have to be on different buses.
You can use interconnect binding, but you need to accurately describe
the interconnect provider.
Rob
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 2/4] dt-bindings: soc: spacemit: Add K1 MBUS controller
@ 2025-05-27 17:12 ` Rob Herring
0 siblings, 0 replies; 40+ messages in thread
From: Rob Herring @ 2025-05-27 17:12 UTC (permalink / raw)
To: Ze Huang
Cc: Krzysztof Kozlowski, Greg Kroah-Hartman, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On Tue, May 27, 2025 at 11:42 AM Ze Huang <huangze@whut.edu.cn> wrote:
>
> On 5/28/25 12:25 AM, Rob Herring wrote:
> > On Tue, May 27, 2025 at 07:13:05PM +0800, Ze Huang wrote:
> >> On Tue, May 27, 2025 at 08:51:19AM +0200, Krzysztof Kozlowski wrote:
> >>> On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote:
> >>>> Some devices on the SpacemiT K1 SoC perform DMA through a memory bus
> >>>> (MBUS) that is not their immediate parent in the device tree. This bus
> >>>> uses a different address mapping than the CPU.
> >>>>
> >>>> To express this topology properly, devices are expected to use the
> >>>> interconnects with name "dma-mem" to reference the MBUS controller.
> >>> I don't get it, sorry. Devices performing DMA through foo-bar should use
> >>> dmas property for foo-bar DMA controller. Interconnects is not for that.
> >>>
> >> Hi Krzysztof,
> >>
> >> Sorry for not clarifying this earlier - let me provide some context.
> >>
> >> The purpose of this node is to describe the address translation used for DMA
> >> device to memory transactions. I’m using the "interconnects" property with the
> >> reserved name "dma-mem" [1] in consumer devices to express this relationship.
> >> The actual translation is handled by the `of_translate_dma_address()` [2].
> >> This support was introduced in the series linked in [3].
> >>
> >> This setup is similar to what we see on platforms like Allwinner sun5i,
> >> sun8i-r40, and NVIDIA Tegra. [4][5]
> >>
> >> I considered reusing the existing Allwinner MBUS driver and bindings.
> >> However, the Allwinner MBUS includes additional functionality such as
> >> bandwidth monitoring and frequency control - features that are either
> >> absent or undocumented on the SpacemiT K1 SoC.
> > The interconnect binding is for when you have those software controls.
> > If you only have address translation, then 'dma-ranges' in a parent node
> > is all you need.
> >
> > Rob
>
> Different devices on the SoC may have distinct DMA address translations.
> A common dma-ranges in the parent node may not represent this accurately.
That is solved with different parent bus nodes which would be a more
accurate representation of the h/w. If the address translation is
different then, the devices have to be on different buses.
You can use interconnect binding, but you need to accurately describe
the interconnect provider.
Rob
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 2/4] dt-bindings: soc: spacemit: Add K1 MBUS controller
2025-05-26 14:40 ` Ze Huang
@ 2025-05-27 6:54 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 40+ messages in thread
From: Krzysztof Kozlowski @ 2025-05-27 6:54 UTC (permalink / raw)
To: Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote:
> Some devices on the SpacemiT K1 SoC perform DMA through a memory bus
> (MBUS) that is not their immediate parent in the device tree. This bus
> uses a different address mapping than the CPU.
>
> To express this topology properly, devices are expected to use the
> interconnects with name "dma-mem" to reference the MBUS controller.
>
> Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> ---
> .../bindings/soc/spacemit/spacemit,k1-mbus.yaml | 55 ++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml
Memory bus controllers go to /memory-controllers/ directory.
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 2/4] dt-bindings: soc: spacemit: Add K1 MBUS controller
@ 2025-05-27 6:54 ` Krzysztof Kozlowski
0 siblings, 0 replies; 40+ messages in thread
From: Krzysztof Kozlowski @ 2025-05-27 6:54 UTC (permalink / raw)
To: Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote:
> Some devices on the SpacemiT K1 SoC perform DMA through a memory bus
> (MBUS) that is not their immediate parent in the device tree. This bus
> uses a different address mapping than the CPU.
>
> To express this topology properly, devices are expected to use the
> interconnects with name "dma-mem" to reference the MBUS controller.
>
> Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> ---
> .../bindings/soc/spacemit/spacemit,k1-mbus.yaml | 55 ++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml
Memory bus controllers go to /memory-controllers/ directory.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 2/4] dt-bindings: soc: spacemit: Add K1 MBUS controller
2025-05-27 6:54 ` Krzysztof Kozlowski
@ 2025-05-27 11:15 ` Ze Huang
-1 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-05-27 11:15 UTC (permalink / raw)
To: Krzysztof Kozlowski, Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On Tue, May 27, 2025 at 08:54:42AM +0200, Krzysztof Kozlowski wrote:
> On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote:
> > Some devices on the SpacemiT K1 SoC perform DMA through a memory bus
> > (MBUS) that is not their immediate parent in the device tree. This bus
> > uses a different address mapping than the CPU.
> >
> > To express this topology properly, devices are expected to use the
> > interconnects with name "dma-mem" to reference the MBUS controller.
> >
> > Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> > ---
> > .../bindings/soc/spacemit/spacemit,k1-mbus.yaml | 55 ++++++++++++++++++++++
> > 1 file changed, 55 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml
>
> Memory bus controllers go to /memory-controllers/ directory.
>
> Best regards,
> Krzysztof
OK
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 2/4] dt-bindings: soc: spacemit: Add K1 MBUS controller
@ 2025-05-27 11:15 ` Ze Huang
0 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-05-27 11:15 UTC (permalink / raw)
To: Krzysztof Kozlowski, Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb, devicetree, linux-riscv, spacemit, linux-kernel
On Tue, May 27, 2025 at 08:54:42AM +0200, Krzysztof Kozlowski wrote:
> On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote:
> > Some devices on the SpacemiT K1 SoC perform DMA through a memory bus
> > (MBUS) that is not their immediate parent in the device tree. This bus
> > uses a different address mapping than the CPU.
> >
> > To express this topology properly, devices are expected to use the
> > interconnects with name "dma-mem" to reference the MBUS controller.
> >
> > Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> > ---
> > .../bindings/soc/spacemit/spacemit,k1-mbus.yaml | 55 ++++++++++++++++++++++
> > 1 file changed, 55 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml
>
> Memory bus controllers go to /memory-controllers/ directory.
>
> Best regards,
> Krzysztof
OK
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v4 3/4] usb: dwc3: add generic driver to support flattened DT
2025-05-26 14:40 ` Ze Huang
@ 2025-05-26 14:40 ` Ze Huang
-1 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-05-26 14:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: linux-usb, devicetree, linux-riscv, spacemit, linux-kernel,
Ze Huang
To support flattened dwc3 dt model and drop the glue layer, introduce the
`dwc3-generic` driver. This enables direct binding of the DWC3 core driver
and offers an alternative to the existing glue driver `dwc3-of-simple`.
Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
drivers/usb/dwc3/Kconfig | 9 ++
drivers/usb/dwc3/Makefile | 1 +
drivers/usb/dwc3/dwc3-generic-plat.c | 189 +++++++++++++++++++++++++++++++++++
3 files changed, 199 insertions(+)
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 310d182e10b50b253d7e5a51674806e6ec442a2a..082627f39c9726ee4e0c5f966c5bc454f5541c9a 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -118,6 +118,15 @@ config USB_DWC3_OF_SIMPLE
Currently supports Xilinx and Qualcomm DWC USB3 IP.
Say 'Y' or 'M' if you have one such device.
+config USB_DWC3_GENERIC_PLAT
+ tristate "DWC3 Generic Platform Driver"
+ depends on OF && COMMON_CLK
+ default USB_DWC3
+ help
+ Support USB3 functionality in simple SoC integrations.
+ Currently supports SpacemiT DWC USB3 IP.
+ Say 'Y' or 'M' if you have one such device.
+
config USB_DWC3_ST
tristate "STMicroelectronics Platforms"
depends on (ARCH_STI || COMPILE_TEST) && OF
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 830e6c9e5fe073c1f662ce34b6a4a2da34c407a2..96469e48ff9d189cc8d0b65e65424eae2158bcfe 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o
obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o
obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o
obj-$(CONFIG_USB_DWC3_RTK) += dwc3-rtk.o
+obj-$(CONFIG_USB_DWC3_GENERIC_PLAT) += dwc3-generic-plat.o
diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
new file mode 100644
index 0000000000000000000000000000000000000000..8ff4626d324c40ecb52e115832c803fed7d38354
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-generic-plat.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * dwc3-generic-plat.c - DesignWare USB3 generic platform driver
+ *
+ * Copyright (C) 2025 Ze Huang <huangze9015@gmail.com>
+ *
+ * Inspired by dwc3-qcom.c and dwc3-of-simple.c
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include "glue.h"
+
+struct dwc3_generic {
+ struct device *dev;
+ struct dwc3 dwc;
+ struct clk_bulk_data *clks;
+ int num_clocks;
+ struct reset_control *resets;
+};
+
+static int dwc3_generic_probe(struct platform_device *pdev)
+{
+ struct dwc3_probe_data probe_data = {};
+ struct device *dev = &pdev->dev;
+ struct dwc3_generic *dwc3;
+ struct resource *res;
+ int ret;
+
+ dwc3 = devm_kzalloc(dev, sizeof(*dwc3), GFP_KERNEL);
+ if (!dwc3)
+ return -ENOMEM;
+
+ dwc3->dev = dev;
+
+ platform_set_drvdata(pdev, dwc3);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "missing memory resource\n");
+ return -ENODEV;
+ }
+
+ dwc3->resets = of_reset_control_array_get_optional_exclusive(dev->of_node);
+ if (IS_ERR(dwc3->resets))
+ return dev_err_probe(dev, PTR_ERR(dwc3->resets), "failed to get reset\n");
+
+ ret = reset_control_assert(dwc3->resets);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to assert reset\n");
+
+ usleep_range(10, 1000);
+
+ ret = reset_control_deassert(dwc3->resets);
+ if (ret) {
+ dev_err(dev, "failed to deassert reset\n");
+ goto reset_assert;
+ }
+
+ ret = clk_bulk_get_all(dwc3->dev, &dwc3->clks);
+ if (ret < 0) {
+ dev_err(dev, "failed to get clocks\n");
+ goto reset_assert;
+ }
+
+ dwc3->num_clocks = ret;
+
+ ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks);
+ if (ret) {
+ dev_err(dev, "failed to enable clocks\n");
+ goto reset_assert;
+ }
+
+ dwc3->dwc.dev = dev;
+ probe_data.dwc = &dwc3->dwc;
+ probe_data.res = res;
+ probe_data.ignore_clocks_and_resets = true;
+ ret = dwc3_core_probe(&probe_data);
+ if (ret) {
+ dev_err(dev, "failed to register DWC3 Core\n");
+ goto clk_disable;
+ }
+
+ return 0;
+
+clk_disable:
+ clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
+ clk_bulk_put_all(dwc3->num_clocks, dwc3->clks);
+
+reset_assert:
+ reset_control_assert(dwc3->resets);
+
+ return ret;
+}
+
+static void dwc3_generic_remove(struct platform_device *pdev)
+{
+ struct dwc3_generic *dwc3 = platform_get_drvdata(pdev);
+
+ dwc3_core_remove(&dwc3->dwc);
+
+ clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
+ clk_bulk_put_all(dwc3->num_clocks, dwc3->clks);
+
+ reset_control_assert(dwc3->resets);
+}
+
+static int __maybe_unused dwc3_generic_suspend(struct device *dev)
+{
+ struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
+ int ret;
+
+ ret = dwc3_pm_suspend(&dwc3->dwc);
+ if (ret)
+ return ret;
+
+ clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
+
+ return 0;
+}
+
+static int __maybe_unused dwc3_generic_resume(struct device *dev)
+{
+ struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks);
+ if (ret)
+ return ret;
+
+ ret = dwc3_pm_resume(&dwc3->dwc);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int __maybe_unused dwc3_generic_runtime_suspend(struct device *dev)
+{
+ struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
+
+ return dwc3_runtime_suspend(&dwc3->dwc);
+}
+
+static int __maybe_unused dwc3_generic_runtime_resume(struct device *dev)
+{
+ struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
+
+ return dwc3_runtime_resume(&dwc3->dwc);
+}
+
+static int __maybe_unused dwc3_generic_runtime_idle(struct device *dev)
+{
+ struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
+
+ return dwc3_runtime_idle(&dwc3->dwc);
+}
+
+static const struct dev_pm_ops dwc3_generic_dev_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(dwc3_generic_suspend, dwc3_generic_resume)
+ SET_RUNTIME_PM_OPS(dwc3_generic_runtime_suspend, dwc3_generic_runtime_resume,
+ dwc3_generic_runtime_idle)
+};
+
+static const struct of_device_id dwc3_generic_of_match[] = {
+ { .compatible = "spacemit,k1-dwc3", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dwc3_generic_of_match);
+
+static struct platform_driver dwc3_generic_driver = {
+ .probe = dwc3_generic_probe,
+ .remove = dwc3_generic_remove,
+ .driver = {
+ .name = "dwc3-generic-plat",
+ .of_match_table = dwc3_generic_of_match,
+#ifdef CONFIG_PM_SLEEP
+ .pm = &dwc3_generic_dev_pm_ops,
+#endif /* CONFIG_PM_SLEEP */
+ },
+};
+module_platform_driver(dwc3_generic_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("DesignWare USB3 generic platform driver");
--
2.49.0
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^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH v4 3/4] usb: dwc3: add generic driver to support flattened DT
@ 2025-05-26 14:40 ` Ze Huang
0 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-05-26 14:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: linux-usb, devicetree, linux-riscv, spacemit, linux-kernel,
Ze Huang
To support flattened dwc3 dt model and drop the glue layer, introduce the
`dwc3-generic` driver. This enables direct binding of the DWC3 core driver
and offers an alternative to the existing glue driver `dwc3-of-simple`.
Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
drivers/usb/dwc3/Kconfig | 9 ++
drivers/usb/dwc3/Makefile | 1 +
drivers/usb/dwc3/dwc3-generic-plat.c | 189 +++++++++++++++++++++++++++++++++++
3 files changed, 199 insertions(+)
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 310d182e10b50b253d7e5a51674806e6ec442a2a..082627f39c9726ee4e0c5f966c5bc454f5541c9a 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -118,6 +118,15 @@ config USB_DWC3_OF_SIMPLE
Currently supports Xilinx and Qualcomm DWC USB3 IP.
Say 'Y' or 'M' if you have one such device.
+config USB_DWC3_GENERIC_PLAT
+ tristate "DWC3 Generic Platform Driver"
+ depends on OF && COMMON_CLK
+ default USB_DWC3
+ help
+ Support USB3 functionality in simple SoC integrations.
+ Currently supports SpacemiT DWC USB3 IP.
+ Say 'Y' or 'M' if you have one such device.
+
config USB_DWC3_ST
tristate "STMicroelectronics Platforms"
depends on (ARCH_STI || COMPILE_TEST) && OF
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 830e6c9e5fe073c1f662ce34b6a4a2da34c407a2..96469e48ff9d189cc8d0b65e65424eae2158bcfe 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o
obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o
obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o
obj-$(CONFIG_USB_DWC3_RTK) += dwc3-rtk.o
+obj-$(CONFIG_USB_DWC3_GENERIC_PLAT) += dwc3-generic-plat.o
diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
new file mode 100644
index 0000000000000000000000000000000000000000..8ff4626d324c40ecb52e115832c803fed7d38354
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-generic-plat.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * dwc3-generic-plat.c - DesignWare USB3 generic platform driver
+ *
+ * Copyright (C) 2025 Ze Huang <huangze9015@gmail.com>
+ *
+ * Inspired by dwc3-qcom.c and dwc3-of-simple.c
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include "glue.h"
+
+struct dwc3_generic {
+ struct device *dev;
+ struct dwc3 dwc;
+ struct clk_bulk_data *clks;
+ int num_clocks;
+ struct reset_control *resets;
+};
+
+static int dwc3_generic_probe(struct platform_device *pdev)
+{
+ struct dwc3_probe_data probe_data = {};
+ struct device *dev = &pdev->dev;
+ struct dwc3_generic *dwc3;
+ struct resource *res;
+ int ret;
+
+ dwc3 = devm_kzalloc(dev, sizeof(*dwc3), GFP_KERNEL);
+ if (!dwc3)
+ return -ENOMEM;
+
+ dwc3->dev = dev;
+
+ platform_set_drvdata(pdev, dwc3);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "missing memory resource\n");
+ return -ENODEV;
+ }
+
+ dwc3->resets = of_reset_control_array_get_optional_exclusive(dev->of_node);
+ if (IS_ERR(dwc3->resets))
+ return dev_err_probe(dev, PTR_ERR(dwc3->resets), "failed to get reset\n");
+
+ ret = reset_control_assert(dwc3->resets);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to assert reset\n");
+
+ usleep_range(10, 1000);
+
+ ret = reset_control_deassert(dwc3->resets);
+ if (ret) {
+ dev_err(dev, "failed to deassert reset\n");
+ goto reset_assert;
+ }
+
+ ret = clk_bulk_get_all(dwc3->dev, &dwc3->clks);
+ if (ret < 0) {
+ dev_err(dev, "failed to get clocks\n");
+ goto reset_assert;
+ }
+
+ dwc3->num_clocks = ret;
+
+ ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks);
+ if (ret) {
+ dev_err(dev, "failed to enable clocks\n");
+ goto reset_assert;
+ }
+
+ dwc3->dwc.dev = dev;
+ probe_data.dwc = &dwc3->dwc;
+ probe_data.res = res;
+ probe_data.ignore_clocks_and_resets = true;
+ ret = dwc3_core_probe(&probe_data);
+ if (ret) {
+ dev_err(dev, "failed to register DWC3 Core\n");
+ goto clk_disable;
+ }
+
+ return 0;
+
+clk_disable:
+ clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
+ clk_bulk_put_all(dwc3->num_clocks, dwc3->clks);
+
+reset_assert:
+ reset_control_assert(dwc3->resets);
+
+ return ret;
+}
+
+static void dwc3_generic_remove(struct platform_device *pdev)
+{
+ struct dwc3_generic *dwc3 = platform_get_drvdata(pdev);
+
+ dwc3_core_remove(&dwc3->dwc);
+
+ clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
+ clk_bulk_put_all(dwc3->num_clocks, dwc3->clks);
+
+ reset_control_assert(dwc3->resets);
+}
+
+static int __maybe_unused dwc3_generic_suspend(struct device *dev)
+{
+ struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
+ int ret;
+
+ ret = dwc3_pm_suspend(&dwc3->dwc);
+ if (ret)
+ return ret;
+
+ clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
+
+ return 0;
+}
+
+static int __maybe_unused dwc3_generic_resume(struct device *dev)
+{
+ struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks);
+ if (ret)
+ return ret;
+
+ ret = dwc3_pm_resume(&dwc3->dwc);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int __maybe_unused dwc3_generic_runtime_suspend(struct device *dev)
+{
+ struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
+
+ return dwc3_runtime_suspend(&dwc3->dwc);
+}
+
+static int __maybe_unused dwc3_generic_runtime_resume(struct device *dev)
+{
+ struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
+
+ return dwc3_runtime_resume(&dwc3->dwc);
+}
+
+static int __maybe_unused dwc3_generic_runtime_idle(struct device *dev)
+{
+ struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
+
+ return dwc3_runtime_idle(&dwc3->dwc);
+}
+
+static const struct dev_pm_ops dwc3_generic_dev_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(dwc3_generic_suspend, dwc3_generic_resume)
+ SET_RUNTIME_PM_OPS(dwc3_generic_runtime_suspend, dwc3_generic_runtime_resume,
+ dwc3_generic_runtime_idle)
+};
+
+static const struct of_device_id dwc3_generic_of_match[] = {
+ { .compatible = "spacemit,k1-dwc3", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dwc3_generic_of_match);
+
+static struct platform_driver dwc3_generic_driver = {
+ .probe = dwc3_generic_probe,
+ .remove = dwc3_generic_remove,
+ .driver = {
+ .name = "dwc3-generic-plat",
+ .of_match_table = dwc3_generic_of_match,
+#ifdef CONFIG_PM_SLEEP
+ .pm = &dwc3_generic_dev_pm_ops,
+#endif /* CONFIG_PM_SLEEP */
+ },
+};
+module_platform_driver(dwc3_generic_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("DesignWare USB3 generic platform driver");
--
2.49.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [PATCH v4 3/4] usb: dwc3: add generic driver to support flattened DT
2025-05-26 14:40 ` Ze Huang
@ 2025-06-03 1:20 ` Thinh Nguyen
-1 siblings, 0 replies; 40+ messages in thread
From: Thinh Nguyen @ 2025-06-03 1:20 UTC (permalink / raw)
To: Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
linux-kernel@vger.kernel.org
On Mon, May 26, 2025, Ze Huang wrote:
> To support flattened dwc3 dt model and drop the glue layer, introduce the
> `dwc3-generic` driver. This enables direct binding of the DWC3 core driver
> and offers an alternative to the existing glue driver `dwc3-of-simple`.
>
> Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> ---
> drivers/usb/dwc3/Kconfig | 9 ++
> drivers/usb/dwc3/Makefile | 1 +
> drivers/usb/dwc3/dwc3-generic-plat.c | 189 +++++++++++++++++++++++++++++++++++
> 3 files changed, 199 insertions(+)
>
> diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
> index 310d182e10b50b253d7e5a51674806e6ec442a2a..082627f39c9726ee4e0c5f966c5bc454f5541c9a 100644
> --- a/drivers/usb/dwc3/Kconfig
> +++ b/drivers/usb/dwc3/Kconfig
> @@ -118,6 +118,15 @@ config USB_DWC3_OF_SIMPLE
> Currently supports Xilinx and Qualcomm DWC USB3 IP.
> Say 'Y' or 'M' if you have one such device.
>
> +config USB_DWC3_GENERIC_PLAT
> + tristate "DWC3 Generic Platform Driver"
> + depends on OF && COMMON_CLK
> + default USB_DWC3
> + help
> + Support USB3 functionality in simple SoC integrations.
> + Currently supports SpacemiT DWC USB3 IP.
> + Say 'Y' or 'M' if you have one such device.
> +
> config USB_DWC3_ST
> tristate "STMicroelectronics Platforms"
> depends on (ARCH_STI || COMPILE_TEST) && OF
> diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
> index 830e6c9e5fe073c1f662ce34b6a4a2da34c407a2..96469e48ff9d189cc8d0b65e65424eae2158bcfe 100644
> --- a/drivers/usb/dwc3/Makefile
> +++ b/drivers/usb/dwc3/Makefile
> @@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o
> obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o
> obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o
> obj-$(CONFIG_USB_DWC3_RTK) += dwc3-rtk.o
> +obj-$(CONFIG_USB_DWC3_GENERIC_PLAT) += dwc3-generic-plat.o
> diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..8ff4626d324c40ecb52e115832c803fed7d38354
> --- /dev/null
> +++ b/drivers/usb/dwc3/dwc3-generic-plat.c
> @@ -0,0 +1,189 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * dwc3-generic-plat.c - DesignWare USB3 generic platform driver
> + *
> + * Copyright (C) 2025 Ze Huang <huangze9015@gmail.com>
> + *
> + * Inspired by dwc3-qcom.c and dwc3-of-simple.c
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +#include "glue.h"
> +
> +struct dwc3_generic {
> + struct device *dev;
> + struct dwc3 dwc;
> + struct clk_bulk_data *clks;
> + int num_clocks;
> + struct reset_control *resets;
> +};
> +
> +static int dwc3_generic_probe(struct platform_device *pdev)
> +{
> + struct dwc3_probe_data probe_data = {};
> + struct device *dev = &pdev->dev;
> + struct dwc3_generic *dwc3;
> + struct resource *res;
> + int ret;
> +
> + dwc3 = devm_kzalloc(dev, sizeof(*dwc3), GFP_KERNEL);
> + if (!dwc3)
> + return -ENOMEM;
> +
> + dwc3->dev = dev;
> +
> + platform_set_drvdata(pdev, dwc3);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(&pdev->dev, "missing memory resource\n");
> + return -ENODEV;
> + }
> +
> + dwc3->resets = of_reset_control_array_get_optional_exclusive(dev->of_node);
> + if (IS_ERR(dwc3->resets))
> + return dev_err_probe(dev, PTR_ERR(dwc3->resets), "failed to get reset\n");
> +
> + ret = reset_control_assert(dwc3->resets);
> + if (ret)
> + return dev_err_probe(dev, ret, "failed to assert reset\n");
> +
> + usleep_range(10, 1000);
> +
> + ret = reset_control_deassert(dwc3->resets);
> + if (ret) {
> + dev_err(dev, "failed to deassert reset\n");
> + goto reset_assert;
> + }
> +
> + ret = clk_bulk_get_all(dwc3->dev, &dwc3->clks);
> + if (ret < 0) {
> + dev_err(dev, "failed to get clocks\n");
> + goto reset_assert;
> + }
> +
> + dwc3->num_clocks = ret;
> +
> + ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks);
> + if (ret) {
> + dev_err(dev, "failed to enable clocks\n");
> + goto reset_assert;
> + }
> +
> + dwc3->dwc.dev = dev;
> + probe_data.dwc = &dwc3->dwc;
> + probe_data.res = res;
> + probe_data.ignore_clocks_and_resets = true;
> + ret = dwc3_core_probe(&probe_data);
> + if (ret) {
> + dev_err(dev, "failed to register DWC3 Core\n");
> + goto clk_disable;
> + }
> +
> + return 0;
> +
> +clk_disable:
> + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> + clk_bulk_put_all(dwc3->num_clocks, dwc3->clks);
> +
> +reset_assert:
> + reset_control_assert(dwc3->resets);
> +
> + return ret;
> +}
> +
> +static void dwc3_generic_remove(struct platform_device *pdev)
> +{
> + struct dwc3_generic *dwc3 = platform_get_drvdata(pdev);
> +
> + dwc3_core_remove(&dwc3->dwc);
> +
> + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> + clk_bulk_put_all(dwc3->num_clocks, dwc3->clks);
> +
> + reset_control_assert(dwc3->resets);
> +}
> +
> +static int __maybe_unused dwc3_generic_suspend(struct device *dev)
We shouldn't need __maybe_unused attr with the new PM macros.
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> + int ret;
> +
> + ret = dwc3_pm_suspend(&dwc3->dwc);
> + if (ret)
> + return ret;
> +
> + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> +
> + return 0;
> +}
> +
> +static int __maybe_unused dwc3_generic_resume(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> + int ret;
> +
> + ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks);
> + if (ret)
> + return ret;
> +
> + ret = dwc3_pm_resume(&dwc3->dwc);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int __maybe_unused dwc3_generic_runtime_suspend(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> +
> + return dwc3_runtime_suspend(&dwc3->dwc);
> +}
> +
> +static int __maybe_unused dwc3_generic_runtime_resume(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> +
> + return dwc3_runtime_resume(&dwc3->dwc);
> +}
> +
> +static int __maybe_unused dwc3_generic_runtime_idle(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> +
> + return dwc3_runtime_idle(&dwc3->dwc);
> +}
> +
> +static const struct dev_pm_ops dwc3_generic_dev_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(dwc3_generic_suspend, dwc3_generic_resume)
> + SET_RUNTIME_PM_OPS(dwc3_generic_runtime_suspend, dwc3_generic_runtime_resume,
> + dwc3_generic_runtime_idle)
> +};
> +
> +static const struct of_device_id dwc3_generic_of_match[] = {
> + { .compatible = "spacemit,k1-dwc3", },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, dwc3_generic_of_match);
> +
> +static struct platform_driver dwc3_generic_driver = {
> + .probe = dwc3_generic_probe,
> + .remove = dwc3_generic_remove,
> + .driver = {
> + .name = "dwc3-generic-plat",
> + .of_match_table = dwc3_generic_of_match,
> +#ifdef CONFIG_PM_SLEEP
Use the new pm_ptr/pm_sleep_ptr.
Thanks,
Thinh
> + .pm = &dwc3_generic_dev_pm_ops,
> +#endif /* CONFIG_PM_SLEEP */
> + },
> +};
> +module_platform_driver(dwc3_generic_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("DesignWare USB3 generic platform driver");
>
> --
> 2.49.0
>
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^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v4 3/4] usb: dwc3: add generic driver to support flattened DT
@ 2025-06-03 1:20 ` Thinh Nguyen
0 siblings, 0 replies; 40+ messages in thread
From: Thinh Nguyen @ 2025-06-03 1:20 UTC (permalink / raw)
To: Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
linux-kernel@vger.kernel.org
On Mon, May 26, 2025, Ze Huang wrote:
> To support flattened dwc3 dt model and drop the glue layer, introduce the
> `dwc3-generic` driver. This enables direct binding of the DWC3 core driver
> and offers an alternative to the existing glue driver `dwc3-of-simple`.
>
> Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> ---
> drivers/usb/dwc3/Kconfig | 9 ++
> drivers/usb/dwc3/Makefile | 1 +
> drivers/usb/dwc3/dwc3-generic-plat.c | 189 +++++++++++++++++++++++++++++++++++
> 3 files changed, 199 insertions(+)
>
> diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
> index 310d182e10b50b253d7e5a51674806e6ec442a2a..082627f39c9726ee4e0c5f966c5bc454f5541c9a 100644
> --- a/drivers/usb/dwc3/Kconfig
> +++ b/drivers/usb/dwc3/Kconfig
> @@ -118,6 +118,15 @@ config USB_DWC3_OF_SIMPLE
> Currently supports Xilinx and Qualcomm DWC USB3 IP.
> Say 'Y' or 'M' if you have one such device.
>
> +config USB_DWC3_GENERIC_PLAT
> + tristate "DWC3 Generic Platform Driver"
> + depends on OF && COMMON_CLK
> + default USB_DWC3
> + help
> + Support USB3 functionality in simple SoC integrations.
> + Currently supports SpacemiT DWC USB3 IP.
> + Say 'Y' or 'M' if you have one such device.
> +
> config USB_DWC3_ST
> tristate "STMicroelectronics Platforms"
> depends on (ARCH_STI || COMPILE_TEST) && OF
> diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
> index 830e6c9e5fe073c1f662ce34b6a4a2da34c407a2..96469e48ff9d189cc8d0b65e65424eae2158bcfe 100644
> --- a/drivers/usb/dwc3/Makefile
> +++ b/drivers/usb/dwc3/Makefile
> @@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o
> obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o
> obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o
> obj-$(CONFIG_USB_DWC3_RTK) += dwc3-rtk.o
> +obj-$(CONFIG_USB_DWC3_GENERIC_PLAT) += dwc3-generic-plat.o
> diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..8ff4626d324c40ecb52e115832c803fed7d38354
> --- /dev/null
> +++ b/drivers/usb/dwc3/dwc3-generic-plat.c
> @@ -0,0 +1,189 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * dwc3-generic-plat.c - DesignWare USB3 generic platform driver
> + *
> + * Copyright (C) 2025 Ze Huang <huangze9015@gmail.com>
> + *
> + * Inspired by dwc3-qcom.c and dwc3-of-simple.c
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +#include "glue.h"
> +
> +struct dwc3_generic {
> + struct device *dev;
> + struct dwc3 dwc;
> + struct clk_bulk_data *clks;
> + int num_clocks;
> + struct reset_control *resets;
> +};
> +
> +static int dwc3_generic_probe(struct platform_device *pdev)
> +{
> + struct dwc3_probe_data probe_data = {};
> + struct device *dev = &pdev->dev;
> + struct dwc3_generic *dwc3;
> + struct resource *res;
> + int ret;
> +
> + dwc3 = devm_kzalloc(dev, sizeof(*dwc3), GFP_KERNEL);
> + if (!dwc3)
> + return -ENOMEM;
> +
> + dwc3->dev = dev;
> +
> + platform_set_drvdata(pdev, dwc3);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(&pdev->dev, "missing memory resource\n");
> + return -ENODEV;
> + }
> +
> + dwc3->resets = of_reset_control_array_get_optional_exclusive(dev->of_node);
> + if (IS_ERR(dwc3->resets))
> + return dev_err_probe(dev, PTR_ERR(dwc3->resets), "failed to get reset\n");
> +
> + ret = reset_control_assert(dwc3->resets);
> + if (ret)
> + return dev_err_probe(dev, ret, "failed to assert reset\n");
> +
> + usleep_range(10, 1000);
> +
> + ret = reset_control_deassert(dwc3->resets);
> + if (ret) {
> + dev_err(dev, "failed to deassert reset\n");
> + goto reset_assert;
> + }
> +
> + ret = clk_bulk_get_all(dwc3->dev, &dwc3->clks);
> + if (ret < 0) {
> + dev_err(dev, "failed to get clocks\n");
> + goto reset_assert;
> + }
> +
> + dwc3->num_clocks = ret;
> +
> + ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks);
> + if (ret) {
> + dev_err(dev, "failed to enable clocks\n");
> + goto reset_assert;
> + }
> +
> + dwc3->dwc.dev = dev;
> + probe_data.dwc = &dwc3->dwc;
> + probe_data.res = res;
> + probe_data.ignore_clocks_and_resets = true;
> + ret = dwc3_core_probe(&probe_data);
> + if (ret) {
> + dev_err(dev, "failed to register DWC3 Core\n");
> + goto clk_disable;
> + }
> +
> + return 0;
> +
> +clk_disable:
> + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> + clk_bulk_put_all(dwc3->num_clocks, dwc3->clks);
> +
> +reset_assert:
> + reset_control_assert(dwc3->resets);
> +
> + return ret;
> +}
> +
> +static void dwc3_generic_remove(struct platform_device *pdev)
> +{
> + struct dwc3_generic *dwc3 = platform_get_drvdata(pdev);
> +
> + dwc3_core_remove(&dwc3->dwc);
> +
> + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> + clk_bulk_put_all(dwc3->num_clocks, dwc3->clks);
> +
> + reset_control_assert(dwc3->resets);
> +}
> +
> +static int __maybe_unused dwc3_generic_suspend(struct device *dev)
We shouldn't need __maybe_unused attr with the new PM macros.
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> + int ret;
> +
> + ret = dwc3_pm_suspend(&dwc3->dwc);
> + if (ret)
> + return ret;
> +
> + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> +
> + return 0;
> +}
> +
> +static int __maybe_unused dwc3_generic_resume(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> + int ret;
> +
> + ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks);
> + if (ret)
> + return ret;
> +
> + ret = dwc3_pm_resume(&dwc3->dwc);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int __maybe_unused dwc3_generic_runtime_suspend(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> +
> + return dwc3_runtime_suspend(&dwc3->dwc);
> +}
> +
> +static int __maybe_unused dwc3_generic_runtime_resume(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> +
> + return dwc3_runtime_resume(&dwc3->dwc);
> +}
> +
> +static int __maybe_unused dwc3_generic_runtime_idle(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> +
> + return dwc3_runtime_idle(&dwc3->dwc);
> +}
> +
> +static const struct dev_pm_ops dwc3_generic_dev_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(dwc3_generic_suspend, dwc3_generic_resume)
> + SET_RUNTIME_PM_OPS(dwc3_generic_runtime_suspend, dwc3_generic_runtime_resume,
> + dwc3_generic_runtime_idle)
> +};
> +
> +static const struct of_device_id dwc3_generic_of_match[] = {
> + { .compatible = "spacemit,k1-dwc3", },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, dwc3_generic_of_match);
> +
> +static struct platform_driver dwc3_generic_driver = {
> + .probe = dwc3_generic_probe,
> + .remove = dwc3_generic_remove,
> + .driver = {
> + .name = "dwc3-generic-plat",
> + .of_match_table = dwc3_generic_of_match,
> +#ifdef CONFIG_PM_SLEEP
Use the new pm_ptr/pm_sleep_ptr.
Thanks,
Thinh
> + .pm = &dwc3_generic_dev_pm_ops,
> +#endif /* CONFIG_PM_SLEEP */
> + },
> +};
> +module_platform_driver(dwc3_generic_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("DesignWare USB3 generic platform driver");
>
> --
> 2.49.0
>
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v4 3/4] usb: dwc3: add generic driver to support flattened DT
2025-06-03 1:20 ` Thinh Nguyen
@ 2025-06-03 2:51 ` Ze Huang
-1 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-06-03 2:51 UTC (permalink / raw)
To: Thinh Nguyen, Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
linux-kernel@vger.kernel.org
On Tue, Jun 03, 2025 at 01:20:35AM +0000, Thinh Nguyen wrote:
> On Mon, May 26, 2025, Ze Huang wrote:
> > To support flattened dwc3 dt model and drop the glue layer, introduce the
> > `dwc3-generic` driver. This enables direct binding of the DWC3 core driver
> > and offers an alternative to the existing glue driver `dwc3-of-simple`.
> >
> > Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> > ---
> > drivers/usb/dwc3/Kconfig | 9 ++
> > drivers/usb/dwc3/Makefile | 1 +
> > drivers/usb/dwc3/dwc3-generic-plat.c | 189 +++++++++++++++++++++++++++++++++++
> > 3 files changed, 199 insertions(+)
> >
> > diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
> > index 310d182e10b50b253d7e5a51674806e6ec442a2a..082627f39c9726ee4e0c5f966c5bc454f5541c9a 100644
> > --- a/drivers/usb/dwc3/Kconfig
> > +++ b/drivers/usb/dwc3/Kconfig
> > @@ -118,6 +118,15 @@ config USB_DWC3_OF_SIMPLE
> > Currently supports Xilinx and Qualcomm DWC USB3 IP.
> > Say 'Y' or 'M' if you have one such device.
> >
> > +config USB_DWC3_GENERIC_PLAT
> > + tristate "DWC3 Generic Platform Driver"
> > + depends on OF && COMMON_CLK
> > + default USB_DWC3
> > + help
> > + Support USB3 functionality in simple SoC integrations.
> > + Currently supports SpacemiT DWC USB3 IP.
> > + Say 'Y' or 'M' if you have one such device.
> > +
> > config USB_DWC3_ST
> > tristate "STMicroelectronics Platforms"
> > depends on (ARCH_STI || COMPILE_TEST) && OF
> > diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
> > index 830e6c9e5fe073c1f662ce34b6a4a2da34c407a2..96469e48ff9d189cc8d0b65e65424eae2158bcfe 100644
> > --- a/drivers/usb/dwc3/Makefile
> > +++ b/drivers/usb/dwc3/Makefile
> > @@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o
> > obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o
> > obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o
> > obj-$(CONFIG_USB_DWC3_RTK) += dwc3-rtk.o
> > +obj-$(CONFIG_USB_DWC3_GENERIC_PLAT) += dwc3-generic-plat.o
> > diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
...
> > +
> > +static void dwc3_generic_remove(struct platform_device *pdev)
> > +{
> > + struct dwc3_generic *dwc3 = platform_get_drvdata(pdev);
> > +
> > + dwc3_core_remove(&dwc3->dwc);
> > +
> > + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> > + clk_bulk_put_all(dwc3->num_clocks, dwc3->clks);
> > +
> > + reset_control_assert(dwc3->resets);
> > +}
> > +
> > +static int __maybe_unused dwc3_generic_suspend(struct device *dev)
>
> We shouldn't need __maybe_unused attr with the new PM macros.
>
Will drop these attr
> > +{
> > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > + int ret;
> > +
> > + ret = dwc3_pm_suspend(&dwc3->dwc);
> > + if (ret)
> > + return ret;
> > +
> > + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> > +
> > + return 0;
> > +}
> > +
> > +static int __maybe_unused dwc3_generic_resume(struct device *dev)
> > +{
> > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > + int ret;
> > +
> > + ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks);
> > + if (ret)
> > + return ret;
> > +
> > + ret = dwc3_pm_resume(&dwc3->dwc);
> > + if (ret)
> > + return ret;
> > +
> > + return 0;
> > +}
> > +
> > +static int __maybe_unused dwc3_generic_runtime_suspend(struct device *dev)
> > +{
> > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > +
> > + return dwc3_runtime_suspend(&dwc3->dwc);
> > +}
> > +
> > +static int __maybe_unused dwc3_generic_runtime_resume(struct device *dev)
> > +{
> > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > +
> > + return dwc3_runtime_resume(&dwc3->dwc);
> > +}
> > +
> > +static int __maybe_unused dwc3_generic_runtime_idle(struct device *dev)
> > +{
> > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > +
> > + return dwc3_runtime_idle(&dwc3->dwc);
> > +}
> > +
> > +static const struct dev_pm_ops dwc3_generic_dev_pm_ops = {
> > + SET_SYSTEM_SLEEP_PM_OPS(dwc3_generic_suspend, dwc3_generic_resume)
> > + SET_RUNTIME_PM_OPS(dwc3_generic_runtime_suspend, dwc3_generic_runtime_resume,
> > + dwc3_generic_runtime_idle)
> > +};
> > +
> > +static const struct of_device_id dwc3_generic_of_match[] = {
> > + { .compatible = "spacemit,k1-dwc3", },
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, dwc3_generic_of_match);
> > +
> > +static struct platform_driver dwc3_generic_driver = {
> > + .probe = dwc3_generic_probe,
> > + .remove = dwc3_generic_remove,
> > + .driver = {
> > + .name = "dwc3-generic-plat",
> > + .of_match_table = dwc3_generic_of_match,
> > +#ifdef CONFIG_PM_SLEEP
>
> Use the new pm_ptr/pm_sleep_ptr.
>
Thanks for pointing it out, I missed this part. I will fix it
> Thanks,
> Thinh
>
> > + .pm = &dwc3_generic_dev_pm_ops,
> > +#endif /* CONFIG_PM_SLEEP */
> > + },
> > +};
> > +module_platform_driver(dwc3_generic_driver);
> > +
> > +MODULE_LICENSE("GPL");
> > +MODULE_DESCRIPTION("DesignWare USB3 generic platform driver");
> >
> > --
> > 2.49.0
> >
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^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v4 3/4] usb: dwc3: add generic driver to support flattened DT
@ 2025-06-03 2:51 ` Ze Huang
0 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-06-03 2:51 UTC (permalink / raw)
To: Thinh Nguyen, Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
linux-kernel@vger.kernel.org
On Tue, Jun 03, 2025 at 01:20:35AM +0000, Thinh Nguyen wrote:
> On Mon, May 26, 2025, Ze Huang wrote:
> > To support flattened dwc3 dt model and drop the glue layer, introduce the
> > `dwc3-generic` driver. This enables direct binding of the DWC3 core driver
> > and offers an alternative to the existing glue driver `dwc3-of-simple`.
> >
> > Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> > ---
> > drivers/usb/dwc3/Kconfig | 9 ++
> > drivers/usb/dwc3/Makefile | 1 +
> > drivers/usb/dwc3/dwc3-generic-plat.c | 189 +++++++++++++++++++++++++++++++++++
> > 3 files changed, 199 insertions(+)
> >
> > diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
> > index 310d182e10b50b253d7e5a51674806e6ec442a2a..082627f39c9726ee4e0c5f966c5bc454f5541c9a 100644
> > --- a/drivers/usb/dwc3/Kconfig
> > +++ b/drivers/usb/dwc3/Kconfig
> > @@ -118,6 +118,15 @@ config USB_DWC3_OF_SIMPLE
> > Currently supports Xilinx and Qualcomm DWC USB3 IP.
> > Say 'Y' or 'M' if you have one such device.
> >
> > +config USB_DWC3_GENERIC_PLAT
> > + tristate "DWC3 Generic Platform Driver"
> > + depends on OF && COMMON_CLK
> > + default USB_DWC3
> > + help
> > + Support USB3 functionality in simple SoC integrations.
> > + Currently supports SpacemiT DWC USB3 IP.
> > + Say 'Y' or 'M' if you have one such device.
> > +
> > config USB_DWC3_ST
> > tristate "STMicroelectronics Platforms"
> > depends on (ARCH_STI || COMPILE_TEST) && OF
> > diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
> > index 830e6c9e5fe073c1f662ce34b6a4a2da34c407a2..96469e48ff9d189cc8d0b65e65424eae2158bcfe 100644
> > --- a/drivers/usb/dwc3/Makefile
> > +++ b/drivers/usb/dwc3/Makefile
> > @@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o
> > obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o
> > obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o
> > obj-$(CONFIG_USB_DWC3_RTK) += dwc3-rtk.o
> > +obj-$(CONFIG_USB_DWC3_GENERIC_PLAT) += dwc3-generic-plat.o
> > diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
...
> > +
> > +static void dwc3_generic_remove(struct platform_device *pdev)
> > +{
> > + struct dwc3_generic *dwc3 = platform_get_drvdata(pdev);
> > +
> > + dwc3_core_remove(&dwc3->dwc);
> > +
> > + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> > + clk_bulk_put_all(dwc3->num_clocks, dwc3->clks);
> > +
> > + reset_control_assert(dwc3->resets);
> > +}
> > +
> > +static int __maybe_unused dwc3_generic_suspend(struct device *dev)
>
> We shouldn't need __maybe_unused attr with the new PM macros.
>
Will drop these attr
> > +{
> > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > + int ret;
> > +
> > + ret = dwc3_pm_suspend(&dwc3->dwc);
> > + if (ret)
> > + return ret;
> > +
> > + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> > +
> > + return 0;
> > +}
> > +
> > +static int __maybe_unused dwc3_generic_resume(struct device *dev)
> > +{
> > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > + int ret;
> > +
> > + ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks);
> > + if (ret)
> > + return ret;
> > +
> > + ret = dwc3_pm_resume(&dwc3->dwc);
> > + if (ret)
> > + return ret;
> > +
> > + return 0;
> > +}
> > +
> > +static int __maybe_unused dwc3_generic_runtime_suspend(struct device *dev)
> > +{
> > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > +
> > + return dwc3_runtime_suspend(&dwc3->dwc);
> > +}
> > +
> > +static int __maybe_unused dwc3_generic_runtime_resume(struct device *dev)
> > +{
> > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > +
> > + return dwc3_runtime_resume(&dwc3->dwc);
> > +}
> > +
> > +static int __maybe_unused dwc3_generic_runtime_idle(struct device *dev)
> > +{
> > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > +
> > + return dwc3_runtime_idle(&dwc3->dwc);
> > +}
> > +
> > +static const struct dev_pm_ops dwc3_generic_dev_pm_ops = {
> > + SET_SYSTEM_SLEEP_PM_OPS(dwc3_generic_suspend, dwc3_generic_resume)
> > + SET_RUNTIME_PM_OPS(dwc3_generic_runtime_suspend, dwc3_generic_runtime_resume,
> > + dwc3_generic_runtime_idle)
> > +};
> > +
> > +static const struct of_device_id dwc3_generic_of_match[] = {
> > + { .compatible = "spacemit,k1-dwc3", },
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, dwc3_generic_of_match);
> > +
> > +static struct platform_driver dwc3_generic_driver = {
> > + .probe = dwc3_generic_probe,
> > + .remove = dwc3_generic_remove,
> > + .driver = {
> > + .name = "dwc3-generic-plat",
> > + .of_match_table = dwc3_generic_of_match,
> > +#ifdef CONFIG_PM_SLEEP
>
> Use the new pm_ptr/pm_sleep_ptr.
>
Thanks for pointing it out, I missed this part. I will fix it
> Thanks,
> Thinh
>
> > + .pm = &dwc3_generic_dev_pm_ops,
> > +#endif /* CONFIG_PM_SLEEP */
> > + },
> > +};
> > +module_platform_driver(dwc3_generic_driver);
> > +
> > +MODULE_LICENSE("GPL");
> > +MODULE_DESCRIPTION("DesignWare USB3 generic platform driver");
> >
> > --
> > 2.49.0
> >
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v4 3/4] usb: dwc3: add generic driver to support flattened DT
2025-06-03 2:51 ` Ze Huang
@ 2025-07-04 2:10 ` Frank Li
-1 siblings, 0 replies; 40+ messages in thread
From: Frank Li @ 2025-07-04 2:10 UTC (permalink / raw)
To: Ze Huang
Cc: Thinh Nguyen, Greg Kroah-Hartman, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Yixun Lan, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
linux-kernel@vger.kernel.org
On Tue, Jun 03, 2025 at 10:51:27AM +0800, Ze Huang wrote:
> On Tue, Jun 03, 2025 at 01:20:35AM +0000, Thinh Nguyen wrote:
> > On Mon, May 26, 2025, Ze Huang wrote:
> > > To support flattened dwc3 dt model and drop the glue layer, introduce the
> > > `dwc3-generic` driver. This enables direct binding of the DWC3 core driver
> > > and offers an alternative to the existing glue driver `dwc3-of-simple`.
> > >
> > > Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> > > ---
Any progress on this patch? If you have not time, I can continue work on
this one.
Frank Li
> > > drivers/usb/dwc3/Kconfig | 9 ++
> > > drivers/usb/dwc3/Makefile | 1 +
> > > drivers/usb/dwc3/dwc3-generic-plat.c | 189 +++++++++++++++++++++++++++++++++++
> > > 3 files changed, 199 insertions(+)
> > >
> > > diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
> > > index 310d182e10b50b253d7e5a51674806e6ec442a2a..082627f39c9726ee4e0c5f966c5bc454f5541c9a 100644
> > > --- a/drivers/usb/dwc3/Kconfig
> > > +++ b/drivers/usb/dwc3/Kconfig
> > > @@ -118,6 +118,15 @@ config USB_DWC3_OF_SIMPLE
> > > Currently supports Xilinx and Qualcomm DWC USB3 IP.
> > > Say 'Y' or 'M' if you have one such device.
> > >
> > > +config USB_DWC3_GENERIC_PLAT
> > > + tristate "DWC3 Generic Platform Driver"
> > > + depends on OF && COMMON_CLK
> > > + default USB_DWC3
> > > + help
> > > + Support USB3 functionality in simple SoC integrations.
> > > + Currently supports SpacemiT DWC USB3 IP.
> > > + Say 'Y' or 'M' if you have one such device.
> > > +
> > > config USB_DWC3_ST
> > > tristate "STMicroelectronics Platforms"
> > > depends on (ARCH_STI || COMPILE_TEST) && OF
> > > diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
> > > index 830e6c9e5fe073c1f662ce34b6a4a2da34c407a2..96469e48ff9d189cc8d0b65e65424eae2158bcfe 100644
> > > --- a/drivers/usb/dwc3/Makefile
> > > +++ b/drivers/usb/dwc3/Makefile
> > > @@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o
> > > obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o
> > > obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o
> > > obj-$(CONFIG_USB_DWC3_RTK) += dwc3-rtk.o
> > > +obj-$(CONFIG_USB_DWC3_GENERIC_PLAT) += dwc3-generic-plat.o
> > > diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
> ...
> > > +
> > > +static void dwc3_generic_remove(struct platform_device *pdev)
> > > +{
> > > + struct dwc3_generic *dwc3 = platform_get_drvdata(pdev);
> > > +
> > > + dwc3_core_remove(&dwc3->dwc);
> > > +
> > > + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> > > + clk_bulk_put_all(dwc3->num_clocks, dwc3->clks);
> > > +
> > > + reset_control_assert(dwc3->resets);
> > > +}
> > > +
> > > +static int __maybe_unused dwc3_generic_suspend(struct device *dev)
> >
> > We shouldn't need __maybe_unused attr with the new PM macros.
> >
>
> Will drop these attr
>
> > > +{
> > > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > > + int ret;
> > > +
> > > + ret = dwc3_pm_suspend(&dwc3->dwc);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int __maybe_unused dwc3_generic_resume(struct device *dev)
> > > +{
> > > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > > + int ret;
> > > +
> > > + ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + ret = dwc3_pm_resume(&dwc3->dwc);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int __maybe_unused dwc3_generic_runtime_suspend(struct device *dev)
> > > +{
> > > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > > +
> > > + return dwc3_runtime_suspend(&dwc3->dwc);
> > > +}
> > > +
> > > +static int __maybe_unused dwc3_generic_runtime_resume(struct device *dev)
> > > +{
> > > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > > +
> > > + return dwc3_runtime_resume(&dwc3->dwc);
> > > +}
> > > +
> > > +static int __maybe_unused dwc3_generic_runtime_idle(struct device *dev)
> > > +{
> > > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > > +
> > > + return dwc3_runtime_idle(&dwc3->dwc);
> > > +}
> > > +
> > > +static const struct dev_pm_ops dwc3_generic_dev_pm_ops = {
> > > + SET_SYSTEM_SLEEP_PM_OPS(dwc3_generic_suspend, dwc3_generic_resume)
> > > + SET_RUNTIME_PM_OPS(dwc3_generic_runtime_suspend, dwc3_generic_runtime_resume,
> > > + dwc3_generic_runtime_idle)
> > > +};
> > > +
> > > +static const struct of_device_id dwc3_generic_of_match[] = {
> > > + { .compatible = "spacemit,k1-dwc3", },
> > > + { /* sentinel */ }
> > > +};
> > > +MODULE_DEVICE_TABLE(of, dwc3_generic_of_match);
> > > +
> > > +static struct platform_driver dwc3_generic_driver = {
> > > + .probe = dwc3_generic_probe,
> > > + .remove = dwc3_generic_remove,
> > > + .driver = {
> > > + .name = "dwc3-generic-plat",
> > > + .of_match_table = dwc3_generic_of_match,
> > > +#ifdef CONFIG_PM_SLEEP
> >
> > Use the new pm_ptr/pm_sleep_ptr.
> >
>
> Thanks for pointing it out, I missed this part. I will fix it
>
> > Thanks,
> > Thinh
> >
> > > + .pm = &dwc3_generic_dev_pm_ops,
> > > +#endif /* CONFIG_PM_SLEEP */
> > > + },
> > > +};
> > > +module_platform_driver(dwc3_generic_driver);
> > > +
> > > +MODULE_LICENSE("GPL");
> > > +MODULE_DESCRIPTION("DesignWare USB3 generic platform driver");
> > >
> > > --
> > > 2.49.0
> > >
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v4 3/4] usb: dwc3: add generic driver to support flattened DT
@ 2025-07-04 2:10 ` Frank Li
0 siblings, 0 replies; 40+ messages in thread
From: Frank Li @ 2025-07-04 2:10 UTC (permalink / raw)
To: Ze Huang
Cc: Thinh Nguyen, Greg Kroah-Hartman, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Yixun Lan, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
linux-kernel@vger.kernel.org
On Tue, Jun 03, 2025 at 10:51:27AM +0800, Ze Huang wrote:
> On Tue, Jun 03, 2025 at 01:20:35AM +0000, Thinh Nguyen wrote:
> > On Mon, May 26, 2025, Ze Huang wrote:
> > > To support flattened dwc3 dt model and drop the glue layer, introduce the
> > > `dwc3-generic` driver. This enables direct binding of the DWC3 core driver
> > > and offers an alternative to the existing glue driver `dwc3-of-simple`.
> > >
> > > Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> > > ---
Any progress on this patch? If you have not time, I can continue work on
this one.
Frank Li
> > > drivers/usb/dwc3/Kconfig | 9 ++
> > > drivers/usb/dwc3/Makefile | 1 +
> > > drivers/usb/dwc3/dwc3-generic-plat.c | 189 +++++++++++++++++++++++++++++++++++
> > > 3 files changed, 199 insertions(+)
> > >
> > > diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
> > > index 310d182e10b50b253d7e5a51674806e6ec442a2a..082627f39c9726ee4e0c5f966c5bc454f5541c9a 100644
> > > --- a/drivers/usb/dwc3/Kconfig
> > > +++ b/drivers/usb/dwc3/Kconfig
> > > @@ -118,6 +118,15 @@ config USB_DWC3_OF_SIMPLE
> > > Currently supports Xilinx and Qualcomm DWC USB3 IP.
> > > Say 'Y' or 'M' if you have one such device.
> > >
> > > +config USB_DWC3_GENERIC_PLAT
> > > + tristate "DWC3 Generic Platform Driver"
> > > + depends on OF && COMMON_CLK
> > > + default USB_DWC3
> > > + help
> > > + Support USB3 functionality in simple SoC integrations.
> > > + Currently supports SpacemiT DWC USB3 IP.
> > > + Say 'Y' or 'M' if you have one such device.
> > > +
> > > config USB_DWC3_ST
> > > tristate "STMicroelectronics Platforms"
> > > depends on (ARCH_STI || COMPILE_TEST) && OF
> > > diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
> > > index 830e6c9e5fe073c1f662ce34b6a4a2da34c407a2..96469e48ff9d189cc8d0b65e65424eae2158bcfe 100644
> > > --- a/drivers/usb/dwc3/Makefile
> > > +++ b/drivers/usb/dwc3/Makefile
> > > @@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o
> > > obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o
> > > obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o
> > > obj-$(CONFIG_USB_DWC3_RTK) += dwc3-rtk.o
> > > +obj-$(CONFIG_USB_DWC3_GENERIC_PLAT) += dwc3-generic-plat.o
> > > diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
> ...
> > > +
> > > +static void dwc3_generic_remove(struct platform_device *pdev)
> > > +{
> > > + struct dwc3_generic *dwc3 = platform_get_drvdata(pdev);
> > > +
> > > + dwc3_core_remove(&dwc3->dwc);
> > > +
> > > + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> > > + clk_bulk_put_all(dwc3->num_clocks, dwc3->clks);
> > > +
> > > + reset_control_assert(dwc3->resets);
> > > +}
> > > +
> > > +static int __maybe_unused dwc3_generic_suspend(struct device *dev)
> >
> > We shouldn't need __maybe_unused attr with the new PM macros.
> >
>
> Will drop these attr
>
> > > +{
> > > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > > + int ret;
> > > +
> > > + ret = dwc3_pm_suspend(&dwc3->dwc);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int __maybe_unused dwc3_generic_resume(struct device *dev)
> > > +{
> > > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > > + int ret;
> > > +
> > > + ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + ret = dwc3_pm_resume(&dwc3->dwc);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int __maybe_unused dwc3_generic_runtime_suspend(struct device *dev)
> > > +{
> > > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > > +
> > > + return dwc3_runtime_suspend(&dwc3->dwc);
> > > +}
> > > +
> > > +static int __maybe_unused dwc3_generic_runtime_resume(struct device *dev)
> > > +{
> > > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > > +
> > > + return dwc3_runtime_resume(&dwc3->dwc);
> > > +}
> > > +
> > > +static int __maybe_unused dwc3_generic_runtime_idle(struct device *dev)
> > > +{
> > > + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> > > +
> > > + return dwc3_runtime_idle(&dwc3->dwc);
> > > +}
> > > +
> > > +static const struct dev_pm_ops dwc3_generic_dev_pm_ops = {
> > > + SET_SYSTEM_SLEEP_PM_OPS(dwc3_generic_suspend, dwc3_generic_resume)
> > > + SET_RUNTIME_PM_OPS(dwc3_generic_runtime_suspend, dwc3_generic_runtime_resume,
> > > + dwc3_generic_runtime_idle)
> > > +};
> > > +
> > > +static const struct of_device_id dwc3_generic_of_match[] = {
> > > + { .compatible = "spacemit,k1-dwc3", },
> > > + { /* sentinel */ }
> > > +};
> > > +MODULE_DEVICE_TABLE(of, dwc3_generic_of_match);
> > > +
> > > +static struct platform_driver dwc3_generic_driver = {
> > > + .probe = dwc3_generic_probe,
> > > + .remove = dwc3_generic_remove,
> > > + .driver = {
> > > + .name = "dwc3-generic-plat",
> > > + .of_match_table = dwc3_generic_of_match,
> > > +#ifdef CONFIG_PM_SLEEP
> >
> > Use the new pm_ptr/pm_sleep_ptr.
> >
>
> Thanks for pointing it out, I missed this part. I will fix it
>
> > Thanks,
> > Thinh
> >
> > > + .pm = &dwc3_generic_dev_pm_ops,
> > > +#endif /* CONFIG_PM_SLEEP */
> > > + },
> > > +};
> > > +module_platform_driver(dwc3_generic_driver);
> > > +
> > > +MODULE_LICENSE("GPL");
> > > +MODULE_DESCRIPTION("DesignWare USB3 generic platform driver");
> > >
> > > --
> > > 2.49.0
> > >
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v4 3/4] usb: dwc3: add generic driver to support flattened DT
2025-07-04 2:10 ` Frank Li
@ 2025-07-04 2:41 ` Ze Huang
-1 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-07-04 2:41 UTC (permalink / raw)
To: Frank Li, Ze Huang
Cc: Thinh Nguyen, Greg Kroah-Hartman, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Yixun Lan, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
linux-kernel@vger.kernel.org
On Thu, Jul 03, 2025 at 10:10:26PM -0400, Frank Li wrote:
> On Tue, Jun 03, 2025 at 10:51:27AM +0800, Ze Huang wrote:
> > On Tue, Jun 03, 2025 at 01:20:35AM +0000, Thinh Nguyen wrote:
> > > On Mon, May 26, 2025, Ze Huang wrote:
> > > > To support flattened dwc3 dt model and drop the glue layer, introduce the
> > > > `dwc3-generic` driver. This enables direct binding of the DWC3 core driver
> > > > and offers an alternative to the existing glue driver `dwc3-of-simple`.
> > > >
> > > > Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> > > > ---
>
> Any progress on this patch? If you have not time, I can continue work on
> this one.
Hi Frank,
I was planning to submit everything together for full functionality, but since
Alex's PHY work[1] is almost done, I'll send out the USB generic driver part
separately first.
Link: https://lore.kernel.org/all/5084a99a-9140-4c4f-9873-f5478f48a49d@ieee.org/ [1]
>
> Frank Li
>
Thanks,
Ze
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 3/4] usb: dwc3: add generic driver to support flattened DT
@ 2025-07-04 2:41 ` Ze Huang
0 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-07-04 2:41 UTC (permalink / raw)
To: Frank Li, Ze Huang
Cc: Thinh Nguyen, Greg Kroah-Hartman, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Yixun Lan, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
linux-kernel@vger.kernel.org
On Thu, Jul 03, 2025 at 10:10:26PM -0400, Frank Li wrote:
> On Tue, Jun 03, 2025 at 10:51:27AM +0800, Ze Huang wrote:
> > On Tue, Jun 03, 2025 at 01:20:35AM +0000, Thinh Nguyen wrote:
> > > On Mon, May 26, 2025, Ze Huang wrote:
> > > > To support flattened dwc3 dt model and drop the glue layer, introduce the
> > > > `dwc3-generic` driver. This enables direct binding of the DWC3 core driver
> > > > and offers an alternative to the existing glue driver `dwc3-of-simple`.
> > > >
> > > > Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> > > > ---
>
> Any progress on this patch? If you have not time, I can continue work on
> this one.
Hi Frank,
I was planning to submit everything together for full functionality, but since
Alex's PHY work[1] is almost done, I'll send out the USB generic driver part
separately first.
Link: https://lore.kernel.org/all/5084a99a-9140-4c4f-9873-f5478f48a49d@ieee.org/ [1]
>
> Frank Li
>
Thanks,
Ze
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 3/4] usb: dwc3: add generic driver to support flattened DT
2025-05-26 14:40 ` Ze Huang
@ 2025-06-05 13:34 ` Yixun Lan
-1 siblings, 0 replies; 40+ messages in thread
From: Yixun Lan @ 2025-06-05 13:34 UTC (permalink / raw)
To: Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thinh Nguyen, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, linux-usb, devicetree,
linux-riscv, spacemit, linux-kernel
Hi Ze,
On 22:40 Mon 26 May , Ze Huang wrote:
> To support flattened dwc3 dt model and drop the glue layer, introduce the
> `dwc3-generic` driver. This enables direct binding of the DWC3 core driver
> and offers an alternative to the existing glue driver `dwc3-of-simple`.
>
> Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> ---
> drivers/usb/dwc3/Kconfig | 9 ++
> drivers/usb/dwc3/Makefile | 1 +
> drivers/usb/dwc3/dwc3-generic-plat.c | 189 +++++++++++++++++++++++++++++++++++
> 3 files changed, 199 insertions(+)
>
> diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
> index 310d182e10b50b253d7e5a51674806e6ec442a2a..082627f39c9726ee4e0c5f966c5bc454f5541c9a 100644
> --- a/drivers/usb/dwc3/Kconfig
> +++ b/drivers/usb/dwc3/Kconfig
> @@ -118,6 +118,15 @@ config USB_DWC3_OF_SIMPLE
> Currently supports Xilinx and Qualcomm DWC USB3 IP.
> Say 'Y' or 'M' if you have one such device.
>
> +config USB_DWC3_GENERIC_PLAT
> + tristate "DWC3 Generic Platform Driver"
> + depends on OF && COMMON_CLK
> + default USB_DWC3
> + help
> + Support USB3 functionality in simple SoC integrations.
> + Currently supports SpacemiT DWC USB3 IP.
> + Say 'Y' or 'M' if you have one such device.
> +
> config USB_DWC3_ST
> tristate "STMicroelectronics Platforms"
> depends on (ARCH_STI || COMPILE_TEST) && OF
> diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
> index 830e6c9e5fe073c1f662ce34b6a4a2da34c407a2..96469e48ff9d189cc8d0b65e65424eae2158bcfe 100644
> --- a/drivers/usb/dwc3/Makefile
> +++ b/drivers/usb/dwc3/Makefile
> @@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o
> obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o
> obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o
> obj-$(CONFIG_USB_DWC3_RTK) += dwc3-rtk.o
> +obj-$(CONFIG_USB_DWC3_GENERIC_PLAT) += dwc3-generic-plat.o
> diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..8ff4626d324c40ecb52e115832c803fed7d38354
> --- /dev/null
> +++ b/drivers/usb/dwc3/dwc3-generic-plat.c
> @@ -0,0 +1,189 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * dwc3-generic-plat.c - DesignWare USB3 generic platform driver
> + *
> + * Copyright (C) 2025 Ze Huang <huangze9015@gmail.com>
> + *
> + * Inspired by dwc3-qcom.c and dwc3-of-simple.c
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +#include "glue.h"
> +
> +struct dwc3_generic {
> + struct device *dev;
> + struct dwc3 dwc;
> + struct clk_bulk_data *clks;
> + int num_clocks;
> + struct reset_control *resets;
> +};
> +
> +static int dwc3_generic_probe(struct platform_device *pdev)
> +{
> + struct dwc3_probe_data probe_data = {};
> + struct device *dev = &pdev->dev;
> + struct dwc3_generic *dwc3;
> + struct resource *res;
> + int ret;
> +
> + dwc3 = devm_kzalloc(dev, sizeof(*dwc3), GFP_KERNEL);
> + if (!dwc3)
> + return -ENOMEM;
> +
> + dwc3->dev = dev;
> +
> + platform_set_drvdata(pdev, dwc3);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(&pdev->dev, "missing memory resource\n");
> + return -ENODEV;
> + }
> +
> + dwc3->resets = of_reset_control_array_get_optional_exclusive(dev->of_node);
> + if (IS_ERR(dwc3->resets))
> + return dev_err_probe(dev, PTR_ERR(dwc3->resets), "failed to get reset\n");
> +
> + ret = reset_control_assert(dwc3->resets);
> + if (ret)
> + return dev_err_probe(dev, ret, "failed to assert reset\n");
> +
> + usleep_range(10, 1000);
> +
> + ret = reset_control_deassert(dwc3->resets);
> + if (ret) {
> + dev_err(dev, "failed to deassert reset\n");
> + goto reset_assert;
> + }
> +
> + ret = clk_bulk_get_all(dwc3->dev, &dwc3->clks);
can you check if able to use devres api for reset/clock here?
(functions start devm_ prefix)
> + if (ret < 0) {
> + dev_err(dev, "failed to get clocks\nt");
> + goto reset_assert;
> + }
> +
> + dwc3->num_clocks = ret;
> +
> + ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks);
> + if (ret) {
> + dev_err(dev, "failed to enable clocks\n");
> + goto reset_assert;
> + }
> +
> + dwc3->dwc.dev = dev;
> + probe_data.dwc = &dwc3->dwc;
> + probe_data.res = res;
> + probe_data.ignore_clocks_and_resets = true;
> + ret = dwc3_core_probe(&probe_data);
> + if (ret) {
> + dev_err(dev, "failed to register DWC3 Core\n");
> + goto clk_disable;
> + }
> +
> + return 0;
> +
> +clk_disable:
> + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> + clk_bulk_put_all(dwc3->num_clocks, dwc3->clks);
> +
> +reset_assert:
> + reset_control_assert(dwc3->resets);
> +
> + return ret;
> +}
> +
> +static void dwc3_generic_remove(struct platform_device *pdev)
> +{
> + struct dwc3_generic *dwc3 = platform_get_drvdata(pdev);
> +
> + dwc3_core_remove(&dwc3->dwc);
> +
> + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> + clk_bulk_put_all(dwc3->num_clocks, dwc3->clks);
> +
> + reset_control_assert(dwc3->resets);
> +}
> +
> +static int __maybe_unused dwc3_generic_suspend(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> + int ret;
> +
> + ret = dwc3_pm_suspend(&dwc3->dwc);
> + if (ret)
> + return ret;
> +
> + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> +
> + return 0;
> +}
> +
> +static int __maybe_unused dwc3_generic_resume(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> + int ret;
> +
> + ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks);
> + if (ret)
> + return ret;
> +
> + ret = dwc3_pm_resume(&dwc3->dwc);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int __maybe_unused dwc3_generic_runtime_suspend(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> +
> + return dwc3_runtime_suspend(&dwc3->dwc);
> +}
> +
> +static int __maybe_unused dwc3_generic_runtime_resume(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> +
> + return dwc3_runtime_resume(&dwc3->dwc);
> +}
> +
> +static int __maybe_unused dwc3_generic_runtime_idle(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> +
> + return dwc3_runtime_idle(&dwc3->dwc);
> +}
> +
> +static const struct dev_pm_ops dwc3_generic_dev_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(dwc3_generic_suspend, dwc3_generic_resume)
> + SET_RUNTIME_PM_OPS(dwc3_generic_runtime_suspend, dwc3_generic_runtime_resume,
> + dwc3_generic_runtime_idle)
> +};
> +
> +static const struct of_device_id dwc3_generic_of_match[] = {
> + { .compatible = "spacemit,k1-dwc3", },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, dwc3_generic_of_match);
> +
> +static struct platform_driver dwc3_generic_driver = {
> + .probe = dwc3_generic_probe,
> + .remove = dwc3_generic_remove,
> + .driver = {
> + .name = "dwc3-generic-plat",
> + .of_match_table = dwc3_generic_of_match,
> +#ifdef CONFIG_PM_SLEEP
> + .pm = &dwc3_generic_dev_pm_ops,
> +#endif /* CONFIG_PM_SLEEP */
> + },
> +};
> +module_platform_driver(dwc3_generic_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("DesignWare USB3 generic platform driver");
>
> --
> 2.49.0
>
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v4 3/4] usb: dwc3: add generic driver to support flattened DT
@ 2025-06-05 13:34 ` Yixun Lan
0 siblings, 0 replies; 40+ messages in thread
From: Yixun Lan @ 2025-06-05 13:34 UTC (permalink / raw)
To: Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thinh Nguyen, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, linux-usb, devicetree,
linux-riscv, spacemit, linux-kernel
Hi Ze,
On 22:40 Mon 26 May , Ze Huang wrote:
> To support flattened dwc3 dt model and drop the glue layer, introduce the
> `dwc3-generic` driver. This enables direct binding of the DWC3 core driver
> and offers an alternative to the existing glue driver `dwc3-of-simple`.
>
> Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> ---
> drivers/usb/dwc3/Kconfig | 9 ++
> drivers/usb/dwc3/Makefile | 1 +
> drivers/usb/dwc3/dwc3-generic-plat.c | 189 +++++++++++++++++++++++++++++++++++
> 3 files changed, 199 insertions(+)
>
> diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
> index 310d182e10b50b253d7e5a51674806e6ec442a2a..082627f39c9726ee4e0c5f966c5bc454f5541c9a 100644
> --- a/drivers/usb/dwc3/Kconfig
> +++ b/drivers/usb/dwc3/Kconfig
> @@ -118,6 +118,15 @@ config USB_DWC3_OF_SIMPLE
> Currently supports Xilinx and Qualcomm DWC USB3 IP.
> Say 'Y' or 'M' if you have one such device.
>
> +config USB_DWC3_GENERIC_PLAT
> + tristate "DWC3 Generic Platform Driver"
> + depends on OF && COMMON_CLK
> + default USB_DWC3
> + help
> + Support USB3 functionality in simple SoC integrations.
> + Currently supports SpacemiT DWC USB3 IP.
> + Say 'Y' or 'M' if you have one such device.
> +
> config USB_DWC3_ST
> tristate "STMicroelectronics Platforms"
> depends on (ARCH_STI || COMPILE_TEST) && OF
> diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
> index 830e6c9e5fe073c1f662ce34b6a4a2da34c407a2..96469e48ff9d189cc8d0b65e65424eae2158bcfe 100644
> --- a/drivers/usb/dwc3/Makefile
> +++ b/drivers/usb/dwc3/Makefile
> @@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o
> obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o
> obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o
> obj-$(CONFIG_USB_DWC3_RTK) += dwc3-rtk.o
> +obj-$(CONFIG_USB_DWC3_GENERIC_PLAT) += dwc3-generic-plat.o
> diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..8ff4626d324c40ecb52e115832c803fed7d38354
> --- /dev/null
> +++ b/drivers/usb/dwc3/dwc3-generic-plat.c
> @@ -0,0 +1,189 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * dwc3-generic-plat.c - DesignWare USB3 generic platform driver
> + *
> + * Copyright (C) 2025 Ze Huang <huangze9015@gmail.com>
> + *
> + * Inspired by dwc3-qcom.c and dwc3-of-simple.c
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +#include "glue.h"
> +
> +struct dwc3_generic {
> + struct device *dev;
> + struct dwc3 dwc;
> + struct clk_bulk_data *clks;
> + int num_clocks;
> + struct reset_control *resets;
> +};
> +
> +static int dwc3_generic_probe(struct platform_device *pdev)
> +{
> + struct dwc3_probe_data probe_data = {};
> + struct device *dev = &pdev->dev;
> + struct dwc3_generic *dwc3;
> + struct resource *res;
> + int ret;
> +
> + dwc3 = devm_kzalloc(dev, sizeof(*dwc3), GFP_KERNEL);
> + if (!dwc3)
> + return -ENOMEM;
> +
> + dwc3->dev = dev;
> +
> + platform_set_drvdata(pdev, dwc3);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(&pdev->dev, "missing memory resource\n");
> + return -ENODEV;
> + }
> +
> + dwc3->resets = of_reset_control_array_get_optional_exclusive(dev->of_node);
> + if (IS_ERR(dwc3->resets))
> + return dev_err_probe(dev, PTR_ERR(dwc3->resets), "failed to get reset\n");
> +
> + ret = reset_control_assert(dwc3->resets);
> + if (ret)
> + return dev_err_probe(dev, ret, "failed to assert reset\n");
> +
> + usleep_range(10, 1000);
> +
> + ret = reset_control_deassert(dwc3->resets);
> + if (ret) {
> + dev_err(dev, "failed to deassert reset\n");
> + goto reset_assert;
> + }
> +
> + ret = clk_bulk_get_all(dwc3->dev, &dwc3->clks);
can you check if able to use devres api for reset/clock here?
(functions start devm_ prefix)
> + if (ret < 0) {
> + dev_err(dev, "failed to get clocks\nt");
> + goto reset_assert;
> + }
> +
> + dwc3->num_clocks = ret;
> +
> + ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks);
> + if (ret) {
> + dev_err(dev, "failed to enable clocks\n");
> + goto reset_assert;
> + }
> +
> + dwc3->dwc.dev = dev;
> + probe_data.dwc = &dwc3->dwc;
> + probe_data.res = res;
> + probe_data.ignore_clocks_and_resets = true;
> + ret = dwc3_core_probe(&probe_data);
> + if (ret) {
> + dev_err(dev, "failed to register DWC3 Core\n");
> + goto clk_disable;
> + }
> +
> + return 0;
> +
> +clk_disable:
> + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> + clk_bulk_put_all(dwc3->num_clocks, dwc3->clks);
> +
> +reset_assert:
> + reset_control_assert(dwc3->resets);
> +
> + return ret;
> +}
> +
> +static void dwc3_generic_remove(struct platform_device *pdev)
> +{
> + struct dwc3_generic *dwc3 = platform_get_drvdata(pdev);
> +
> + dwc3_core_remove(&dwc3->dwc);
> +
> + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> + clk_bulk_put_all(dwc3->num_clocks, dwc3->clks);
> +
> + reset_control_assert(dwc3->resets);
> +}
> +
> +static int __maybe_unused dwc3_generic_suspend(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> + int ret;
> +
> + ret = dwc3_pm_suspend(&dwc3->dwc);
> + if (ret)
> + return ret;
> +
> + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks);
> +
> + return 0;
> +}
> +
> +static int __maybe_unused dwc3_generic_resume(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> + int ret;
> +
> + ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks);
> + if (ret)
> + return ret;
> +
> + ret = dwc3_pm_resume(&dwc3->dwc);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int __maybe_unused dwc3_generic_runtime_suspend(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> +
> + return dwc3_runtime_suspend(&dwc3->dwc);
> +}
> +
> +static int __maybe_unused dwc3_generic_runtime_resume(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> +
> + return dwc3_runtime_resume(&dwc3->dwc);
> +}
> +
> +static int __maybe_unused dwc3_generic_runtime_idle(struct device *dev)
> +{
> + struct dwc3_generic *dwc3 = dev_get_drvdata(dev);
> +
> + return dwc3_runtime_idle(&dwc3->dwc);
> +}
> +
> +static const struct dev_pm_ops dwc3_generic_dev_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(dwc3_generic_suspend, dwc3_generic_resume)
> + SET_RUNTIME_PM_OPS(dwc3_generic_runtime_suspend, dwc3_generic_runtime_resume,
> + dwc3_generic_runtime_idle)
> +};
> +
> +static const struct of_device_id dwc3_generic_of_match[] = {
> + { .compatible = "spacemit,k1-dwc3", },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, dwc3_generic_of_match);
> +
> +static struct platform_driver dwc3_generic_driver = {
> + .probe = dwc3_generic_probe,
> + .remove = dwc3_generic_remove,
> + .driver = {
> + .name = "dwc3-generic-plat",
> + .of_match_table = dwc3_generic_of_match,
> +#ifdef CONFIG_PM_SLEEP
> + .pm = &dwc3_generic_dev_pm_ops,
> +#endif /* CONFIG_PM_SLEEP */
> + },
> +};
> +module_platform_driver(dwc3_generic_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("DesignWare USB3 generic platform driver");
>
> --
> 2.49.0
>
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <20250605213443.17a7aa26b@smtp.qiye.163.com>]
* Re: [PATCH v4 3/4] usb: dwc3: add generic driver to support flattened DT
[not found] ` <20250605213443.17a7aa26b@smtp.qiye.163.com>
@ 2025-06-06 11:43 ` Ze Huang
0 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-06-06 11:43 UTC (permalink / raw)
To: Yixun Lan, Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thinh Nguyen, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, linux-usb, devicetree,
linux-riscv, spacemit, linux-kernel
On Thu, Jun 05, 2025 at 01:34:27PM +0000, Yixun Lan wrote:
> Hi Ze,
>
> On 22:40 Mon 26 May , Ze Huang wrote:
> > To support flattened dwc3 dt model and drop the glue layer, introduce the
> > `dwc3-generic` driver. This enables direct binding of the DWC3 core driver
> > and offers an alternative to the existing glue driver `dwc3-of-simple`.
> >
> > Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> > ---
...
> > + ret = reset_control_deassert(dwc3->resets);
> > + if (ret) {
> > + dev_err(dev, "failed to deassert reset\n");
> > + goto reset_assert;
> > + }
> > +
> > + ret = clk_bulk_get_all(dwc3->dev, &dwc3->clks);
> can you check if able to use devres api for reset/clock here?
> (functions start devm_ prefix)
>
OK, will do
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v4 3/4] usb: dwc3: add generic driver to support flattened DT
@ 2025-06-06 11:43 ` Ze Huang
0 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-06-06 11:43 UTC (permalink / raw)
To: Yixun Lan, Ze Huang
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thinh Nguyen, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, linux-usb, devicetree,
linux-riscv, spacemit, linux-kernel
On Thu, Jun 05, 2025 at 01:34:27PM +0000, Yixun Lan wrote:
> Hi Ze,
>
> On 22:40 Mon 26 May , Ze Huang wrote:
> > To support flattened dwc3 dt model and drop the glue layer, introduce the
> > `dwc3-generic` driver. This enables direct binding of the DWC3 core driver
> > and offers an alternative to the existing glue driver `dwc3-of-simple`.
> >
> > Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> > ---
...
> > + ret = reset_control_deassert(dwc3->resets);
> > + if (ret) {
> > + dev_err(dev, "failed to deassert reset\n");
> > + goto reset_assert;
> > + }
> > +
> > + ret = clk_bulk_get_all(dwc3->dev, &dwc3->clks);
> can you check if able to use devres api for reset/clock here?
> (functions start devm_ prefix)
>
OK, will do
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v4 4/4] riscv: dts: spacemit: add usb3.0 support for K1
2025-05-26 14:40 ` Ze Huang
@ 2025-05-26 14:40 ` Ze Huang
-1 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-05-26 14:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: linux-usb, devicetree, linux-riscv, spacemit, linux-kernel,
Ze Huang
Add USB 3.0 support for the SpacemiT K1 SoC, including the
following components:
- USB 2.0 PHY nodes
- USB 3.0 combo PHY node
- USB 3.0 host controller
- USB 3.0 hub and vbus regulator (usb3_vhub, usb3_vbus)
- DRAM interconnect node for USB DMA ("dma-mem")
The `usb3_vbus` and `usb3_vhub` regulator node provides a fixed 5V
supply to power the onboard USB 3.0 hub and usb vbus.
On K1, some DMA transfers from devices to memory use separate buses with
different DMA address translation rules from the parent node. We express
this relationship through the interconnects node "dma-mem", similar to [1].
Link: https://lore.kernel.org/all/09e5e29a4c54ec7337e4e62e5d6001b69d92b103.1554108995.git-series.maxime.ripard@bootlin.com [1]
Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 51 +++++++++++++++++++
arch/riscv/boot/dts/spacemit/k1.dtsi | 67 +++++++++++++++++++++++++
2 files changed, 118 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 816ef1bc358ec490aff184d5915d680dbd9f00cb..1f4585fe30b64a63ee643ed9596a3a97db8c0f0d 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -28,6 +28,25 @@ led1 {
default-state = "on";
};
};
+
+ usb3_vhub: regulator-vhub-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "USB30_VHUB";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usb3_vbus: regulator-vbus-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "USB30_VBUS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
&uart0 {
@@ -35,3 +54,35 @@ &uart0 {
pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};
+
+&usbphy2 {
+ status = "okay";
+};
+
+&combphy {
+ status = "okay";
+};
+
+&usb_dwc3 {
+ dr_mode = "host";
+ vbus-supply = <&usb3_vbus>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ hub_2_0: hub@1 {
+ compatible = "usb2109,2817";
+ reg = <0x1>;
+ vdd-supply = <&usb3_vhub>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb2109,817";
+ reg = <0x2>;
+ vdd-supply = <&usb3_vhub>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
+ };
+};
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 61f5ca250ded0da7b91cd4bbd55a5574a89c6ab0..e57b39bba877f90d52227349c983ce638559e601 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -4,6 +4,8 @@
*/
#include <dt-bindings/clock/spacemit,k1-syscon.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
/dts-v1/;
/ {
@@ -346,6 +348,15 @@ soc {
dma-noncoherent;
ranges;
+ mbus0: dram-controller@0 {
+ compatible = "spacemit,k1-mbus";
+ reg = <0x0 0x00000000 0x0 0x80000000>;
+ dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #interconnect-cells = <0>;
+ };
+
syscon_rcpu: system-controller@c0880000 {
compatible = "spacemit,k1-syscon-rcpu";
reg = <0x0 0xc0880000 0x0 0x2048>;
@@ -358,6 +369,62 @@ syscon_rcpu2: system-controller@c0888000 {
#reset-cells = <1>;
};
+ usb_dwc3: usb@c0a00000 {
+ compatible = "spacemit,k1-dwc3";
+ reg = <0x0 0xc0a00000 0x0 0x10000>;
+ clocks = <&syscon_apmu CLK_USB30>;
+ clock-names = "usbdrd30";
+ interconnects = <&mbus0>;
+ interconnect-names = "dma-mem";
+ interrupts = <125>;
+ phys = <&usbphy2>, <&combphy PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi";
+ resets = <&syscon_apmu RESET_USB3_0>;
+ snps,hsphy_interface = "utmi";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,dis_rxdet_inp3_quirk;
+ status = "disabled";
+ };
+
+ usbphy0: phy@c0940000 {
+ compatible = "spacemit,k1-usb2-phy";
+ reg = <0x0 0xc0940000 0x0 0x200>;
+ clocks = <&syscon_apmu CLK_USB_AXI>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usbphy1: phy@c09c0000 {
+ compatible = "spacemit,k1-usb2-phy";
+ reg = <0x0 0xc09c0000 0x0 0x200>;
+ clocks = <&syscon_apmu CLK_USB_P1>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usbphy2: phy@c0a30000 {
+ compatible = "spacemit,k1-usb2-phy";
+ reg = <0x0 0xc0a30000 0x0 0x200>;
+ clocks = <&syscon_apmu CLK_USB30>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ combphy: phy@c0b10000 {
+ compatible = "spacemit,k1-combphy";
+ reg = <0x0 0xc0b10000 0x0 0x800>,
+ <0x0 0xd4282910 0x0 0x400>;
+ reg-names = "ctrl", "sel";
+ resets = <&syscon_apmu RESET_PCIE0>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
syscon_apbc: system-control@d4015000 {
compatible = "spacemit,k1-syscon-apbc";
reg = <0x0 0xd4015000 0x0 0x1000>;
--
2.49.0
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^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH v4 4/4] riscv: dts: spacemit: add usb3.0 support for K1
@ 2025-05-26 14:40 ` Ze Huang
0 siblings, 0 replies; 40+ messages in thread
From: Ze Huang @ 2025-05-26 14:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Thinh Nguyen, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: linux-usb, devicetree, linux-riscv, spacemit, linux-kernel,
Ze Huang
Add USB 3.0 support for the SpacemiT K1 SoC, including the
following components:
- USB 2.0 PHY nodes
- USB 3.0 combo PHY node
- USB 3.0 host controller
- USB 3.0 hub and vbus regulator (usb3_vhub, usb3_vbus)
- DRAM interconnect node for USB DMA ("dma-mem")
The `usb3_vbus` and `usb3_vhub` regulator node provides a fixed 5V
supply to power the onboard USB 3.0 hub and usb vbus.
On K1, some DMA transfers from devices to memory use separate buses with
different DMA address translation rules from the parent node. We express
this relationship through the interconnects node "dma-mem", similar to [1].
Link: https://lore.kernel.org/all/09e5e29a4c54ec7337e4e62e5d6001b69d92b103.1554108995.git-series.maxime.ripard@bootlin.com [1]
Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 51 +++++++++++++++++++
arch/riscv/boot/dts/spacemit/k1.dtsi | 67 +++++++++++++++++++++++++
2 files changed, 118 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 816ef1bc358ec490aff184d5915d680dbd9f00cb..1f4585fe30b64a63ee643ed9596a3a97db8c0f0d 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -28,6 +28,25 @@ led1 {
default-state = "on";
};
};
+
+ usb3_vhub: regulator-vhub-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "USB30_VHUB";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usb3_vbus: regulator-vbus-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "USB30_VBUS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
&uart0 {
@@ -35,3 +54,35 @@ &uart0 {
pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};
+
+&usbphy2 {
+ status = "okay";
+};
+
+&combphy {
+ status = "okay";
+};
+
+&usb_dwc3 {
+ dr_mode = "host";
+ vbus-supply = <&usb3_vbus>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ hub_2_0: hub@1 {
+ compatible = "usb2109,2817";
+ reg = <0x1>;
+ vdd-supply = <&usb3_vhub>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb2109,817";
+ reg = <0x2>;
+ vdd-supply = <&usb3_vhub>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
+ };
+};
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 61f5ca250ded0da7b91cd4bbd55a5574a89c6ab0..e57b39bba877f90d52227349c983ce638559e601 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -4,6 +4,8 @@
*/
#include <dt-bindings/clock/spacemit,k1-syscon.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
/dts-v1/;
/ {
@@ -346,6 +348,15 @@ soc {
dma-noncoherent;
ranges;
+ mbus0: dram-controller@0 {
+ compatible = "spacemit,k1-mbus";
+ reg = <0x0 0x00000000 0x0 0x80000000>;
+ dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #interconnect-cells = <0>;
+ };
+
syscon_rcpu: system-controller@c0880000 {
compatible = "spacemit,k1-syscon-rcpu";
reg = <0x0 0xc0880000 0x0 0x2048>;
@@ -358,6 +369,62 @@ syscon_rcpu2: system-controller@c0888000 {
#reset-cells = <1>;
};
+ usb_dwc3: usb@c0a00000 {
+ compatible = "spacemit,k1-dwc3";
+ reg = <0x0 0xc0a00000 0x0 0x10000>;
+ clocks = <&syscon_apmu CLK_USB30>;
+ clock-names = "usbdrd30";
+ interconnects = <&mbus0>;
+ interconnect-names = "dma-mem";
+ interrupts = <125>;
+ phys = <&usbphy2>, <&combphy PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi";
+ resets = <&syscon_apmu RESET_USB3_0>;
+ snps,hsphy_interface = "utmi";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,dis_rxdet_inp3_quirk;
+ status = "disabled";
+ };
+
+ usbphy0: phy@c0940000 {
+ compatible = "spacemit,k1-usb2-phy";
+ reg = <0x0 0xc0940000 0x0 0x200>;
+ clocks = <&syscon_apmu CLK_USB_AXI>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usbphy1: phy@c09c0000 {
+ compatible = "spacemit,k1-usb2-phy";
+ reg = <0x0 0xc09c0000 0x0 0x200>;
+ clocks = <&syscon_apmu CLK_USB_P1>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usbphy2: phy@c0a30000 {
+ compatible = "spacemit,k1-usb2-phy";
+ reg = <0x0 0xc0a30000 0x0 0x200>;
+ clocks = <&syscon_apmu CLK_USB30>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ combphy: phy@c0b10000 {
+ compatible = "spacemit,k1-combphy";
+ reg = <0x0 0xc0b10000 0x0 0x800>,
+ <0x0 0xd4282910 0x0 0x400>;
+ reg-names = "ctrl", "sel";
+ resets = <&syscon_apmu RESET_PCIE0>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
syscon_apbc: system-control@d4015000 {
compatible = "spacemit,k1-syscon-apbc";
reg = <0x0 0xd4015000 0x0 0x1000>;
--
2.49.0
^ permalink raw reply related [flat|nested] 40+ messages in thread