From: Anup Patel <apatel@ventanamicro.com>
To: Atish Patra <atish.patra@linux.dev>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Alexandre Ghiti <alex@ghiti.fr>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH 00/13] MMU related improvements for KVM RISC-V
Date: Thu, 5 Jun 2025 11:44:45 +0530 [thread overview]
Message-ID: <20250605061458.196003-1-apatel@ventanamicro.com> (raw)
This series primarily has various MMU improvements for KVM RISC-V
and it also serves as a preparatory series for the upcoming nested
virtualization support.
PATCH1 to PATCH2: SBI spec related fixes in SBI RFENCE extension
PATCH3 to PATCH6: Few cosmetic improvements
PATCH7 to PATCH8: TLB maintenance related improvements
PATCH9 to PATCH13: MMU related preparatory work for nested virtualization
These patches can also be found in the riscv_kvm_mmu_imp_v1 branch
at: https://github.com/avpatel/linux.git
Anup Patel (13):
RISC-V: KVM: Fix the size parameter check in SBI SFENCE calls
RISC-V: KVM: Don't treat SBI HFENCE calls as NOPs
RISC-V: KVM: Check kvm_riscv_vcpu_alloc_vector_context() return value
RISC-V: KVM: Drop the return value of kvm_riscv_vcpu_aia_init()
RISC-V: KVM: Rename and move kvm_riscv_local_tlb_sanitize()
RISC-V: KVM: Replace KVM_REQ_HFENCE_GVMA_VMID_ALL with
KVM_REQ_TLB_FLUSH
RISC-V: KVM: Don't flush TLB in gstage_set_pte() when PTE is unchanged
RISC-V: KVM: Implement kvm_arch_flush_remote_tlbs_range()
RISC-V: KVM: Factor-out MMU related declarations into separate headers
RISC-V: KVM: Introduce struct kvm_gstage_mapping
RISC-V: KVM: Add vmid field to struct kvm_riscv_hfence
RISC-V: KVM: Factor-out g-stage page table management
RISC-V: KVM: Pass VMID as parameter to kvm_riscv_hfence_xyz() APIs
arch/riscv/include/asm/kvm_aia.h | 2 +-
arch/riscv/include/asm/kvm_gstage.h | 72 ++++
arch/riscv/include/asm/kvm_host.h | 103 +-----
arch/riscv/include/asm/kvm_mmu.h | 21 ++
arch/riscv/include/asm/kvm_tlb.h | 84 +++++
arch/riscv/include/asm/kvm_vmid.h | 27 ++
arch/riscv/kvm/Makefile | 1 +
arch/riscv/kvm/aia_device.c | 6 +-
arch/riscv/kvm/aia_imsic.c | 12 +-
arch/riscv/kvm/gstage.c | 336 +++++++++++++++++++
arch/riscv/kvm/main.c | 3 +-
arch/riscv/kvm/mmu.c | 499 ++++++----------------------
arch/riscv/kvm/tlb.c | 110 +++---
arch/riscv/kvm/vcpu.c | 27 +-
arch/riscv/kvm/vcpu_exit.c | 7 +-
arch/riscv/kvm/vcpu_sbi_replace.c | 25 +-
arch/riscv/kvm/vcpu_sbi_v01.c | 25 +-
arch/riscv/kvm/vm.c | 7 +-
arch/riscv/kvm/vmid.c | 25 ++
19 files changed, 791 insertions(+), 601 deletions(-)
create mode 100644 arch/riscv/include/asm/kvm_gstage.h
create mode 100644 arch/riscv/include/asm/kvm_mmu.h
create mode 100644 arch/riscv/include/asm/kvm_tlb.h
create mode 100644 arch/riscv/include/asm/kvm_vmid.h
create mode 100644 arch/riscv/kvm/gstage.c
--
2.43.0
--
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Atish Patra <atish.patra@linux.dev>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Alexandre Ghiti <alex@ghiti.fr>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH 00/13] MMU related improvements for KVM RISC-V
Date: Thu, 5 Jun 2025 11:44:45 +0530 [thread overview]
Message-ID: <20250605061458.196003-1-apatel@ventanamicro.com> (raw)
This series primarily has various MMU improvements for KVM RISC-V
and it also serves as a preparatory series for the upcoming nested
virtualization support.
PATCH1 to PATCH2: SBI spec related fixes in SBI RFENCE extension
PATCH3 to PATCH6: Few cosmetic improvements
PATCH7 to PATCH8: TLB maintenance related improvements
PATCH9 to PATCH13: MMU related preparatory work for nested virtualization
These patches can also be found in the riscv_kvm_mmu_imp_v1 branch
at: https://github.com/avpatel/linux.git
Anup Patel (13):
RISC-V: KVM: Fix the size parameter check in SBI SFENCE calls
RISC-V: KVM: Don't treat SBI HFENCE calls as NOPs
RISC-V: KVM: Check kvm_riscv_vcpu_alloc_vector_context() return value
RISC-V: KVM: Drop the return value of kvm_riscv_vcpu_aia_init()
RISC-V: KVM: Rename and move kvm_riscv_local_tlb_sanitize()
RISC-V: KVM: Replace KVM_REQ_HFENCE_GVMA_VMID_ALL with
KVM_REQ_TLB_FLUSH
RISC-V: KVM: Don't flush TLB in gstage_set_pte() when PTE is unchanged
RISC-V: KVM: Implement kvm_arch_flush_remote_tlbs_range()
RISC-V: KVM: Factor-out MMU related declarations into separate headers
RISC-V: KVM: Introduce struct kvm_gstage_mapping
RISC-V: KVM: Add vmid field to struct kvm_riscv_hfence
RISC-V: KVM: Factor-out g-stage page table management
RISC-V: KVM: Pass VMID as parameter to kvm_riscv_hfence_xyz() APIs
arch/riscv/include/asm/kvm_aia.h | 2 +-
arch/riscv/include/asm/kvm_gstage.h | 72 ++++
arch/riscv/include/asm/kvm_host.h | 103 +-----
arch/riscv/include/asm/kvm_mmu.h | 21 ++
arch/riscv/include/asm/kvm_tlb.h | 84 +++++
arch/riscv/include/asm/kvm_vmid.h | 27 ++
arch/riscv/kvm/Makefile | 1 +
arch/riscv/kvm/aia_device.c | 6 +-
arch/riscv/kvm/aia_imsic.c | 12 +-
arch/riscv/kvm/gstage.c | 336 +++++++++++++++++++
arch/riscv/kvm/main.c | 3 +-
arch/riscv/kvm/mmu.c | 499 ++++++----------------------
arch/riscv/kvm/tlb.c | 110 +++---
arch/riscv/kvm/vcpu.c | 27 +-
arch/riscv/kvm/vcpu_exit.c | 7 +-
arch/riscv/kvm/vcpu_sbi_replace.c | 25 +-
arch/riscv/kvm/vcpu_sbi_v01.c | 25 +-
arch/riscv/kvm/vm.c | 7 +-
arch/riscv/kvm/vmid.c | 25 ++
19 files changed, 791 insertions(+), 601 deletions(-)
create mode 100644 arch/riscv/include/asm/kvm_gstage.h
create mode 100644 arch/riscv/include/asm/kvm_mmu.h
create mode 100644 arch/riscv/include/asm/kvm_tlb.h
create mode 100644 arch/riscv/include/asm/kvm_vmid.h
create mode 100644 arch/riscv/kvm/gstage.c
--
2.43.0
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Atish Patra <atish.patra@linux.dev>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Alexandre Ghiti <alex@ghiti.fr>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH 00/13] MMU related improvements for KVM RISC-V
Date: Thu, 5 Jun 2025 11:44:45 +0530 [thread overview]
Message-ID: <20250605061458.196003-1-apatel@ventanamicro.com> (raw)
This series primarily has various MMU improvements for KVM RISC-V
and it also serves as a preparatory series for the upcoming nested
virtualization support.
PATCH1 to PATCH2: SBI spec related fixes in SBI RFENCE extension
PATCH3 to PATCH6: Few cosmetic improvements
PATCH7 to PATCH8: TLB maintenance related improvements
PATCH9 to PATCH13: MMU related preparatory work for nested virtualization
These patches can also be found in the riscv_kvm_mmu_imp_v1 branch
at: https://github.com/avpatel/linux.git
Anup Patel (13):
RISC-V: KVM: Fix the size parameter check in SBI SFENCE calls
RISC-V: KVM: Don't treat SBI HFENCE calls as NOPs
RISC-V: KVM: Check kvm_riscv_vcpu_alloc_vector_context() return value
RISC-V: KVM: Drop the return value of kvm_riscv_vcpu_aia_init()
RISC-V: KVM: Rename and move kvm_riscv_local_tlb_sanitize()
RISC-V: KVM: Replace KVM_REQ_HFENCE_GVMA_VMID_ALL with
KVM_REQ_TLB_FLUSH
RISC-V: KVM: Don't flush TLB in gstage_set_pte() when PTE is unchanged
RISC-V: KVM: Implement kvm_arch_flush_remote_tlbs_range()
RISC-V: KVM: Factor-out MMU related declarations into separate headers
RISC-V: KVM: Introduce struct kvm_gstage_mapping
RISC-V: KVM: Add vmid field to struct kvm_riscv_hfence
RISC-V: KVM: Factor-out g-stage page table management
RISC-V: KVM: Pass VMID as parameter to kvm_riscv_hfence_xyz() APIs
arch/riscv/include/asm/kvm_aia.h | 2 +-
arch/riscv/include/asm/kvm_gstage.h | 72 ++++
arch/riscv/include/asm/kvm_host.h | 103 +-----
arch/riscv/include/asm/kvm_mmu.h | 21 ++
arch/riscv/include/asm/kvm_tlb.h | 84 +++++
arch/riscv/include/asm/kvm_vmid.h | 27 ++
arch/riscv/kvm/Makefile | 1 +
arch/riscv/kvm/aia_device.c | 6 +-
arch/riscv/kvm/aia_imsic.c | 12 +-
arch/riscv/kvm/gstage.c | 336 +++++++++++++++++++
arch/riscv/kvm/main.c | 3 +-
arch/riscv/kvm/mmu.c | 499 ++++++----------------------
arch/riscv/kvm/tlb.c | 110 +++---
arch/riscv/kvm/vcpu.c | 27 +-
arch/riscv/kvm/vcpu_exit.c | 7 +-
arch/riscv/kvm/vcpu_sbi_replace.c | 25 +-
arch/riscv/kvm/vcpu_sbi_v01.c | 25 +-
arch/riscv/kvm/vm.c | 7 +-
arch/riscv/kvm/vmid.c | 25 ++
19 files changed, 791 insertions(+), 601 deletions(-)
create mode 100644 arch/riscv/include/asm/kvm_gstage.h
create mode 100644 arch/riscv/include/asm/kvm_mmu.h
create mode 100644 arch/riscv/include/asm/kvm_tlb.h
create mode 100644 arch/riscv/include/asm/kvm_vmid.h
create mode 100644 arch/riscv/kvm/gstage.c
--
2.43.0
_______________________________________________
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next reply other threads:[~2025-06-05 6:15 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-05 6:14 Anup Patel [this message]
2025-06-05 6:14 ` [PATCH 00/13] MMU related improvements for KVM RISC-V Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` [PATCH 01/13] RISC-V: KVM: Fix the size parameter check in SBI SFENCE calls Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-06 0:00 ` Atish Patra
2025-06-06 0:00 ` Atish Patra
2025-06-06 0:00 ` Atish Patra
2025-06-09 4:43 ` Anup Patel
2025-06-09 4:43 ` Anup Patel
2025-06-09 4:43 ` Anup Patel
2025-06-05 6:14 ` [PATCH 02/13] RISC-V: KVM: Don't treat SBI HFENCE calls as NOPs Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-06 0:11 ` Atish Patra
2025-06-06 0:11 ` Atish Patra
2025-06-06 0:11 ` Atish Patra
2025-06-09 4:43 ` Anup Patel
2025-06-09 4:43 ` Anup Patel
2025-06-09 4:43 ` Anup Patel
2025-06-05 6:14 ` [PATCH 03/13] RISC-V: KVM: Check kvm_riscv_vcpu_alloc_vector_context() return value Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-06 0:16 ` Atish Patra
2025-06-06 0:16 ` Atish Patra
2025-06-06 0:16 ` Atish Patra
2025-06-09 5:01 ` Anup Patel
2025-06-09 5:01 ` Anup Patel
2025-06-09 5:01 ` Anup Patel
2025-06-05 6:14 ` [PATCH 04/13] RISC-V: KVM: Drop the return value of kvm_riscv_vcpu_aia_init() Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-06 0:52 ` Atish Patra
2025-06-06 0:52 ` Atish Patra
2025-06-06 0:52 ` Atish Patra
2025-06-06 4:14 ` Nutty Liu
2025-06-06 4:14 ` Nutty Liu
2025-06-06 4:14 ` Nutty Liu
2025-06-05 6:14 ` [PATCH 05/13] RISC-V: KVM: Rename and move kvm_riscv_local_tlb_sanitize() Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-06 1:21 ` Atish Patra
2025-06-06 1:21 ` Atish Patra
2025-06-06 1:21 ` Atish Patra
2025-06-06 4:25 ` Nutty Liu
2025-06-06 4:25 ` Nutty Liu
2025-06-06 4:25 ` Nutty Liu
2025-06-05 6:14 ` [PATCH 06/13] RISC-V: KVM: Replace KVM_REQ_HFENCE_GVMA_VMID_ALL with KVM_REQ_TLB_FLUSH Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-06 1:24 ` Atish Patra
2025-06-06 1:24 ` Atish Patra
2025-06-06 1:24 ` Atish Patra
2025-06-05 6:14 ` [PATCH 07/13] RISC-V: KVM: Don't flush TLB in gstage_set_pte() when PTE is unchanged Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` [PATCH 08/13] RISC-V: KVM: Implement kvm_arch_flush_remote_tlbs_range() Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` [PATCH 09/13] RISC-V: KVM: Factor-out MMU related declarations into separate headers Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` [PATCH 10/13] RISC-V: KVM: Introduce struct kvm_gstage_mapping Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` [PATCH 11/13] RISC-V: KVM: Add vmid field to struct kvm_riscv_hfence Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` [PATCH 12/13] RISC-V: KVM: Factor-out g-stage page table management Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` [PATCH 13/13] RISC-V: KVM: Pass VMID as parameter to kvm_riscv_hfence_xyz() APIs Anup Patel
2025-06-05 6:14 ` Anup Patel
2025-06-05 6:14 ` Anup Patel
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