From: Jonathan Cameron via <qemu-arm@nongnu.org>
To: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>,
<linuxarm@huawei.com>
Cc: <qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>,
<eric.auger@redhat.com>, <peter.maydell@linaro.org>,
<jgg@nvidia.com>, <nicolinc@nvidia.com>, <ddutile@redhat.com>,
<berrange@redhat.com>, <imammedo@redhat.com>,
<nathanc@nvidia.com>, <mochs@nvidia.com>, <smostafa@google.com>,
<gustavo.romero@linaro.org>, <wangzhou1@hisilicon.com>,
<jiangkunkun@huawei.com>, <jonathan.cameron@huawei.com>,
<zhangfei.gao@linaro.org>
Subject: Re: [PATCH v5 08/11] qemu-options.hx: Document the arm-smmuv3 device
Date: Mon, 23 Jun 2025 12:47:29 +0100 [thread overview]
Message-ID: <20250623124712.000058de@huawei.com> (raw)
In-Reply-To: <20250623094230.76084-9-shameerali.kolothum.thodi@huawei.com>
On Mon, 23 Jun 2025 10:42:27 +0100
Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> wrote:
> Now that arm,virt can have user-creatable smmuv3 devices, document it.
>
> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> ---
> qemu-options.hx | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/qemu-options.hx b/qemu-options.hx
> index 7eb8e02b4b..7d1a12f7ef 100644
> --- a/qemu-options.hx
> +++ b/qemu-options.hx
> @@ -1226,6 +1226,13 @@ SRST
> ``aw-bits=val`` (val between 32 and 64, default depends on machine)
> This decides the address width of the IOVA address space.
>
> +``-device arm-smmuv3,primary-bus=id``
> + This is only supported by ``-machine virt`` (ARM).
> +
> + ``primary-bus=id``
> + Accepts either the default root complex (pcie.0) or a
> + pxb-pcie based root complex.
> +
> ERST
>
> DEF("name", HAS_ARG, QEMU_OPTION_name,
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>,
<linuxarm@huawei.com>
Cc: <qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>,
<eric.auger@redhat.com>, <peter.maydell@linaro.org>,
<jgg@nvidia.com>, <nicolinc@nvidia.com>, <ddutile@redhat.com>,
<berrange@redhat.com>, <imammedo@redhat.com>,
<nathanc@nvidia.com>, <mochs@nvidia.com>, <smostafa@google.com>,
<gustavo.romero@linaro.org>, <wangzhou1@hisilicon.com>,
<jiangkunkun@huawei.com>, <jonathan.cameron@huawei.com>,
<zhangfei.gao@linaro.org>
Subject: Re: [PATCH v5 08/11] qemu-options.hx: Document the arm-smmuv3 device
Date: Mon, 23 Jun 2025 12:47:29 +0100 [thread overview]
Message-ID: <20250623124712.000058de@huawei.com> (raw)
In-Reply-To: <20250623094230.76084-9-shameerali.kolothum.thodi@huawei.com>
On Mon, 23 Jun 2025 10:42:27 +0100
Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> wrote:
> Now that arm,virt can have user-creatable smmuv3 devices, document it.
>
> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> ---
> qemu-options.hx | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/qemu-options.hx b/qemu-options.hx
> index 7eb8e02b4b..7d1a12f7ef 100644
> --- a/qemu-options.hx
> +++ b/qemu-options.hx
> @@ -1226,6 +1226,13 @@ SRST
> ``aw-bits=val`` (val between 32 and 64, default depends on machine)
> This decides the address width of the IOVA address space.
>
> +``-device arm-smmuv3,primary-bus=id``
> + This is only supported by ``-machine virt`` (ARM).
> +
> + ``primary-bus=id``
> + Accepts either the default root complex (pcie.0) or a
> + pxb-pcie based root complex.
> +
> ERST
>
> DEF("name", HAS_ARG, QEMU_OPTION_name,
next prev parent reply other threads:[~2025-06-23 11:47 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-23 9:42 [PATCH v5 00/11] hw/arm/virt: Add support for user creatable SMMUv3 device Shameer Kolothum via
2025-06-23 9:42 ` Shameer Kolothum via
2025-06-23 9:42 ` [PATCH v5 01/11] hw/arm/smmu-common: Check SMMU has PCIe Root Complex association Shameer Kolothum via
2025-06-23 9:42 ` Shameer Kolothum via
2025-06-23 11:32 ` Jonathan Cameron via
2025-06-23 11:32 ` Jonathan Cameron via
2025-06-27 11:52 ` Eric Auger
2025-06-30 7:01 ` Shameerali Kolothum Thodi via
2025-06-30 7:01 ` Shameerali Kolothum Thodi via
2025-07-01 6:31 ` Eric Auger
2025-06-23 9:42 ` [PATCH v5 02/11] hw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT build Shameer Kolothum via
2025-06-23 9:42 ` Shameer Kolothum via
2025-06-27 11:54 ` Eric Auger
2025-06-23 9:42 ` [PATCH v5 03/11] hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices Shameer Kolothum via
2025-06-23 9:42 ` Shameer Kolothum via
2025-06-23 9:42 ` [PATCH v5 04/11] hw/arm/virt: Factor out common SMMUV3 dt bindings code Shameer Kolothum via
2025-06-23 9:42 ` Shameer Kolothum via
2025-06-23 9:42 ` [PATCH v5 05/11] hw/arm/virt: Add an SMMU_IO_LEN macro Shameer Kolothum via
2025-06-23 9:42 ` Shameer Kolothum via
2025-06-23 11:35 ` Jonathan Cameron via
2025-06-23 9:42 ` [PATCH v5 06/11] hw/pci: Introduce pci_setup_iommu_per_bus() for per-bus IOMMU ops retrieval Shameer Kolothum via
2025-06-23 9:42 ` Shameer Kolothum via
2025-06-23 11:39 ` Jonathan Cameron via
2025-06-27 12:04 ` Eric Auger
2025-06-30 7:05 ` Shameerali Kolothum Thodi via
2025-06-30 7:05 ` Shameerali Kolothum Thodi via
2025-06-30 7:37 ` Shameerali Kolothum Thodi via
2025-06-23 9:42 ` [PATCH v5 07/11] hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation Shameer Kolothum via
2025-06-23 9:42 ` Shameer Kolothum via
2025-06-23 11:46 ` Jonathan Cameron via
2025-06-23 11:46 ` Jonathan Cameron via
2025-06-27 12:05 ` Eric Auger
2025-06-23 9:42 ` [PATCH v5 08/11] qemu-options.hx: Document the arm-smmuv3 device Shameer Kolothum via
2025-06-23 9:42 ` Shameer Kolothum via
2025-06-23 11:47 ` Jonathan Cameron via [this message]
2025-06-23 11:47 ` Jonathan Cameron via
2025-06-27 12:08 ` Eric Auger
2025-06-23 9:42 ` [PATCH v5 09/11] bios-tables-test: Allow for smmuv3 test data Shameer Kolothum via
2025-06-23 11:49 ` Jonathan Cameron via
2025-06-27 12:14 ` Eric Auger
2025-06-23 9:42 ` [PATCH v5 10/11] qtest/bios-tables-test: Add tests for legacy smmuv3 and smmuv3 device Shameer Kolothum via
2025-06-23 11:57 ` Jonathan Cameron via
2025-06-23 11:57 ` Jonathan Cameron via
2025-06-27 12:34 ` Eric Auger
2025-06-30 7:08 ` Shameerali Kolothum Thodi via
2025-06-30 7:08 ` Shameerali Kolothum Thodi via
2025-06-23 9:42 ` [PATCH v5 11/11] qtest/bios-tables-test: Update tables for smmuv3 tests Shameer Kolothum via
2025-06-23 12:00 ` Jonathan Cameron via
2025-06-23 12:00 ` Jonathan Cameron via
2025-06-27 12:36 ` Eric Auger
2025-06-30 7:11 ` Shameerali Kolothum Thodi via
2025-06-30 7:11 ` Shameerali Kolothum Thodi via
2025-07-01 6:35 ` Eric Auger
2025-06-27 12:36 ` [PATCH v5 00/11] hw/arm/virt: Add support for user creatable SMMUv3 device Eric Auger
2025-06-30 7:12 ` Shameerali Kolothum Thodi via
2025-06-30 7:12 ` Shameerali Kolothum Thodi via
2025-07-01 6:37 ` Eric Auger
2025-07-02 1:01 ` Nathan Chen
2025-07-02 15:08 ` Shameerali Kolothum Thodi via
2025-07-02 15:08 ` Shameerali Kolothum Thodi via
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250623124712.000058de@huawei.com \
--to=qemu-arm@nongnu.org \
--cc=berrange@redhat.com \
--cc=ddutile@redhat.com \
--cc=eric.auger@redhat.com \
--cc=gustavo.romero@linaro.org \
--cc=imammedo@redhat.com \
--cc=jgg@nvidia.com \
--cc=jiangkunkun@huawei.com \
--cc=jonathan.cameron@huawei.com \
--cc=linuxarm@huawei.com \
--cc=mochs@nvidia.com \
--cc=nathanc@nvidia.com \
--cc=nicolinc@nvidia.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=shameerali.kolothum.thodi@huawei.com \
--cc=smostafa@google.com \
--cc=wangzhou1@hisilicon.com \
--cc=zhangfei.gao@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.