RE: [PATCH v5 11/11] qtest/bios-tables-test: Update tables for smmuv3 tests

[Shameerali Kolothum Thodi via <qemu-arm@nongnu.org>]

> -----Original Message-----
> From: Eric Auger <eric.auger@redhat.com>
> Sent: Friday, June 27, 2025 1:36 PM
> To: Shameerali Kolothum Thodi
> <shameerali.kolothum.thodi@huawei.com>; qemu-arm@nongnu.org;
> qemu-devel@nongnu.org
> Cc: peter.maydell@linaro.org; jgg@nvidia.com; nicolinc@nvidia.com;
> ddutile@redhat.com; berrange@redhat.com; imammedo@redhat.com;
> nathanc@nvidia.com; mochs@nvidia.com; smostafa@google.com;
> gustavo.romero@linaro.org; Linuxarm <linuxarm@huawei.com>; Wangzhou
> (B) <wangzhou1@hisilicon.com>; jiangkunkun <jiangkunkun@huawei.com>;
> Jonathan Cameron <jonathan.cameron@huawei.com>;
> zhangfei.gao@linaro.org
> Subject: Re: [PATCH v5 11/11] qtest/bios-tables-test: Update tables for
> smmuv3 tests
> 
> Hi Shameer,
> 
> On 6/23/25 11:42 AM, Shameer Kolothum wrote:
> > For the legacy smmuv3 test case, IORT has a single SMMUV3 node and a
> > Root Complex node with three ID mappings of which two points to the
> > SMMUv3 node and the remaining one points to ITS.
> 
> You don't describe DSDT at all below, just IORT. I don't know whether it is
> mandated though

I don't think DSDT is required as the code changes we want to test is
IORT related only.

> > ...
> > [030h 0048   1]                         Type : 00
> > [031h 0049   2]                       Length : 0018
> > [033h 0051   1]                     Revision : 01
> > [034h 0052   4]                   Identifier : 00000000
> > [038h 0056   4]                Mapping Count : 00000000
> > [03Ch 0060   4]               Mapping Offset : 00000000
> >
> > [040h 0064   4]                     ItsCount : 00000001
> > [044h 0068   4]                  Identifiers : 00000000
> >
> > [048h 0072   1]                         Type : 04
> > [049h 0073   2]                       Length : 0058
> > [04Bh 0075   1]                     Revision : 04
> > [04Ch 0076   4]                   Identifier : 00000001
> > [050h 0080   4]                Mapping Count : 00000001
> > [054h 0084   4]               Mapping Offset : 00000044
> >
> > [058h 0088   8]                 Base Address : 0000000009050000
> > [060h 0096   4]        Flags (decoded below) : 00000001
> >                              COHACC Override : 1
> >                                HTTU Override : 0
> >                       Proximity Domain Valid : 0
> > [064h 0100   4]                     Reserved : 00000000
> > [068h 0104   8]                VATOS Address : 0000000000000000
> > [070h 0112   4]                        Model : 00000000
> > [074h 0116   4]                   Event GSIV : 0000006A
> > [078h 0120   4]                     PRI GSIV : 0000006B
> > [07Ch 0124   4]                    GERR GSIV : 0000006D
> > [080h 0128   4]                    Sync GSIV : 0000006C
> > [084h 0132   4]             Proximity Domain : 00000000
> > [088h 0136   4]      Device ID Mapping Index : 00000000
> >
> > [08Ch 0140   4]                   Input base : 00000000
> > [090h 0144   4]                     ID Count : 0000FFFF
> > [094h 0148   4]                  Output Base : 00000000
> > [098h 0152   4]             Output Reference : 00000030
> > [09Ch 0156   4]        Flags (decoded below) : 00000000
> >                               Single Mapping : 0
> >
> > [0A0h 0160   1]                         Type : 02
> > [0A1h 0161   2]                       Length : 0074
> > [0A3h 0163   1]                     Revision : 03
> > [0A4h 0164   4]                   Identifier : 00000002
> > [0A8h 0168   4]                Mapping Count : 00000004
> > [0ACh 0172   4]               Mapping Offset : 00000024
> >
> > [0B0h 0176   8]            Memory Properties : [IORT Memory Access
> Properties]
> > [0B0h 0176   4]              Cache Coherency : 00000001
> > [0B4h 0180   1]        Hints (decoded below) : 00
> >                                    Transient : 0
> >                               Write Allocate : 0
> >                                Read Allocate : 0
> >                                     Override : 0
> > [0B5h 0181   2]                     Reserved : 0000
> > [0B7h 0183   1] Memory Flags (decoded below) : 03
> >                                    Coherency : 1
> >                             Device Attribute : 1
> > [0B8h 0184   4]                ATS Attribute : 00000000
> > [0BCh 0188   4]           PCI Segment Number : 00000000
> > [0C0h 0192   1]            Memory Size Limit : 40
> > [0C1h 0193   2]           PASID Capabilities : 0000
> > [0C3h 0195   1]                     Reserved : 00
> >
> > [0C4h 0196   4]                   Input base : 00000000
> > [0C8h 0200   4]                     ID Count : 000001FF
> > [0CCh 0204   4]                  Output Base : 00000000
> > [0D0h 0208   4]             Output Reference : 00000048
> > [0D4h 0212   4]        Flags (decoded below) : 00000000
> >                               Single Mapping : 0
> >
> > [0D8h 0216   4]                   Input base : 00001000
> > [0DCh 0220   4]                     ID Count : 000000FF
> > [0E0h 0224   4]                  Output Base : 00001000
> > [0E4h 0228   4]             Output Reference : 00000048
> > [0E8h 0232   4]        Flags (decoded below) : 00000000
> >                               Single Mapping : 0
> >
> > [0ECh 0236   4]                   Input base : 00000200
> > [0F0h 0240   4]                     ID Count : 00000DFF
> > [0F4h 0244   4]                  Output Base : 00000200
> > [0F8h 0248   4]             Output Reference : 00000030
> > [0FCh 0252   4]        Flags (decoded below) : 00000000
> >                               Single Mapping : 0
> >
> > [100h 0256   4]                   Input base : 00001100
> > [104h 0260   4]                     ID Count : 0000EEFF
> > [108h 0264   4]                  Output Base : 00001100
> > [10Ch 0268   4]             Output Reference : 00000030
> > [110h 0272   4]        Flags (decoded below) : 00000000
> >                               Single Mapping : 0
> >
> > For the smmuv3-dev test case, IORT has two SMMUV3 nodes and a Root
> > Complex node with ID mappings of which two points to two different
> > SMMUv3 nodes and remianining ones pointing
> remaining. Still difficult to parse for me ;-)

Ok 😊. I will rephrase as suggested in the previous one.

Thanks,
Shameer