[PATCH 0/2] riscv: fix envcfg.STCE

["Radim Krčmář" <rkrcmar@ventanamicro.com>]

Hello,

I reviewed a very unintuitive implementation of Sstc in Sail, and QEMU
seems to have a minor bug there, which is addressed [1/2].
[2/2] is just a sanitization.

I only compiled the code, and have no idea how to easily test it, so
feel free to drop the patches, and treat this as a bug report.

Thanks.

Radim Krčmář (2):
  target/riscv: disable *stimecmp interrupts without *envcfg.STCE
  target/riscv: disarm timer when writing past value

 target/riscv/csr.c         | 12 ++++++++++++
 target/riscv/time_helper.c | 12 ++++++++++++
 2 files changed, 24 insertions(+)

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2.49.0