From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Jim Shu" <jim.shu@sifive.com>
Cc: "Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
<qemu-riscv@nongnu.org>, <qemu-devel@nongnu.org>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Weiwei Li" <liwei1518@gmail.com>,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
"Atish Patra" <atishp@rivosinc.com>,
<qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org>
Subject: Re: [PATCH 1/2] target/riscv: disable *stimecmp interrupts without *envcfg.STCE
Date: Wed, 25 Jun 2025 09:26:19 +0200 [thread overview]
Message-ID: <DAVFP4YNR8KQ.3RYUHSEF34EG1@ventanamicro.com> (raw)
In-Reply-To: <CALw707rf-7ftLs3xM2Btxz9H78E0nDj6D=1N18jWe5jroZ_7Zg@mail.gmail.com>
2025-06-25T14:24:25+08:00, Jim Shu <jim.shu@sifive.com>:
> Hi Radim,
>
> Does your patchset want to resolve the same issue as my sstc patch [1]?
> My sstc patchset has been merged to "riscv-to-apply.next".
Yeah, I wasn't aware where patches go in the QEMU land.
> Maybe you can review it or check if there is still any issue in the
> "riscv-to-apply.next" branch, thanks!
My patch is doing exactly the same as [1/4] and [3/4] in your series.
I see you also fixed the NULL dereference. :)
I'm withdrawing this series, thanks.
next prev parent reply other threads:[~2025-06-25 7:27 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-23 16:53 [PATCH 0/2] riscv: fix envcfg.STCE Radim Krčmář
2025-06-23 16:53 ` [PATCH 1/2] target/riscv: disable *stimecmp interrupts without *envcfg.STCE Radim Krčmář
2025-06-23 21:39 ` Daniel Henrique Barboza
2025-06-24 12:48 ` Andrew Jones
2025-06-24 13:48 ` Radim Krčmář
2025-06-25 6:24 ` Jim Shu
2025-06-25 7:26 ` Radim Krčmář [this message]
2025-06-23 16:53 ` [PATCH 2/2] target/riscv: disarm timer when writing past value Radim Krčmář
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