Re: [PATCH v17 16/22] cxl/region: Factor out interleave ways setup

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

On Fri, 27 Jun 2025 16:05:20 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> On 6/27/25 2:13 AM, Jonathan Cameron wrote:
> > On Tue, 24 Jun 2025 15:13:49 +0100
> > <alejandro.lucero-palau@amd.com> wrote:
> >   
> >> From: Alejandro Lucero <alucerop@amd.com>
> >>
> >> Region creation based on Type3 devices is triggered from user space
> >> allowing memory combination through interleaving.
> >>
> >> In preparation for kernel driven region creation, that is Type2 drivers
> >> triggering region creation backed with its advertised CXL memory, factor
> >> out a common helper from the user-sysfs region setup for interleave ways.
> >>
> >> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> >> Reviewed-by: Zhi Wang <zhiw@nvidia.com>
> >> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> >> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> >> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>  
> > As a heads up, this code changes a fair bit in Dan's ACQUIRE() series
> > that may well land before this.  Dave can ask for whatever resolution he
> > wants when we get to that stage!
> > 
> >   
> We probably want to rebase on top of that. Dan has an immutable branch in cxl.git for the ACQUIRE() patch. Or are you talking about the outstanding CXL changes?
> 
The CXL specific ones from that series.

J
>