* [PATCH] iommu/amd: Enable PASID and ATS capabilities in the correct order
@ 2025-07-03 15:54 Easwar Hariharan
2025-07-04 12:51 ` Jason Gunthorpe
2025-07-05 4:31 ` Vasant Hegde
0 siblings, 2 replies; 3+ messages in thread
From: Easwar Hariharan @ 2025-07-03 15:54 UTC (permalink / raw)
To: Joerg Roedel, Suravee Suthikulpanit, Will Deacon, Robin Murphy,
Jason Gunthorpe, Vasant Hegde, Jerry Snitselaar,
open list:AMD IOMMU (AMD-VI), open list
Cc: Easwar Hariharan, Jason Gunthorpe
Per the PCIe spec, behavior of the PASID capability is undefined if the
value of the PASID Enable bit changes while the Enable bit of the
function's ATS control register is Set. Unfortunately,
pdev_enable_caps() does exactly that by ordering enabling ATS for the
device before enabling PASID.
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Vasant Hegde <vasant.hegde@amd.com>
Cc: Jason Gunthorpe <jgg@nvidia.com>
Cc: Jerry Snitselaar <jsnitsel@redhat.com>
Fixes: eda8c2860ab679 ("iommu/amd: Enable device ATS/PASID/PRI capabilities independently")
Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com>
---
drivers/iommu/amd/iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 3117d99cf83d..8b8d3e843743 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -634,8 +634,8 @@ static inline void pdev_disable_cap_pasid(struct pci_dev *pdev)
static void pdev_enable_caps(struct pci_dev *pdev)
{
- pdev_enable_cap_ats(pdev);
pdev_enable_cap_pasid(pdev);
+ pdev_enable_cap_ats(pdev);
pdev_enable_cap_pri(pdev);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] iommu/amd: Enable PASID and ATS capabilities in the correct order
2025-07-03 15:54 [PATCH] iommu/amd: Enable PASID and ATS capabilities in the correct order Easwar Hariharan
@ 2025-07-04 12:51 ` Jason Gunthorpe
2025-07-05 4:31 ` Vasant Hegde
1 sibling, 0 replies; 3+ messages in thread
From: Jason Gunthorpe @ 2025-07-04 12:51 UTC (permalink / raw)
To: Easwar Hariharan
Cc: Joerg Roedel, Suravee Suthikulpanit, Will Deacon, Robin Murphy,
Vasant Hegde, Jerry Snitselaar, open list:AMD IOMMU (AMD-VI),
open list
On Thu, Jul 03, 2025 at 08:54:33AM -0700, Easwar Hariharan wrote:
> Per the PCIe spec, behavior of the PASID capability is undefined if the
> value of the PASID Enable bit changes while the Enable bit of the
> function's ATS control register is Set. Unfortunately,
> pdev_enable_caps() does exactly that by ordering enabling ATS for the
> device before enabling PASID.
>
> Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> Cc: Vasant Hegde <vasant.hegde@amd.com>
> Cc: Jason Gunthorpe <jgg@nvidia.com>
> Cc: Jerry Snitselaar <jsnitsel@redhat.com>
> Fixes: eda8c2860ab679 ("iommu/amd: Enable device ATS/PASID/PRI capabilities independently")
> Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com>
> ---
> drivers/iommu/amd/iommu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
The other two drivers look like they do it Ok.
Jason
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] iommu/amd: Enable PASID and ATS capabilities in the correct order
2025-07-03 15:54 [PATCH] iommu/amd: Enable PASID and ATS capabilities in the correct order Easwar Hariharan
2025-07-04 12:51 ` Jason Gunthorpe
@ 2025-07-05 4:31 ` Vasant Hegde
1 sibling, 0 replies; 3+ messages in thread
From: Vasant Hegde @ 2025-07-05 4:31 UTC (permalink / raw)
To: Easwar Hariharan, Joerg Roedel, Suravee Suthikulpanit,
Will Deacon, Robin Murphy, Jason Gunthorpe, Jerry Snitselaar,
open list:AMD IOMMU (AMD-VI), open list
Cc: Jason Gunthorpe
On 7/3/2025 9:24 PM, Easwar Hariharan wrote:
> Per the PCIe spec, behavior of the PASID capability is undefined if the
> value of the PASID Enable bit changes while the Enable bit of the
> function's ATS control register is Set. Unfortunately,
> pdev_enable_caps() does exactly that by ordering enabling ATS for the
> device before enabling PASID.
> > Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> Cc: Vasant Hegde <vasant.hegde@amd.com>
> Cc: Jason Gunthorpe <jgg@nvidia.com>
> Cc: Jerry Snitselaar <jsnitsel@redhat.com>
> Fixes: eda8c2860ab679 ("iommu/amd: Enable device ATS/PASID/PRI capabilities independently")
> Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com>
Patch looks good.
Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
-Vasant
> ---
> drivers/iommu/amd/iommu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
> index 3117d99cf83d..8b8d3e843743 100644
> --- a/drivers/iommu/amd/iommu.c
> +++ b/drivers/iommu/amd/iommu.c
> @@ -634,8 +634,8 @@ static inline void pdev_disable_cap_pasid(struct pci_dev *pdev)
>
> static void pdev_enable_caps(struct pci_dev *pdev)
> {
> - pdev_enable_cap_ats(pdev);
> pdev_enable_cap_pasid(pdev);
> + pdev_enable_cap_ats(pdev);
> pdev_enable_cap_pri(pdev);
> }
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-07-03 15:54 [PATCH] iommu/amd: Enable PASID and ATS capabilities in the correct order Easwar Hariharan
2025-07-04 12:51 ` Jason Gunthorpe
2025-07-05 4:31 ` Vasant Hegde
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