From: Kane Chen via <qemu-arm@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Jamin Lin" <jamin_lin@aspeedtech.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <troy_lee@aspeedtech.com>, Kane-Chen-AS <kane_chen@aspeedtech.com>
Subject: [PATCH v4 0/5] ASPEED OTP QEMU model: block backend, machine alias, SoC integration
Date: Tue, 8 Jul 2025 13:57:52 +0800 [thread overview]
Message-ID: <20250708055810.2868680-1-kane_chen@aspeedtech.com> (raw)
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
This patch series extends the QEMU model for the ASPEED OTP (One-Time
Programmable) memory device with block backend support and tighter
integration with the SoC and machine configuration.
The OTP model simulates a simple fuse array, used in ASPEED SoCs
for secure boot and configuration purposes. The updated model now
supports loading initial OTP content from a file via the QEMU CLI.
Example usage:
./qemu-system-arm \
-machine ast2600-evb,otpmem=otp \
-blockdev driver=file,filename=otpmem.img,node-name=otp \
-global aspeed-otp.drive=otp \
...
ChangeLog
---------
v4:
- Add a 'drive' property to allow backing OTP data with a block device
- Expose a machine parameter (`-machine otpmem=XXX`) for convenient
aliasing of the OTP drive via QOM path
v3:
- Switched to object_property_set_int() for setting "size"
- Simplified qdev_realize() error handling by passing errp directly
- Added "drive" property to OTP model for future extensibility
v2:
- Rename device from 'aspeed_otpmem' to 'aspeed_otp' and move it to hw/nvram/
- Move OTP device realization from instance_init to the realize function
- Improve error logging with qemu_log_mask() and remove unused error propagation
v1:
- Initial version
---
Kane-Chen-AS (5):
hw/misc/aspeed_otp: Add ASPEED OTP memory device model
hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC
hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs
hw/misc/aspeed_otp: Add 'drive' property to support block backend
hw/misc/aspeed_sbc: Add machine parameter to alias OTP drive property
include/hw/misc/aspeed_sbc.h | 5 ++
include/hw/nvram/aspeed_otp.h | 33 ++++++++++
hw/arm/aspeed.c | 20 ++++++
hw/arm/aspeed_ast2600.c | 2 +-
hw/misc/aspeed_sbc.c | 121 ++++++++++++++++++++++++++++++++++
hw/nvram/aspeed_otp.c | 113 +++++++++++++++++++++++++++++++
hw/misc/trace-events | 5 ++
hw/nvram/meson.build | 4 ++
8 files changed, 302 insertions(+), 1 deletion(-)
create mode 100644 include/hw/nvram/aspeed_otp.h
create mode 100644 hw/nvram/aspeed_otp.c
--
2.43.0
WARNING: multiple messages have this Message-ID (diff)
From: Kane Chen via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Jamin Lin" <jamin_lin@aspeedtech.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <troy_lee@aspeedtech.com>, Kane-Chen-AS <kane_chen@aspeedtech.com>
Subject: [PATCH v4 0/5] ASPEED OTP QEMU model: block backend, machine alias, SoC integration
Date: Tue, 8 Jul 2025 13:57:52 +0800 [thread overview]
Message-ID: <20250708055810.2868680-1-kane_chen@aspeedtech.com> (raw)
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
This patch series extends the QEMU model for the ASPEED OTP (One-Time
Programmable) memory device with block backend support and tighter
integration with the SoC and machine configuration.
The OTP model simulates a simple fuse array, used in ASPEED SoCs
for secure boot and configuration purposes. The updated model now
supports loading initial OTP content from a file via the QEMU CLI.
Example usage:
./qemu-system-arm \
-machine ast2600-evb,otpmem=otp \
-blockdev driver=file,filename=otpmem.img,node-name=otp \
-global aspeed-otp.drive=otp \
...
ChangeLog
---------
v4:
- Add a 'drive' property to allow backing OTP data with a block device
- Expose a machine parameter (`-machine otpmem=XXX`) for convenient
aliasing of the OTP drive via QOM path
v3:
- Switched to object_property_set_int() for setting "size"
- Simplified qdev_realize() error handling by passing errp directly
- Added "drive" property to OTP model for future extensibility
v2:
- Rename device from 'aspeed_otpmem' to 'aspeed_otp' and move it to hw/nvram/
- Move OTP device realization from instance_init to the realize function
- Improve error logging with qemu_log_mask() and remove unused error propagation
v1:
- Initial version
---
Kane-Chen-AS (5):
hw/misc/aspeed_otp: Add ASPEED OTP memory device model
hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC
hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs
hw/misc/aspeed_otp: Add 'drive' property to support block backend
hw/misc/aspeed_sbc: Add machine parameter to alias OTP drive property
include/hw/misc/aspeed_sbc.h | 5 ++
include/hw/nvram/aspeed_otp.h | 33 ++++++++++
hw/arm/aspeed.c | 20 ++++++
hw/arm/aspeed_ast2600.c | 2 +-
hw/misc/aspeed_sbc.c | 121 ++++++++++++++++++++++++++++++++++
hw/nvram/aspeed_otp.c | 113 +++++++++++++++++++++++++++++++
hw/misc/trace-events | 5 ++
hw/nvram/meson.build | 4 ++
8 files changed, 302 insertions(+), 1 deletion(-)
create mode 100644 include/hw/nvram/aspeed_otp.h
create mode 100644 hw/nvram/aspeed_otp.c
--
2.43.0
next reply other threads:[~2025-07-08 20:46 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-08 5:57 Kane Chen via [this message]
2025-07-08 5:57 ` [PATCH v4 0/5] ASPEED OTP QEMU model: block backend, machine alias, SoC integration Kane Chen via
2025-07-08 5:57 ` [PATCH v4 1/5] hw/misc/aspeed_otp: Add ASPEED OTP memory device model Kane Chen via
2025-07-08 5:57 ` Kane Chen via
2025-07-22 9:30 ` [SPAM] " Cédric Le Goater
2025-07-22 9:54 ` Cédric Le Goater
2025-07-22 9:59 ` Kane Chen
2025-07-08 5:57 ` [PATCH v4 2/5] hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC Kane Chen via
2025-07-08 5:57 ` Kane Chen via
2025-07-08 5:57 ` [PATCH v4 3/5] hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs Kane Chen via
2025-07-08 5:57 ` Kane Chen via
2025-07-08 5:57 ` [PATCH v4 4/5] hw/misc/aspeed_otp: Add 'drive' property to support block backend Kane Chen via
2025-07-08 5:57 ` Kane Chen via
2025-07-22 9:30 ` [SPAM] " Cédric Le Goater
2025-07-22 10:27 ` Alex Bennée
2025-07-22 11:27 ` Cédric Le Goater
2025-07-08 5:57 ` [PATCH v4 5/5] hw/misc/aspeed_sbc: Add machine parameter to alias OTP drive property Kane Chen via
2025-07-08 5:57 ` Kane Chen via
2025-07-22 9:35 ` [SPAM] " Cédric Le Goater
2025-07-22 9:41 ` [SPAM] [PATCH v4 0/5] ASPEED OTP QEMU model: block backend, machine alias, SoC integration Cédric Le Goater
2025-07-22 10:03 ` Kane Chen
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