* Re: [PATCH net-next 4/5] dpll: zl3073x: Refactor DPLL initialization
@ 2025-07-28 16:11 kernel test robot
0 siblings, 0 replies; 3+ messages in thread
From: kernel test robot @ 2025-07-28 16:11 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp, Dan Carpenter
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20250725154136.1008132-5-ivecera@redhat.com>
References: <20250725154136.1008132-5-ivecera@redhat.com>
TO: Ivan Vecera <ivecera@redhat.com>
TO: netdev@vger.kernel.org
CC: Jiri Pirko <jiri@resnulli.us>
CC: Eric Dumazet <edumazet@google.com>
CC: Jakub Kicinski <kuba@kernel.org>
CC: Paolo Abeni <pabeni@redhat.com>
CC: Simon Horman <horms@kernel.org>
CC: Jonathan Corbet <corbet@lwn.net>
CC: Prathosh Satish <Prathosh.Satish@microchip.com>
CC: linux-doc@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: Michal Schmidt <mschmidt@redhat.com>
CC: Petr Oros <poros@redhat.com>
Hi Ivan,
kernel test robot noticed the following build warnings:
[auto build test WARNING on net-next/main]
url: https://github.com/intel-lab-lkp/linux/commits/Ivan-Vecera/dpll-zl3073x-Add-functions-to-access-hardware-registers/20250725-234600
base: net-next/main
patch link: https://lore.kernel.org/r/20250725154136.1008132-5-ivecera%40redhat.com
patch subject: [PATCH net-next 4/5] dpll: zl3073x: Refactor DPLL initialization
:::::: branch date: 3 days ago
:::::: commit date: 3 days ago
config: nios2-randconfig-r072-20250728 (https://download.01.org/0day-ci/archive/20250728/202507282309.ToVNHlep-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 8.5.0
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Closes: https://lore.kernel.org/r/202507282309.ToVNHlep-lkp@intel.com/
smatch warnings:
drivers/dpll/zl3073x/core.c:996 zl3073x_dev_phase_meas_setup() error: uninitialized symbol 'mask'.
vim +/mask +996 drivers/dpll/zl3073x/core.c
75a71ecc24125f Ivan Vecera 2025-07-04 958
cafbc8d62bf9bd Ivan Vecera 2025-07-25 959 /**
cafbc8d62bf9bd Ivan Vecera 2025-07-25 960 * zl3073x_dev_phase_meas_setup - setup phase offset measurement
cafbc8d62bf9bd Ivan Vecera 2025-07-25 961 * @zldev: pointer to zl3073x_dev structure
cafbc8d62bf9bd Ivan Vecera 2025-07-25 962 *
cafbc8d62bf9bd Ivan Vecera 2025-07-25 963 * Enable phase offset measurement block, set measurement averaging factor
cafbc8d62bf9bd Ivan Vecera 2025-07-25 964 * and enable DPLL-to-its-ref phase measurement for all DPLLs.
cafbc8d62bf9bd Ivan Vecera 2025-07-25 965 *
cafbc8d62bf9bd Ivan Vecera 2025-07-25 966 * Returns: 0 on success, <0 on error
cafbc8d62bf9bd Ivan Vecera 2025-07-25 967 */
cafbc8d62bf9bd Ivan Vecera 2025-07-25 968 static int
cafbc8d62bf9bd Ivan Vecera 2025-07-25 969 zl3073x_dev_phase_meas_setup(struct zl3073x_dev *zldev)
cafbc8d62bf9bd Ivan Vecera 2025-07-25 970 {
cafbc8d62bf9bd Ivan Vecera 2025-07-25 971 struct zl3073x_dpll *zldpll;
cafbc8d62bf9bd Ivan Vecera 2025-07-25 972 u8 dpll_meas_ctrl, mask;
cafbc8d62bf9bd Ivan Vecera 2025-07-25 973 int rc;
cafbc8d62bf9bd Ivan Vecera 2025-07-25 974
cafbc8d62bf9bd Ivan Vecera 2025-07-25 975 /* Read DPLL phase measurement control register */
cafbc8d62bf9bd Ivan Vecera 2025-07-25 976 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, &dpll_meas_ctrl);
cafbc8d62bf9bd Ivan Vecera 2025-07-25 977 if (rc)
cafbc8d62bf9bd Ivan Vecera 2025-07-25 978 return rc;
cafbc8d62bf9bd Ivan Vecera 2025-07-25 979
cafbc8d62bf9bd Ivan Vecera 2025-07-25 980 /* Setup phase measurement averaging factor */
cafbc8d62bf9bd Ivan Vecera 2025-07-25 981 dpll_meas_ctrl &= ~ZL_DPLL_MEAS_CTRL_AVG_FACTOR;
cafbc8d62bf9bd Ivan Vecera 2025-07-25 982 dpll_meas_ctrl |= FIELD_PREP(ZL_DPLL_MEAS_CTRL_AVG_FACTOR, 3);
cafbc8d62bf9bd Ivan Vecera 2025-07-25 983
cafbc8d62bf9bd Ivan Vecera 2025-07-25 984 /* Enable DPLL measurement block */
cafbc8d62bf9bd Ivan Vecera 2025-07-25 985 dpll_meas_ctrl |= ZL_DPLL_MEAS_CTRL_EN;
cafbc8d62bf9bd Ivan Vecera 2025-07-25 986
cafbc8d62bf9bd Ivan Vecera 2025-07-25 987 /* Update phase measurement control register */
cafbc8d62bf9bd Ivan Vecera 2025-07-25 988 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, dpll_meas_ctrl);
cafbc8d62bf9bd Ivan Vecera 2025-07-25 989 if (rc)
cafbc8d62bf9bd Ivan Vecera 2025-07-25 990 return rc;
cafbc8d62bf9bd Ivan Vecera 2025-07-25 991
cafbc8d62bf9bd Ivan Vecera 2025-07-25 992 /* Enable DPLL-to-connected-ref measurement for each channel */
cafbc8d62bf9bd Ivan Vecera 2025-07-25 993 list_for_each_entry(zldpll, &zldev->dplls, list)
cafbc8d62bf9bd Ivan Vecera 2025-07-25 994 mask |= BIT(zldpll->id);
cafbc8d62bf9bd Ivan Vecera 2025-07-25 995
cafbc8d62bf9bd Ivan Vecera 2025-07-25 @996 return zl3073x_write_u8(zldev, ZL_REG_DPLL_PHASE_ERR_READ_MASK, mask);
cafbc8d62bf9bd Ivan Vecera 2025-07-25 997 }
cafbc8d62bf9bd Ivan Vecera 2025-07-25 998
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH net-next 0/5] dpll: zl3073x: Add support for devlink flash
@ 2025-07-25 15:41 Ivan Vecera
2025-07-25 15:41 ` [PATCH net-next 4/5] dpll: zl3073x: Refactor DPLL initialization Ivan Vecera
0 siblings, 1 reply; 3+ messages in thread
From: Ivan Vecera @ 2025-07-25 15:41 UTC (permalink / raw)
To: netdev
Cc: Jiri Pirko, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Simon Horman, Jonathan Corbet, Prathosh Satish,
linux-doc, linux-kernel, Michal Schmidt, Petr Oros
Add functionality for accessing device hardware registers, loading
firmware bundles, and accessing the device's internal flash memory,
and use it to implement the devlink flash functionality.
Patch breakdown:
Patch1: helpers to access hardware registers
Patch2: low level functions to access flash memory
Patch3: support to load firmware bundles
Patch4: refactoring device initialization and helper functions
for stopping and resuming device normal operation
Patch5: devlink .flash_update callback implementation
Ivan Vecera (5):
dpll: zl3073x: Add functions to access hardware registers
dpll: zl3073x: Add low-level flash functions
dpll: zl3073x: Add firmware loading functionality
dpll: zl3073x: Refactor DPLL initialization
dpll: zl3073x: Implement devlink flash callback
Documentation/networking/devlink/zl3073x.rst | 14 +
drivers/dpll/zl3073x/Makefile | 2 +-
drivers/dpll/zl3073x/core.c | 362 +++++++---
drivers/dpll/zl3073x/core.h | 32 +
drivers/dpll/zl3073x/devlink.c | 92 ++-
drivers/dpll/zl3073x/devlink.h | 3 +
drivers/dpll/zl3073x/flash.c | 674 +++++++++++++++++++
drivers/dpll/zl3073x/flash.h | 29 +
drivers/dpll/zl3073x/fw.c | 495 ++++++++++++++
drivers/dpll/zl3073x/fw.h | 52 ++
drivers/dpll/zl3073x/regs.h | 51 ++
11 files changed, 1715 insertions(+), 91 deletions(-)
create mode 100644 drivers/dpll/zl3073x/flash.c
create mode 100644 drivers/dpll/zl3073x/flash.h
create mode 100644 drivers/dpll/zl3073x/fw.c
create mode 100644 drivers/dpll/zl3073x/fw.h
--
2.49.1
^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH net-next 4/5] dpll: zl3073x: Refactor DPLL initialization 2025-07-25 15:41 [PATCH net-next 0/5] dpll: zl3073x: Add support for devlink flash Ivan Vecera @ 2025-07-25 15:41 ` Ivan Vecera 2025-07-26 10:57 ` kernel test robot 0 siblings, 1 reply; 3+ messages in thread From: Ivan Vecera @ 2025-07-25 15:41 UTC (permalink / raw) To: netdev Cc: Jiri Pirko, David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, Simon Horman, Jonathan Corbet, Prathosh Satish, linux-doc, linux-kernel, Michal Schmidt, Petr Oros Refactor DPLL initialization and move DPLL (de)registration, monitoring control, fetching device invariant parameters and phase offset measurement block setup to separate functions. Use these new functions during device probe and teardown functions and during changes to the clock_id devlink parameter. These functions will also be used in the next patch implementing devlink flash, where this functionality is likewise required. Signed-off-by: Ivan Vecera <ivecera@redhat.com> --- drivers/dpll/zl3073x/core.c | 207 +++++++++++++++++++++------------ drivers/dpll/zl3073x/core.h | 3 + drivers/dpll/zl3073x/devlink.c | 18 +-- 3 files changed, 142 insertions(+), 86 deletions(-) diff --git a/drivers/dpll/zl3073x/core.c b/drivers/dpll/zl3073x/core.c index 86c26edc90462..b3015173d9f63 100644 --- a/drivers/dpll/zl3073x/core.c +++ b/drivers/dpll/zl3073x/core.c @@ -956,21 +956,142 @@ zl3073x_dev_periodic_work(struct kthread_work *work) msecs_to_jiffies(500)); } +/** + * zl3073x_dev_phase_meas_setup - setup phase offset measurement + * @zldev: pointer to zl3073x_dev structure + * + * Enable phase offset measurement block, set measurement averaging factor + * and enable DPLL-to-its-ref phase measurement for all DPLLs. + * + * Returns: 0 on success, <0 on error + */ +static int +zl3073x_dev_phase_meas_setup(struct zl3073x_dev *zldev) +{ + struct zl3073x_dpll *zldpll; + u8 dpll_meas_ctrl, mask; + int rc; + + /* Read DPLL phase measurement control register */ + rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, &dpll_meas_ctrl); + if (rc) + return rc; + + /* Setup phase measurement averaging factor */ + dpll_meas_ctrl &= ~ZL_DPLL_MEAS_CTRL_AVG_FACTOR; + dpll_meas_ctrl |= FIELD_PREP(ZL_DPLL_MEAS_CTRL_AVG_FACTOR, 3); + + /* Enable DPLL measurement block */ + dpll_meas_ctrl |= ZL_DPLL_MEAS_CTRL_EN; + + /* Update phase measurement control register */ + rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, dpll_meas_ctrl); + if (rc) + return rc; + + /* Enable DPLL-to-connected-ref measurement for each channel */ + list_for_each_entry(zldpll, &zldev->dplls, list) + mask |= BIT(zldpll->id); + + return zl3073x_write_u8(zldev, ZL_REG_DPLL_PHASE_ERR_READ_MASK, mask); +} + +/** + * zl3073x_dev_start - Start normal operation + * @zldev: zl3073x device pointer + * @full: perform full initialization + * + * The function starts normal operation, which means registering all DPLLs and + * their pins, and starting monitoring. If full initialization is requested, + * the function additionally initializes the phase offset measurement block and + * fetches hardware-invariant parameters. + * + * Return: 0 on success, <0 on error + */ +int zl3073x_dev_start(struct zl3073x_dev *zldev, bool full) +{ + struct zl3073x_dpll *zldpll; + int rc; + + if (full) { + /* Fetch device state */ + rc = zl3073x_dev_state_fetch(zldev); + if (rc) + return rc; + + /* Setup phase offset measurement block */ + rc = zl3073x_dev_phase_meas_setup(zldev); + if (rc) { + dev_err(zldev->dev, + "Failed to setup phase measurement\n"); + return rc; + } + } + + /* Register all DPLLs */ + list_for_each_entry(zldpll, &zldev->dplls, list) { + rc = zl3073x_dpll_register(zldpll); + if (rc) { + dev_err_probe(zldev->dev, rc, + "Failed to register DPLL%u\n", + zldpll->id); + return rc; + } + } + + /* Perform initial firmware fine phase correction */ + rc = zl3073x_dpll_init_fine_phase_adjust(zldev); + if (rc) { + dev_err_probe(zldev->dev, rc, + "Failed to init fine phase correction\n"); + return rc; + } + + /* Start monitoring */ + kthread_queue_delayed_work(zldev->kworker, &zldev->work, 0); + + return 0; +} + +/** + * zl3073x_dev_stop - Stop normal operation + * @zldev: zl3073x device pointer + * + * The function stops the normal operation that mean deregistration of all + * DPLLs and their pins and stop monitoring. + * + * Return: 0 on success, <0 on error + */ +void zl3073x_dev_stop(struct zl3073x_dev *zldev) +{ + struct zl3073x_dpll *zldpll; + + /* Stop monitoring */ + kthread_cancel_delayed_work_sync(&zldev->work); + + /* Unregister all DPLLs */ + list_for_each_entry(zldpll, &zldev->dplls, list) { + if (zldpll->dpll_dev) + zl3073x_dpll_unregister(zldpll); + } +} + static void zl3073x_dev_dpll_fini(void *ptr) { struct zl3073x_dpll *zldpll, *next; struct zl3073x_dev *zldev = ptr; - /* Stop monitoring thread */ + /* Stop monitoring and unregister DPLLs */ + zl3073x_dev_stop(zldev); + + /* Destroy monitoring thread */ if (zldev->kworker) { - kthread_cancel_delayed_work_sync(&zldev->work); kthread_destroy_worker(zldev->kworker); zldev->kworker = NULL; } - /* Release DPLLs */ + /* Free all DPLLs */ list_for_each_entry_safe(zldpll, next, &zldev->dplls, list) { - zl3073x_dpll_unregister(zldpll); list_del(&zldpll->list); zl3073x_dpll_free(zldpll); } @@ -986,7 +1107,7 @@ zl3073x_devm_dpll_init(struct zl3073x_dev *zldev, u8 num_dplls) INIT_LIST_HEAD(&zldev->dplls); - /* Initialize all DPLLs */ + /* Allocate all DPLLs */ for (i = 0; i < num_dplls; i++) { zldpll = zl3073x_dpll_alloc(zldev, i); if (IS_ERR(zldpll)) { @@ -996,25 +1117,9 @@ zl3073x_devm_dpll_init(struct zl3073x_dev *zldev, u8 num_dplls) goto error; } - rc = zl3073x_dpll_register(zldpll); - if (rc) { - dev_err_probe(zldev->dev, rc, - "Failed to register DPLL%u\n", i); - zl3073x_dpll_free(zldpll); - goto error; - } - list_add_tail(&zldpll->list, &zldev->dplls); } - /* Perform initial firmware fine phase correction */ - rc = zl3073x_dpll_init_fine_phase_adjust(zldev); - if (rc) { - dev_err_probe(zldev->dev, rc, - "Failed to init fine phase correction\n"); - goto error; - } - /* Initialize monitoring thread */ kthread_init_delayed_work(&zldev->work, zl3073x_dev_periodic_work); kworker = kthread_run_worker(0, "zl3073x-%s", dev_name(zldev->dev)); @@ -1022,9 +1127,14 @@ zl3073x_devm_dpll_init(struct zl3073x_dev *zldev, u8 num_dplls) rc = PTR_ERR(kworker); goto error; } - zldev->kworker = kworker; - kthread_queue_delayed_work(zldev->kworker, &zldev->work, 0); + + /* Start normal operation */ + rc = zl3073x_dev_start(zldev, true); + if (rc) { + dev_err_probe(zldev->dev, rc, "Failed to start device\n"); + goto error; + } /* Add devres action to release DPLL related resources */ rc = devm_add_action_or_reset(zldev->dev, zl3073x_dev_dpll_fini, zldev); @@ -1039,46 +1149,6 @@ zl3073x_devm_dpll_init(struct zl3073x_dev *zldev, u8 num_dplls) return rc; } -/** - * zl3073x_dev_phase_meas_setup - setup phase offset measurement - * @zldev: pointer to zl3073x_dev structure - * @num_channels: number of DPLL channels - * - * Enable phase offset measurement block, set measurement averaging factor - * and enable DPLL-to-its-ref phase measurement for all DPLLs. - * - * Returns: 0 on success, <0 on error - */ -static int -zl3073x_dev_phase_meas_setup(struct zl3073x_dev *zldev, int num_channels) -{ - u8 dpll_meas_ctrl, mask; - int i, rc; - - /* Read DPLL phase measurement control register */ - rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, &dpll_meas_ctrl); - if (rc) - return rc; - - /* Setup phase measurement averaging factor */ - dpll_meas_ctrl &= ~ZL_DPLL_MEAS_CTRL_AVG_FACTOR; - dpll_meas_ctrl |= FIELD_PREP(ZL_DPLL_MEAS_CTRL_AVG_FACTOR, 3); - - /* Enable DPLL measurement block */ - dpll_meas_ctrl |= ZL_DPLL_MEAS_CTRL_EN; - - /* Update phase measurement control register */ - rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, dpll_meas_ctrl); - if (rc) - return rc; - - /* Enable DPLL-to-connected-ref measurement for each channel */ - for (i = 0, mask = 0; i < num_channels; i++) - mask |= BIT(i); - - return zl3073x_write_u8(zldev, ZL_REG_DPLL_PHASE_ERR_READ_MASK, mask); -} - /** * zl3073x_dev_probe - initialize zl3073x device * @zldev: pointer to zl3073x device @@ -1146,17 +1216,6 @@ int zl3073x_dev_probe(struct zl3073x_dev *zldev, return dev_err_probe(zldev->dev, rc, "Failed to initialize mutex\n"); - /* Fetch device state */ - rc = zl3073x_dev_state_fetch(zldev); - if (rc) - return rc; - - /* Setup phase offset measurement block */ - rc = zl3073x_dev_phase_meas_setup(zldev, chip_info->num_channels); - if (rc) - return dev_err_probe(zldev->dev, rc, - "Failed to setup phase measurement\n"); - /* Register DPLL channels */ rc = zl3073x_devm_dpll_init(zldev, chip_info->num_channels); if (rc) diff --git a/drivers/dpll/zl3073x/core.h b/drivers/dpll/zl3073x/core.h index a9c098dd6d5a2..f4a6cecbbba7e 100644 --- a/drivers/dpll/zl3073x/core.h +++ b/drivers/dpll/zl3073x/core.h @@ -111,6 +111,9 @@ struct zl3073x_dev *zl3073x_devm_alloc(struct device *dev); int zl3073x_dev_probe(struct zl3073x_dev *zldev, const struct zl3073x_chip_info *chip_info); +int zl3073x_dev_start(struct zl3073x_dev *zldev, bool full); +void zl3073x_dev_stop(struct zl3073x_dev *zldev); + /********************** * Registers operations **********************/ diff --git a/drivers/dpll/zl3073x/devlink.c b/drivers/dpll/zl3073x/devlink.c index f3ca973a4d416..d0f6d9cd4a68e 100644 --- a/drivers/dpll/zl3073x/devlink.c +++ b/drivers/dpll/zl3073x/devlink.c @@ -86,14 +86,12 @@ zl3073x_devlink_reload_down(struct devlink *devlink, bool netns_change, struct netlink_ext_ack *extack) { struct zl3073x_dev *zldev = devlink_priv(devlink); - struct zl3073x_dpll *zldpll; if (action != DEVLINK_RELOAD_ACTION_DRIVER_REINIT) return -EOPNOTSUPP; - /* Unregister all DPLLs */ - list_for_each_entry(zldpll, &zldev->dplls, list) - zl3073x_dpll_unregister(zldpll); + /* Stop normal operation */ + zl3073x_dev_stop(zldev); return 0; } @@ -107,7 +105,6 @@ zl3073x_devlink_reload_up(struct devlink *devlink, { struct zl3073x_dev *zldev = devlink_priv(devlink); union devlink_param_value val; - struct zl3073x_dpll *zldpll; int rc; if (action != DEVLINK_RELOAD_ACTION_DRIVER_REINIT) @@ -125,13 +122,10 @@ zl3073x_devlink_reload_up(struct devlink *devlink, zldev->clock_id = val.vu64; } - /* Re-register all DPLLs */ - list_for_each_entry(zldpll, &zldev->dplls, list) { - rc = zl3073x_dpll_register(zldpll); - if (rc) - dev_warn(zldev->dev, - "Failed to re-register DPLL%u\n", zldpll->id); - } + /* Restart normal operation */ + rc = zl3073x_dev_start(zldev, false); + if (rc) + dev_warn(zldev->dev, "Failed to re-start normal operation\n"); *actions_performed = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT); -- 2.49.1 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH net-next 4/5] dpll: zl3073x: Refactor DPLL initialization 2025-07-25 15:41 ` [PATCH net-next 4/5] dpll: zl3073x: Refactor DPLL initialization Ivan Vecera @ 2025-07-26 10:57 ` kernel test robot 0 siblings, 0 replies; 3+ messages in thread From: kernel test robot @ 2025-07-26 10:57 UTC (permalink / raw) To: Ivan Vecera, netdev Cc: llvm, oe-kbuild-all, Jiri Pirko, Eric Dumazet, Jakub Kicinski, Paolo Abeni, Simon Horman, Jonathan Corbet, Prathosh Satish, linux-doc, linux-kernel, Michal Schmidt, Petr Oros Hi Ivan, kernel test robot noticed the following build warnings: [auto build test WARNING on net-next/main] url: https://github.com/intel-lab-lkp/linux/commits/Ivan-Vecera/dpll-zl3073x-Add-functions-to-access-hardware-registers/20250725-234600 base: net-next/main patch link: https://lore.kernel.org/r/20250725154136.1008132-5-ivecera%40redhat.com patch subject: [PATCH net-next 4/5] dpll: zl3073x: Refactor DPLL initialization config: i386-randconfig-001-20250726 (https://download.01.org/0day-ci/archive/20250726/202507261812.7458edBX-lkp@intel.com/config) compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250726/202507261812.7458edBX-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202507261812.7458edBX-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/dpll/zl3073x/core.c:994:3: warning: variable 'mask' is uninitialized when used here [-Wuninitialized] 994 | mask |= BIT(zldpll->id); | ^~~~ drivers/dpll/zl3073x/core.c:972:25: note: initialize the variable 'mask' to silence this warning 972 | u8 dpll_meas_ctrl, mask; | ^ | = '\0' 1 warning generated. vim +/mask +994 drivers/dpll/zl3073x/core.c 958 959 /** 960 * zl3073x_dev_phase_meas_setup - setup phase offset measurement 961 * @zldev: pointer to zl3073x_dev structure 962 * 963 * Enable phase offset measurement block, set measurement averaging factor 964 * and enable DPLL-to-its-ref phase measurement for all DPLLs. 965 * 966 * Returns: 0 on success, <0 on error 967 */ 968 static int 969 zl3073x_dev_phase_meas_setup(struct zl3073x_dev *zldev) 970 { 971 struct zl3073x_dpll *zldpll; 972 u8 dpll_meas_ctrl, mask; 973 int rc; 974 975 /* Read DPLL phase measurement control register */ 976 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, &dpll_meas_ctrl); 977 if (rc) 978 return rc; 979 980 /* Setup phase measurement averaging factor */ 981 dpll_meas_ctrl &= ~ZL_DPLL_MEAS_CTRL_AVG_FACTOR; 982 dpll_meas_ctrl |= FIELD_PREP(ZL_DPLL_MEAS_CTRL_AVG_FACTOR, 3); 983 984 /* Enable DPLL measurement block */ 985 dpll_meas_ctrl |= ZL_DPLL_MEAS_CTRL_EN; 986 987 /* Update phase measurement control register */ 988 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, dpll_meas_ctrl); 989 if (rc) 990 return rc; 991 992 /* Enable DPLL-to-connected-ref measurement for each channel */ 993 list_for_each_entry(zldpll, &zldev->dplls, list) > 994 mask |= BIT(zldpll->id); 995 996 return zl3073x_write_u8(zldev, ZL_REG_DPLL_PHASE_ERR_READ_MASK, mask); 997 } 998 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2025-07-28 16:11 UTC | newest] Thread overview: 3+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-07-28 16:11 [PATCH net-next 4/5] dpll: zl3073x: Refactor DPLL initialization kernel test robot -- strict thread matches above, loose matches on Subject: below -- 2025-07-25 15:41 [PATCH net-next 0/5] dpll: zl3073x: Add support for devlink flash Ivan Vecera 2025-07-25 15:41 ` [PATCH net-next 4/5] dpll: zl3073x: Refactor DPLL initialization Ivan Vecera 2025-07-26 10:57 ` kernel test robot
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