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From: Alex Elder <elder@riscstar.com>
To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org,
	bhelgaas@google.com, vkoul@kernel.org, kishon@kernel.org
Cc: dlan@gentoo.org, paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, alex@ghiti.fr, p.zabel@pengutronix.de,
	tglx@linutronix.de, johan+linaro@kernel.org,
	thippeswamy.havalige@amd.com, namcao@linutronix.de,
	mayank.rana@oss.qualcomm.com, shradha.t@samsung.com,
	inochiama@gmail.com, quic_schintav@quicinc.com,
	fan.ni@samsung.com, devicetree@vger.kernel.org,
	linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
	spacemit@lists.linux.dev, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH 2/6] dt-bindings: phy: spacemit: introduce PCIe PHY
Date: Wed, 13 Aug 2025 13:46:56 -0500	[thread overview]
Message-ID: <20250813184701.2444372-3-elder@riscstar.com> (raw)
In-Reply-To: <20250813184701.2444372-1-elder@riscstar.com>

Add the Device Tree binding for two PCIe PHYs present on the SpacemiT
K1 SoC.  These PHYs are dependent on a separate combo PHY, which
determines at probe time the calibration values used by the PCIe-only
PHYs.

Signed-off-by: Alex Elder <elder@riscstar.com>
---
 .../bindings/phy/spacemit,k1-pcie-phy.yaml    | 49 +++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
new file mode 100644
index 0000000000000..b0cbd231d9378
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/spacemit,k1-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 PCIe PHY
+
+maintainers:
+  - Alex Elder <elder@riscstar.com>
+
+description:
+  There are two PHYs on the SpacemiT K1 SoC used for PCIe (only).
+  These PHYs must be configured using calibration values that are
+  determined by a third "combo PHY".  The combo PHY determines
+  these calibration values during probe so they can be used for
+  the two PCIe-only PHYs.
+
+  During normal operation, the PCIe port driver is responsible for
+  ensuring all clocks needed by a PHY are enabled, and all resets
+  affecting the PHY are deasserted.
+
+properties:
+  compatible:
+    const: spacemit,k1-pcie-phy
+
+  reg:
+    items:
+      - description: PHY control registers
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/spacemit,k1-syscon.h>
+    pcie1_phy: phy@c0c10000 {
+        compatible = "spacemit,k1-pcie-phy";
+        reg = <0xc0c10000 0x1000>;
+        #phy-cells = <0>;
+        status = "disabled";
+    };
-- 
2.48.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: Alex Elder <elder@riscstar.com>
To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org,
	bhelgaas@google.com, vkoul@kernel.org, kishon@kernel.org
Cc: dlan@gentoo.org, paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, alex@ghiti.fr, p.zabel@pengutronix.de,
	tglx@linutronix.de, johan+linaro@kernel.org,
	thippeswamy.havalige@amd.com, namcao@linutronix.de,
	mayank.rana@oss.qualcomm.com, shradha.t@samsung.com,
	inochiama@gmail.com, quic_schintav@quicinc.com,
	fan.ni@samsung.com, devicetree@vger.kernel.org,
	linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
	spacemit@lists.linux.dev, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH 2/6] dt-bindings: phy: spacemit: introduce PCIe PHY
Date: Wed, 13 Aug 2025 13:46:56 -0500	[thread overview]
Message-ID: <20250813184701.2444372-3-elder@riscstar.com> (raw)
In-Reply-To: <20250813184701.2444372-1-elder@riscstar.com>

Add the Device Tree binding for two PCIe PHYs present on the SpacemiT
K1 SoC.  These PHYs are dependent on a separate combo PHY, which
determines at probe time the calibration values used by the PCIe-only
PHYs.

Signed-off-by: Alex Elder <elder@riscstar.com>
---
 .../bindings/phy/spacemit,k1-pcie-phy.yaml    | 49 +++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
new file mode 100644
index 0000000000000..b0cbd231d9378
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/spacemit,k1-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 PCIe PHY
+
+maintainers:
+  - Alex Elder <elder@riscstar.com>
+
+description:
+  There are two PHYs on the SpacemiT K1 SoC used for PCIe (only).
+  These PHYs must be configured using calibration values that are
+  determined by a third "combo PHY".  The combo PHY determines
+  these calibration values during probe so they can be used for
+  the two PCIe-only PHYs.
+
+  During normal operation, the PCIe port driver is responsible for
+  ensuring all clocks needed by a PHY are enabled, and all resets
+  affecting the PHY are deasserted.
+
+properties:
+  compatible:
+    const: spacemit,k1-pcie-phy
+
+  reg:
+    items:
+      - description: PHY control registers
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/spacemit,k1-syscon.h>
+    pcie1_phy: phy@c0c10000 {
+        compatible = "spacemit,k1-pcie-phy";
+        reg = <0xc0c10000 0x1000>;
+        #phy-cells = <0>;
+        status = "disabled";
+    };
-- 
2.48.1


WARNING: multiple messages have this Message-ID (diff)
From: Alex Elder <elder@riscstar.com>
To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org,
	bhelgaas@google.com, vkoul@kernel.org, kishon@kernel.org
Cc: dlan@gentoo.org, paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, alex@ghiti.fr, p.zabel@pengutronix.de,
	tglx@linutronix.de, johan+linaro@kernel.org,
	thippeswamy.havalige@amd.com, namcao@linutronix.de,
	mayank.rana@oss.qualcomm.com, shradha.t@samsung.com,
	inochiama@gmail.com, quic_schintav@quicinc.com,
	fan.ni@samsung.com, devicetree@vger.kernel.org,
	linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
	spacemit@lists.linux.dev, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH 2/6] dt-bindings: phy: spacemit: introduce PCIe PHY
Date: Wed, 13 Aug 2025 13:46:56 -0500	[thread overview]
Message-ID: <20250813184701.2444372-3-elder@riscstar.com> (raw)
In-Reply-To: <20250813184701.2444372-1-elder@riscstar.com>

Add the Device Tree binding for two PCIe PHYs present on the SpacemiT
K1 SoC.  These PHYs are dependent on a separate combo PHY, which
determines at probe time the calibration values used by the PCIe-only
PHYs.

Signed-off-by: Alex Elder <elder@riscstar.com>
---
 .../bindings/phy/spacemit,k1-pcie-phy.yaml    | 49 +++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
new file mode 100644
index 0000000000000..b0cbd231d9378
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/spacemit,k1-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 PCIe PHY
+
+maintainers:
+  - Alex Elder <elder@riscstar.com>
+
+description:
+  There are two PHYs on the SpacemiT K1 SoC used for PCIe (only).
+  These PHYs must be configured using calibration values that are
+  determined by a third "combo PHY".  The combo PHY determines
+  these calibration values during probe so they can be used for
+  the two PCIe-only PHYs.
+
+  During normal operation, the PCIe port driver is responsible for
+  ensuring all clocks needed by a PHY are enabled, and all resets
+  affecting the PHY are deasserted.
+
+properties:
+  compatible:
+    const: spacemit,k1-pcie-phy
+
+  reg:
+    items:
+      - description: PHY control registers
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/spacemit,k1-syscon.h>
+    pcie1_phy: phy@c0c10000 {
+        compatible = "spacemit,k1-pcie-phy";
+        reg = <0xc0c10000 0x1000>;
+        #phy-cells = <0>;
+        status = "disabled";
+    };
-- 
2.48.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2025-08-13 22:46 UTC|newest]

Thread overview: 93+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-13 18:46 [PATCH 0/6] Introduce SpacemiT K1 PCIe phy and host controller Alex Elder
2025-08-13 18:46 ` Alex Elder
2025-08-13 18:46 ` Alex Elder
2025-08-13 18:46 ` [PATCH 1/6] dt-bindings: phy: spacemit: add SpacemiT PCIe/combo PHY Alex Elder
2025-08-13 18:46   ` Alex Elder
2025-08-13 18:46   ` Alex Elder
2025-08-14  2:52   ` Yao Zi
2025-08-14  2:52     ` Yao Zi
2025-08-14  2:52     ` Yao Zi
2025-08-14 12:30     ` Alex Elder
2025-08-14 12:30       ` Alex Elder
2025-08-14 12:30       ` Alex Elder
2025-08-14  6:11   ` Krzysztof Kozlowski
2025-08-14  6:11     ` Krzysztof Kozlowski
2025-08-14  6:11     ` Krzysztof Kozlowski
2025-08-14 11:59     ` Alex Elder
2025-08-14 11:59       ` Alex Elder
2025-08-14 11:59       ` Alex Elder
2025-08-14 20:51   ` Rob Herring
2025-08-14 20:51     ` Rob Herring
2025-08-14 20:51     ` Rob Herring
2025-08-14 21:48     ` Alex Elder
2025-08-14 21:48       ` Alex Elder
2025-08-14 21:48       ` Alex Elder
2025-08-13 18:46 ` Alex Elder [this message]
2025-08-13 18:46   ` [PATCH 2/6] dt-bindings: phy: spacemit: introduce PCIe PHY Alex Elder
2025-08-13 18:46   ` Alex Elder
2025-08-14  6:17   ` Krzysztof Kozlowski
2025-08-14  6:17     ` Krzysztof Kozlowski
2025-08-14  6:17     ` Krzysztof Kozlowski
2025-08-13 18:46 ` [PATCH 3/6] dt-bindings: phy: spacemit: introduce PCIe root complex Alex Elder
2025-08-13 18:46   ` Alex Elder
2025-08-13 18:46   ` Alex Elder
2025-08-13 20:49   ` Rob Herring (Arm)
2025-08-13 20:49     ` Rob Herring (Arm)
2025-08-13 20:49     ` Rob Herring (Arm)
2025-08-13 21:21     ` Alex Elder
2025-08-13 21:21       ` Alex Elder
2025-08-13 21:21       ` Alex Elder
2025-09-15  8:14   ` Manivannan Sadhasivam
2025-09-15  8:14     ` Manivannan Sadhasivam
2025-09-15  8:14     ` Manivannan Sadhasivam
2025-09-19 20:14     ` Alex Elder
2025-09-19 20:14       ` Alex Elder
2025-09-19 20:14       ` Alex Elder
2025-09-20  5:55       ` Manivannan Sadhasivam
2025-09-20  5:55         ` Manivannan Sadhasivam
2025-09-20  5:55         ` Manivannan Sadhasivam
2025-10-01  2:40         ` Alex Elder
2025-10-01  2:40           ` Alex Elder
2025-10-01  2:40           ` Alex Elder
2025-08-13 18:46 ` [PATCH 4/6] phy: spacemit: introduce PCIe/combo PHY Alex Elder
2025-08-13 18:46   ` Alex Elder
2025-08-13 18:46   ` Alex Elder
2025-08-13 23:42   ` Inochi Amaoto
2025-08-13 23:42     ` Inochi Amaoto
2025-08-13 23:42     ` Inochi Amaoto
2025-08-14 12:15     ` Alex Elder
2025-08-14 12:15       ` Alex Elder
2025-08-14 12:15       ` Alex Elder
2025-08-14 22:49       ` Inochi Amaoto
2025-08-14 22:49         ` Inochi Amaoto
2025-08-14 22:49         ` Inochi Amaoto
2025-08-14 23:57       ` Yixun Lan
2025-08-14 23:57         ` Yixun Lan
2025-08-14 23:57         ` Yixun Lan
2025-08-13 18:46 ` [PATCH 5/6] PCI: spacemit: introduce SpacemiT PCIe host driver Alex Elder
2025-08-13 18:46   ` Alex Elder
2025-08-13 18:46   ` Alex Elder
2025-08-13 21:22   ` Bjorn Helgaas
2025-08-13 21:22     ` Bjorn Helgaas
2025-08-13 21:22     ` Bjorn Helgaas
2025-08-13 21:27     ` Alex Elder
2025-08-13 21:27       ` Alex Elder
2025-08-13 21:27       ` Alex Elder
2025-09-19 18:06       ` Alex Elder
2025-09-19 18:06         ` Alex Elder
2025-09-19 18:06         ` Alex Elder
2025-09-15  8:09   ` Manivannan Sadhasivam
2025-09-15  8:09     ` Manivannan Sadhasivam
2025-09-15  8:09     ` Manivannan Sadhasivam
2025-09-19 22:10     ` Alex Elder
2025-09-19 22:10       ` Alex Elder
2025-09-19 22:10       ` Alex Elder
2025-09-20  5:33       ` Manivannan Sadhasivam
2025-09-20  5:33         ` Manivannan Sadhasivam
2025-09-20  5:33         ` Manivannan Sadhasivam
2025-10-01  2:40       ` Alex Elder
2025-10-01  2:40         ` Alex Elder
2025-10-01  2:40         ` Alex Elder
2025-08-13 18:47 ` [PATCH 6/6] riscv: dts: spacemit: PCIe and PHY-related updates Alex Elder
2025-08-13 18:47   ` Alex Elder
2025-08-13 18:47   ` Alex Elder

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