From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
kvm@vger.kernel.org
Cc: Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>, Will Deacon <will@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Cornelia Huck <cohuck@redhat.com>
Subject: [PATCH v3 1/6] arm64: Add capability denoting FEAT_RASv1p1
Date: Sun, 17 Aug 2025 21:21:53 +0100 [thread overview]
Message-ID: <20250817202158.395078-2-maz@kernel.org> (raw)
In-Reply-To: <20250817202158.395078-1-maz@kernel.org>
Detecting FEAT_RASv1p1 is rather complicated, as there are two
ways for the architecture to advertise the same thing (always a
delight...).
Add a capability that will advertise this in a synthetic way to
the rest of the kernel.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kernel/cpufeature.c | 24 ++++++++++++++++++++++++
arch/arm64/tools/cpucaps | 1 +
2 files changed, 25 insertions(+)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9ad065f15f1d6..0d45c5e9b4da5 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2269,6 +2269,24 @@ static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
/* Firmware may have left a deferred SError in this register. */
write_sysreg_s(0, SYS_DISR_EL1);
}
+static bool has_rasv1p1(const struct arm64_cpu_capabilities *__unused, int scope)
+{
+ const struct arm64_cpu_capabilities rasv1p1_caps[] = {
+ {
+ ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, V1P1)
+ },
+ {
+ ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP)
+ },
+ {
+ ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, RAS_frac, RASv1p1)
+ },
+ };
+
+ return (has_cpuid_feature(&rasv1p1_caps[0], scope) ||
+ (has_cpuid_feature(&rasv1p1_caps[1], scope) &&
+ has_cpuid_feature(&rasv1p1_caps[2], scope)));
+}
#endif /* CONFIG_ARM64_RAS_EXTN */
#ifdef CONFIG_ARM64_PTR_AUTH
@@ -2687,6 +2705,12 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.cpu_enable = cpu_clear_disr,
ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP)
},
+ {
+ .desc = "RASv1p1 Extension Support",
+ .capability = ARM64_HAS_RASV1P1_EXTN,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+ .matches = has_rasv1p1,
+ },
#endif /* CONFIG_ARM64_RAS_EXTN */
#ifdef CONFIG_ARM64_AMU_EXTN
{
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index ef0b7946f5a48..9ff5cdbd27597 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -53,6 +53,7 @@ HAS_S1PIE
HAS_S1POE
HAS_SCTLR2
HAS_RAS_EXTN
+HAS_RASV1P1_EXTN
HAS_RNG
HAS_SB
HAS_STAGE2_FWB
--
2.39.2
next prev parent reply other threads:[~2025-08-17 20:22 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-17 20:21 [PATCH v3 0/6] KVM: arm64: FEAT_RASv1p1 support and RAS selection Marc Zyngier
2025-08-17 20:21 ` Marc Zyngier [this message]
2025-08-18 12:32 ` [PATCH v3 1/6] arm64: Add capability denoting FEAT_RASv1p1 Cornelia Huck
2025-08-17 20:21 ` [PATCH v3 2/6] KVM: arm64: Handle RASv1p1 registers Marc Zyngier
2025-08-18 12:34 ` Cornelia Huck
2025-08-21 13:13 ` Ben Horgan
2025-08-21 13:37 ` Marc Zyngier
2025-08-21 13:44 ` Ben Horgan
2025-08-17 20:21 ` [PATCH v3 3/6] KVM: arm64: Ignore HCR_EL2.FIEN set by L1 guest's EL2 Marc Zyngier
2025-08-19 10:24 ` Joey Gouly
2025-08-17 20:21 ` [PATCH v3 4/6] KVM: arm64: Make ID_AA64PFR0_EL1.RAS writable Marc Zyngier
2025-08-18 12:37 ` Cornelia Huck
2025-08-17 20:21 ` [PATCH v3 5/6] KVM: arm64: Make ID_AA64PFR1_EL1.RAS_frac writable Marc Zyngier
2025-08-18 12:43 ` Cornelia Huck
2025-08-17 20:21 ` [PATCH v3 6/6] KVM: arm64: Get rid of ARM64_FEATURE_MASK() Marc Zyngier
2025-08-21 11:29 ` Ben Horgan
2025-08-21 13:43 ` Marc Zyngier
2025-08-22 0:01 ` [PATCH v3 0/6] KVM: arm64: FEAT_RASv1p1 support and RAS selection Oliver Upton
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