* [PATCH 1/5] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file
2025-09-12 13:14 [PATCH 0/5] nvmem: patches for 6.18 srini
@ 2025-09-12 13:14 ` srini
2025-09-12 13:14 ` [PATCH 2/5] nvmem: s32g-ocotp: Add driver for S32G OCOTP srini
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: srini @ 2025-09-12 13:14 UTC (permalink / raw)
To: gregkh
Cc: linux-kernel, Ciprian Costea, Dan Carpenter, Rob Herring (Arm),
Srinivas Kandagatla
From: Ciprian Costea <ciprianmarian.costea@nxp.com>
Add bindings to expose the On Chip One-Time Programmable Controller
(OCOTP) for the NXP s32g chipset. There are three versions of this
chip but they're compatible so we can fall back to the nxp,s32g2-ocotp
compatible.
Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Srinivas Kandagatla <srini@kernel.org>
---
.../bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml b/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml
new file mode 100644
index 000000000000..8d46e7d28da6
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/nxp,s32g-ocotp-nvmem.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP S32G OCOTP NVMEM driver
+
+maintainers:
+ - Ciprian Costea <ciprianmarian.costea@nxp.com>
+
+description:
+ The drivers provides an interface to access One Time
+ Programmable memory pages, such as TMU fuse values.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - nxp,s32g2-ocotp
+ - items:
+ - enum:
+ - nxp,s32g3-ocotp
+ - nxp,s32r45-ocotp
+ - const: nxp,s32g2-ocotp
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+allOf:
+ - $ref: nvmem.yaml#
+
+examples:
+ - |
+ nvmem@400a4000 {
+ compatible = "nxp,s32g2-ocotp";
+ reg = <0x400a4000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
--
2.50.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/5] nvmem: s32g-ocotp: Add driver for S32G OCOTP
2025-09-12 13:14 [PATCH 0/5] nvmem: patches for 6.18 srini
2025-09-12 13:14 ` [PATCH 1/5] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file srini
@ 2025-09-12 13:14 ` srini
2025-09-12 13:14 ` [PATCH 3/5] dt-bindings: nvmem: sl28cpld: add sa67mcu compatible srini
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: srini @ 2025-09-12 13:14 UTC (permalink / raw)
To: gregkh
Cc: linux-kernel, Ciprian Costea, Ghennadi Procopciuc, Larisa Grigore,
Dan Carpenter, Srinivas Kandagatla
From: Ciprian Costea <ciprianmarian.costea@nxp.com>
Provide access to the On Chip One-Time Programmable Controller (OCOTP)
pages on the NXP S32G platform.
Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
Co-developed-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Signed-off-by: Srinivas Kandagatla <srini@kernel.org>
---
drivers/nvmem/Kconfig | 10 ++++
drivers/nvmem/Makefile | 2 +
drivers/nvmem/s32g-ocotp-nvmem.c | 100 +++++++++++++++++++++++++++++++
3 files changed, 112 insertions(+)
create mode 100644 drivers/nvmem/s32g-ocotp-nvmem.c
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index edd811444ce5..f3b8ffa77528 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -240,6 +240,16 @@ config NVMEM_NINTENDO_OTP
This driver can also be built as a module. If so, the module
will be called nvmem-nintendo-otp.
+config NVMEM_S32G_OCOTP
+ tristate "S32G SoC OCOTP support"
+ depends on ARCH_S32
+ help
+ This is a driver for the 'OCOTP' peripheral available on S32G
+ platforms.
+
+ If you say Y here, you will get support for the One Time
+ Programmable memory pages.
+
config NVMEM_QCOM_QFPROM
tristate "QCOM QFPROM Support"
depends on ARCH_QCOM || COMPILE_TEST
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 2021d59688db..5634945f8196 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -79,6 +79,8 @@ obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) += nvmem_sunplus_ocotp.o
nvmem_sunplus_ocotp-y := sunplus-ocotp.o
obj-$(CONFIG_NVMEM_SUNXI_SID) += nvmem_sunxi_sid.o
nvmem_sunxi_sid-y := sunxi_sid.o
+obj-$(CONFIG_NVMEM_S32G_OCOTP) += nvmem-s32g-ocotp-nvmem.o
+nvmem-s32g-ocotp-nvmem-y := s32g-ocotp-nvmem.o
obj-$(CONFIG_NVMEM_U_BOOT_ENV) += nvmem_u-boot-env.o
nvmem_u-boot-env-y := u-boot-env.o
obj-$(CONFIG_NVMEM_UNIPHIER_EFUSE) += nvmem-uniphier-efuse.o
diff --git a/drivers/nvmem/s32g-ocotp-nvmem.c b/drivers/nvmem/s32g-ocotp-nvmem.c
new file mode 100644
index 000000000000..119871ab3a94
--- /dev/null
+++ b/drivers/nvmem/s32g-ocotp-nvmem.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023-2025 NXP
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/nvmem-provider.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+struct s32g_ocotp_priv {
+ struct device *dev;
+ void __iomem *base;
+};
+
+static int s32g_ocotp_read(void *context, unsigned int offset,
+ void *val, size_t bytes)
+{
+ struct s32g_ocotp_priv *s32g_data = context;
+ u32 *dst = val;
+
+ while (bytes >= sizeof(u32)) {
+ *dst++ = ioread32(s32g_data->base + offset);
+
+ bytes -= sizeof(u32);
+ offset += sizeof(u32);
+ }
+
+ return 0;
+}
+
+static struct nvmem_keepout s32g_keepouts[] = {
+ { .start = 0, .end = 520 },
+ { .start = 540, .end = 564 },
+ { .start = 596, .end = 664 },
+ { .start = 668, .end = 676 },
+ { .start = 684, .end = 732 },
+ { .start = 744, .end = 864 },
+ { .start = 908, .end = 924 },
+ { .start = 928, .end = 936 },
+ { .start = 948, .end = 964 },
+ { .start = 968, .end = 976 },
+ { .start = 984, .end = 1012 },
+};
+
+static struct nvmem_config s32g_ocotp_nvmem_config = {
+ .name = "s32g-ocotp",
+ .add_legacy_fixed_of_cells = true,
+ .read_only = true,
+ .word_size = 4,
+ .reg_read = s32g_ocotp_read,
+ .keepout = s32g_keepouts,
+ .nkeepout = ARRAY_SIZE(s32g_keepouts),
+};
+
+static const struct of_device_id ocotp_of_match[] = {
+ { .compatible = "nxp,s32g2-ocotp" },
+ { /* sentinel */ }
+};
+
+static int s32g_ocotp_probe(struct platform_device *pdev)
+{
+ struct s32g_ocotp_priv *s32g_data;
+ struct device *dev = &pdev->dev;
+ struct nvmem_device *nvmem;
+ struct resource *res;
+
+ s32g_data = devm_kzalloc(dev, sizeof(*s32g_data), GFP_KERNEL);
+ if (!s32g_data)
+ return -ENOMEM;
+
+ s32g_data->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(s32g_data->base))
+ return dev_err_probe(dev, PTR_ERR(s32g_data->base),
+ "Cannot map OCOTP device.\n");
+
+ s32g_data->dev = dev;
+ s32g_ocotp_nvmem_config.dev = dev;
+ s32g_ocotp_nvmem_config.priv = s32g_data;
+ s32g_ocotp_nvmem_config.size = resource_size(res);
+
+ nvmem = devm_nvmem_register(dev, &s32g_ocotp_nvmem_config);
+
+ return PTR_ERR_OR_ZERO(nvmem);
+}
+
+static struct platform_driver s32g_ocotp_driver = {
+ .probe = s32g_ocotp_probe,
+ .driver = {
+ .name = "s32g-ocotp",
+ .of_match_table = ocotp_of_match,
+ },
+};
+module_platform_driver(s32g_ocotp_driver);
+MODULE_AUTHOR("NXP");
+MODULE_DESCRIPTION("S32G OCOTP driver");
+MODULE_LICENSE("GPL");
--
2.50.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/5] dt-bindings: nvmem: sl28cpld: add sa67mcu compatible
2025-09-12 13:14 [PATCH 0/5] nvmem: patches for 6.18 srini
2025-09-12 13:14 ` [PATCH 1/5] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file srini
2025-09-12 13:14 ` [PATCH 2/5] nvmem: s32g-ocotp: Add driver for S32G OCOTP srini
@ 2025-09-12 13:14 ` srini
2025-09-12 13:14 ` [PATCH 4/5] dt-bindings: nvmem: Document support for Airoha AN8855 Switch EFUSE srini
2025-09-12 13:14 ` [PATCH 5/5] nvmem: an8855: Add " srini
4 siblings, 0 replies; 6+ messages in thread
From: srini @ 2025-09-12 13:14 UTC (permalink / raw)
To: gregkh
Cc: linux-kernel, Michael Walle, Krzysztof Kozlowski,
Srinivas Kandagatla
From: Michael Walle <mwalle@kernel.org>
The Kontron SMARC-sAM67 has the same nvmem layout as the SMARC-sAL28. To
To be prepared for any board specific quirks, add a specific compatible.
Signed-off-by: Michael Walle <mwalle@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Srinivas Kandagatla <srini@kernel.org>
---
.../bindings/nvmem/layouts/kontron,sl28-vpd.yaml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml b/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml
index c713e23819f1..afd1919c6b1c 100644
--- a/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml
+++ b/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml
@@ -19,7 +19,12 @@ select: false
properties:
compatible:
- const: kontron,sl28-vpd
+ oneOf:
+ - items:
+ - enum:
+ - kontron,sa67-vpd
+ - const: kontron,sl28-vpd
+ - const: kontron,sl28-vpd
serial-number:
type: object
--
2.50.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 4/5] dt-bindings: nvmem: Document support for Airoha AN8855 Switch EFUSE
2025-09-12 13:14 [PATCH 0/5] nvmem: patches for 6.18 srini
` (2 preceding siblings ...)
2025-09-12 13:14 ` [PATCH 3/5] dt-bindings: nvmem: sl28cpld: add sa67mcu compatible srini
@ 2025-09-12 13:14 ` srini
2025-09-12 13:14 ` [PATCH 5/5] nvmem: an8855: Add " srini
4 siblings, 0 replies; 6+ messages in thread
From: srini @ 2025-09-12 13:14 UTC (permalink / raw)
To: gregkh
Cc: linux-kernel, Christian Marangi, Rob Herring (Arm),
Srinivas Kandagatla
From: Christian Marangi <ansuelsmth@gmail.com>
Document support for Airoha AN8855 Switch EFUSE used to calibrate
internal PHYs and store additional configuration info.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Srinivas Kandagatla <srini@kernel.org>
---
.../bindings/nvmem/airoha,an8855-efuse.yaml | 123 ++++++++++++++++++
1 file changed, 123 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml b/Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml
new file mode 100644
index 000000000000..9802d9ea2176
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/airoha,an8855-efuse.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8855 Switch EFUSE
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description:
+ Airoha AN8855 EFUSE used to calibrate internal PHYs and store additional
+ configuration info.
+
+$ref: nvmem.yaml#
+
+properties:
+ compatible:
+ const: airoha,an8855-efuse
+
+ '#nvmem-cell-cells':
+ const: 0
+
+required:
+ - compatible
+ - '#nvmem-cell-cells'
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ efuse {
+ compatible = "airoha,an8855-efuse";
+
+ #nvmem-cell-cells = <0>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ shift_sel_port0_tx_a: shift-sel-port0-tx-a@c {
+ reg = <0xc 0x4>;
+ };
+
+ shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 {
+ reg = <0x10 0x4>;
+ };
+
+ shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 {
+ reg = <0x14 0x4>;
+ };
+
+ shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 {
+ reg = <0x18 0x4>;
+ };
+
+ shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c {
+ reg = <0x1c 0x4>;
+ };
+
+ shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 {
+ reg = <0x20 0x4>;
+ };
+
+ shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 {
+ reg = <0x24 0x4>;
+ };
+
+ shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 {
+ reg = <0x28 0x4>;
+ };
+
+ shift_sel_port2_tx_a: shift-sel-port2-tx-a@2c {
+ reg = <0x2c 0x4>;
+ };
+
+ shift_sel_port2_tx_b: shift-sel-port2-tx-b@30 {
+ reg = <0x30 0x4>;
+ };
+
+ shift_sel_port2_tx_c: shift-sel-port2-tx-c@34 {
+ reg = <0x34 0x4>;
+ };
+
+ shift_sel_port2_tx_d: shift-sel-port2-tx-d@38 {
+ reg = <0x38 0x4>;
+ };
+
+ shift_sel_port3_tx_a: shift-sel-port3-tx-a@4c {
+ reg = <0x4c 0x4>;
+ };
+
+ shift_sel_port3_tx_b: shift-sel-port3-tx-b@50 {
+ reg = <0x50 0x4>;
+ };
+
+ shift_sel_port3_tx_c: shift-sel-port3-tx-c@54 {
+ reg = <0x54 0x4>;
+ };
+
+ shift_sel_port3_tx_d: shift-sel-port3-tx-d@58 {
+ reg = <0x58 0x4>;
+ };
+
+ shift_sel_port4_tx_a: shift-sel-port4-tx-a@5c {
+ reg = <0x5c 0x4>;
+ };
+
+ shift_sel_port4_tx_b: shift-sel-port4-tx-b@60 {
+ reg = <0x60 0x4>;
+ };
+
+ shift_sel_port4_tx_c: shift-sel-port4-tx-c@64 {
+ reg = <0x64 0x4>;
+ };
+
+ shift_sel_port4_tx_d: shift-sel-port4-tx-d@68 {
+ reg = <0x68 0x4>;
+ };
+ };
+ };
--
2.50.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 5/5] nvmem: an8855: Add support for Airoha AN8855 Switch EFUSE
2025-09-12 13:14 [PATCH 0/5] nvmem: patches for 6.18 srini
` (3 preceding siblings ...)
2025-09-12 13:14 ` [PATCH 4/5] dt-bindings: nvmem: Document support for Airoha AN8855 Switch EFUSE srini
@ 2025-09-12 13:14 ` srini
4 siblings, 0 replies; 6+ messages in thread
From: srini @ 2025-09-12 13:14 UTC (permalink / raw)
To: gregkh; +Cc: linux-kernel, Christian Marangi, Srinivas Kandagatla
From: Christian Marangi <ansuelsmth@gmail.com>
Add support for Airoha AN8855 Switch EFUSE. These EFUSE might be used
for calibration data for the internal switch PHYs.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Srinivas Kandagatla <srini@kernel.org>
---
drivers/nvmem/Kconfig | 11 ++++++
drivers/nvmem/Makefile | 2 ++
drivers/nvmem/an8855-efuse.c | 68 ++++++++++++++++++++++++++++++++++++
3 files changed, 81 insertions(+)
create mode 100644 drivers/nvmem/an8855-efuse.c
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index f3b8ffa77528..e0d88d3199c1 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -28,6 +28,17 @@ source "drivers/nvmem/layouts/Kconfig"
# Devices
+config NVMEM_AN8855_EFUSE
+ tristate "Airoha AN8855 eFuse support"
+ depends on MFD_AIROHA_AN8855 || COMPILE_TEST
+ help
+ Say y here to enable support for reading eFuses on Airoha AN8855
+ Switch. These are e.g. used to store factory programmed
+ calibration data required for the PHY.
+
+ This driver can also be built as a module. If so, the module will
+ be called nvmem-an8855-efuse.
+
config NVMEM_APPLE_EFUSES
tristate "Apple eFuse support"
depends on ARCH_APPLE || COMPILE_TEST
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 5634945f8196..70a4464dcb1e 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -10,6 +10,8 @@ nvmem_layouts-y := layouts.o
obj-y += layouts/
# Devices
+obj-$(CONFIG_NVMEM_AN8855_EFUSE) += nvmem-an8855-efuse.o
+nvmem-an8855-efuse-y := an8855-efuse.o
obj-$(CONFIG_NVMEM_APPLE_EFUSES) += nvmem-apple-efuses.o
nvmem-apple-efuses-y := apple-efuses.o
obj-$(CONFIG_NVMEM_APPLE_SPMI) += apple_nvmem_spmi.o
diff --git a/drivers/nvmem/an8855-efuse.c b/drivers/nvmem/an8855-efuse.c
new file mode 100644
index 000000000000..d1afde6f623f
--- /dev/null
+++ b/drivers/nvmem/an8855-efuse.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Airoha AN8855 Switch EFUSE Driver
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/nvmem-provider.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#define AN8855_EFUSE_CELL 50
+
+#define AN8855_EFUSE_DATA0 0x1000a500
+#define AN8855_EFUSE_R50O GENMASK(30, 24)
+
+static int an8855_efuse_read(void *context, unsigned int offset,
+ void *val, size_t bytes)
+{
+ struct regmap *regmap = context;
+
+ return regmap_bulk_read(regmap, AN8855_EFUSE_DATA0 + offset,
+ val, bytes / sizeof(u32));
+}
+
+static int an8855_efuse_probe(struct platform_device *pdev)
+{
+ struct nvmem_config an8855_nvmem_config = {
+ .name = "an8855-efuse",
+ .size = AN8855_EFUSE_CELL * sizeof(u32),
+ .stride = sizeof(u32),
+ .word_size = sizeof(u32),
+ .reg_read = an8855_efuse_read,
+ };
+ struct device *dev = &pdev->dev;
+ struct nvmem_device *nvmem;
+ struct regmap *regmap;
+
+ /* Assign NVMEM priv to MFD regmap */
+ regmap = dev_get_regmap(dev->parent, NULL);
+ if (!regmap)
+ return -ENOENT;
+
+ an8855_nvmem_config.priv = regmap;
+ an8855_nvmem_config.dev = dev;
+ nvmem = devm_nvmem_register(dev, &an8855_nvmem_config);
+
+ return PTR_ERR_OR_ZERO(nvmem);
+}
+
+static const struct of_device_id an8855_efuse_of_match[] = {
+ { .compatible = "airoha,an8855-efuse", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, an8855_efuse_of_match);
+
+static struct platform_driver an8855_efuse_driver = {
+ .probe = an8855_efuse_probe,
+ .driver = {
+ .name = "an8855-efuse",
+ .of_match_table = an8855_efuse_of_match,
+ },
+};
+module_platform_driver(an8855_efuse_driver);
+
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Driver for AN8855 Switch EFUSE");
+MODULE_LICENSE("GPL");
--
2.50.0
^ permalink raw reply related [flat|nested] 6+ messages in thread