From: Neha Malcom Francis <n-francis@ti.com>
To: <trini@konsulko.com>, <s-k6@ti.com>, <bb@ti.com>
Cc: <m-chawdhry@ti.com>, <u-boot@lists.denx.de>, <u-kumar1@ti.com>,
<gehariprasath@ti.com>, <n-francis@ti.com>
Subject: [PATCH v2 4/7] arm: dts: k3-j784s4: ddr: Update to v0.12.0 of DDR config tool
Date: Mon, 3 Nov 2025 12:40:32 +0530 [thread overview]
Message-ID: <20251103071035.674604-5-n-francis@ti.com> (raw)
In-Reply-To: <20251103071035.674604-1-n-francis@ti.com>
Update the DDR configuration for J784S4 according to the SysConfig
DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0
is [0].
[0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html
Tested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
---
No changes since v1
arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi | 653 ++++++++++---------
1 file changed, 341 insertions(+), 312 deletions(-)
diff --git a/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
index 0e16d2f201d..521464e2264 100644
--- a/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
+++ b/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
@@ -1,11 +1,29 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
- * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.10.0
- * This file was generated on 04/12/2023
- */
+ * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated with the following tool revisions:
+ * - SysConfig: Revision 1.25.0+4268
+ * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0
+ * This file was generated on Thu Oct 30 2025 14:55:08 GMT+0530 (India Standard Time)
+ *
+ * Multi DDR Configuration (table based on register configuration tool inputs):
+ * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
+ * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE |
+ * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~|
+ * | 0 | 8 GB | 8 GB |
+ * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~|
+ * | 1 | 8 GB | 8 GB |
+ * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~|
+ * | 2 | 8 GB | 8 GB |
+ * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~|
+ * | 3 | 8 GB | 8 GB |
+ * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
+*/
-#define DDRSS_PLL_FHS_CNT 10
+#define DDRSS_PLL_FHS_CNT 5
+#define DDRSS1_PLL_FHS_CNT 5
+#define DDRSS2_PLL_FHS_CNT 5
+#define DDRSS3_PLL_FHS_CNT 5
#define DDRSS_PLL_FREQUENCY_0 27500000
#define DDRSS_PLL_FREQUENCY_1 1066500000
#define DDRSS_PLL_FREQUENCY_2 1066500000
@@ -16,6 +34,17 @@
#define MULTI_DDR_CFG_HYBRID_SELECT 24
#define MULTI_DDR_CFG_EMIFS_ACTIVE 15
+#define DDR0_CTL_NODE_STAT okay
+#define DDR1_CTL_NODE_STAT okay
+#define DDR2_CTL_NODE_STAT okay
+#define DDR3_CTL_NODE_STAT okay
+
+#define DDR_REG0_SIZE_MSB 0x00000000
+#define DDR_REG0_SIZE_LSB 0x80000000
+#define DDR_REG1_SIZE_MSB 0x00000007
+#define DDR_REG1_SIZE_LSB 0x80000000
+
+
#define DDRSS0_CTL_00_DATA 0x00000B00
#define DDRSS0_CTL_01_DATA 0x00000000
#define DDRSS0_CTL_02_DATA 0x00000000
@@ -36,7 +65,7 @@
#define DDRSS0_CTL_17_DATA 0x00000005
#define DDRSS0_CTL_18_DATA 0x000010A9
#define DDRSS0_CTL_19_DATA 0x01010000
-#define DDRSS0_CTL_20_DATA 0x02011001
+#define DDRSS0_CTL_20_DATA 0x01011001
#define DDRSS0_CTL_21_DATA 0x02010000
#define DDRSS0_CTL_22_DATA 0x00020100
#define DDRSS0_CTL_23_DATA 0x0000000B
@@ -51,7 +80,7 @@
#define DDRSS0_CTL_32_DATA 0x00000000
#define DDRSS0_CTL_33_DATA 0x00000000
#define DDRSS0_CTL_34_DATA 0x040C0000
-#define DDRSS0_CTL_35_DATA 0x12481248
+#define DDRSS0_CTL_35_DATA 0x12501250
#define DDRSS0_CTL_36_DATA 0x00050804
#define DDRSS0_CTL_37_DATA 0x09040008
#define DDRSS0_CTL_38_DATA 0x15000204
@@ -66,27 +95,27 @@
#define DDRSS0_CTL_47_DATA 0x1E161110
#define DDRSS0_CTL_48_DATA 0x1000922C
#define DDRSS0_CTL_49_DATA 0x02030410
-#define DDRSS0_CTL_50_DATA 0x2C040500
+#define DDRSS0_CTL_50_DATA 0x2C060500
#define DDRSS0_CTL_51_DATA 0x08292C29
#define DDRSS0_CTL_52_DATA 0x14000E0A
#define DDRSS0_CTL_53_DATA 0x04010A0A
#define DDRSS0_CTL_54_DATA 0x01010004
-#define DDRSS0_CTL_55_DATA 0x04545408
+#define DDRSS0_CTL_55_DATA 0x0454540A
#define DDRSS0_CTL_56_DATA 0x04313104
#define DDRSS0_CTL_57_DATA 0x00003131
#define DDRSS0_CTL_58_DATA 0x00010100
#define DDRSS0_CTL_59_DATA 0x03010000
#define DDRSS0_CTL_60_DATA 0x00001508
-#define DDRSS0_CTL_61_DATA 0x00000063
+#define DDRSS0_CTL_61_DATA 0x00000068
#define DDRSS0_CTL_62_DATA 0x0000032B
#define DDRSS0_CTL_63_DATA 0x00001035
#define DDRSS0_CTL_64_DATA 0x0000032B
#define DDRSS0_CTL_65_DATA 0x00001035
#define DDRSS0_CTL_66_DATA 0x00000005
#define DDRSS0_CTL_67_DATA 0x00050000
-#define DDRSS0_CTL_68_DATA 0x00CB0012
-#define DDRSS0_CTL_69_DATA 0x00CB0408
-#define DDRSS0_CTL_70_DATA 0x00400408
+#define DDRSS0_CTL_68_DATA 0x00CB0005
+#define DDRSS0_CTL_69_DATA 0x00CB0200
+#define DDRSS0_CTL_70_DATA 0x00400200
#define DDRSS0_CTL_71_DATA 0x00120103
#define DDRSS0_CTL_72_DATA 0x00100005
#define DDRSS0_CTL_73_DATA 0x2F080010
@@ -192,22 +221,22 @@
#define DDRSS0_CTL_173_DATA 0x00000000
#define DDRSS0_CTL_174_DATA 0x00000000
#define DDRSS0_CTL_175_DATA 0x3FF40084
-#define DDRSS0_CTL_176_DATA 0x33003FF4
-#define DDRSS0_CTL_177_DATA 0x00003333
+#define DDRSS0_CTL_176_DATA 0xF3003FF4
+#define DDRSS0_CTL_177_DATA 0x0000F3F3
#define DDRSS0_CTL_178_DATA 0x35000000
#define DDRSS0_CTL_179_DATA 0x27270035
#define DDRSS0_CTL_180_DATA 0x0F0F0000
#define DDRSS0_CTL_181_DATA 0x16000000
#define DDRSS0_CTL_182_DATA 0x00841616
#define DDRSS0_CTL_183_DATA 0x3FF43FF4
-#define DDRSS0_CTL_184_DATA 0x33333300
+#define DDRSS0_CTL_184_DATA 0xF3F3F300
#define DDRSS0_CTL_185_DATA 0x00000000
#define DDRSS0_CTL_186_DATA 0x00353500
#define DDRSS0_CTL_187_DATA 0x00002727
#define DDRSS0_CTL_188_DATA 0x00000F0F
#define DDRSS0_CTL_189_DATA 0x16161600
#define DDRSS0_CTL_190_DATA 0x00000020
-#define DDRSS0_CTL_191_DATA 0x00000000
+#define DDRSS0_CTL_191_DATA 0x01000000
#define DDRSS0_CTL_192_DATA 0x00000001
#define DDRSS0_CTL_193_DATA 0x00000000
#define DDRSS0_CTL_194_DATA 0x01000000
@@ -307,14 +336,14 @@
#define DDRSS0_CTL_288_DATA 0x00000000
#define DDRSS0_CTL_289_DATA 0x00000000
#define DDRSS0_CTL_290_DATA 0x03030300
-#define DDRSS0_CTL_291_DATA 0x00000001
+#define DDRSS0_CTL_291_DATA 0x00010101
#define DDRSS0_CTL_292_DATA 0x00000000
#define DDRSS0_CTL_293_DATA 0x00000000
#define DDRSS0_CTL_294_DATA 0x00000000
#define DDRSS0_CTL_295_DATA 0x00000000
#define DDRSS0_CTL_296_DATA 0x00000000
-#define DDRSS0_CTL_297_DATA 0x00000000
-#define DDRSS0_CTL_298_DATA 0x00000000
+#define DDRSS0_CTL_297_DATA 0xFFFFFFFF
+#define DDRSS0_CTL_298_DATA 0x00000FFF
#define DDRSS0_CTL_299_DATA 0x00000000
#define DDRSS0_CTL_300_DATA 0x00000000
#define DDRSS0_CTL_301_DATA 0x00000000
@@ -335,7 +364,7 @@
#define DDRSS0_CTL_316_DATA 0x01010001
#define DDRSS0_CTL_317_DATA 0x00010101
#define DDRSS0_CTL_318_DATA 0x050A0A03
-#define DDRSS0_CTL_319_DATA 0x10081F1F
+#define DDRSS0_CTL_319_DATA 0x10082323
#define DDRSS0_CTL_320_DATA 0x00090310
#define DDRSS0_CTL_321_DATA 0x0B0C030F
#define DDRSS0_CTL_322_DATA 0x0B0C0306
@@ -410,7 +439,7 @@
#define DDRSS0_CTL_391_DATA 0x00000200
#define DDRSS0_CTL_392_DATA 0x00000200
#define DDRSS0_CTL_393_DATA 0x00000200
-#define DDRSS0_CTL_394_DATA 0x00000252
+#define DDRSS0_CTL_394_DATA 0x00000270
#define DDRSS0_CTL_395_DATA 0x000007BC
#define DDRSS0_CTL_396_DATA 0x00000204
#define DDRSS0_CTL_397_DATA 0x0000206A
@@ -420,7 +449,7 @@
#define DDRSS0_CTL_401_DATA 0x00000200
#define DDRSS0_CTL_402_DATA 0x0000613E
#define DDRSS0_CTL_403_DATA 0x00014424
-#define DDRSS0_CTL_404_DATA 0x00000E15
+#define DDRSS0_CTL_404_DATA 0x00000E19
#define DDRSS0_CTL_405_DATA 0x0000206A
#define DDRSS0_CTL_406_DATA 0x00000200
#define DDRSS0_CTL_407_DATA 0x00000200
@@ -428,7 +457,7 @@
#define DDRSS0_CTL_409_DATA 0x00000200
#define DDRSS0_CTL_410_DATA 0x0000613E
#define DDRSS0_CTL_411_DATA 0x00014424
-#define DDRSS0_CTL_412_DATA 0x02020E15
+#define DDRSS0_CTL_412_DATA 0x02020E19
#define DDRSS0_CTL_413_DATA 0x03030202
#define DDRSS0_CTL_414_DATA 0x00000022
#define DDRSS0_CTL_415_DATA 0x00000000
@@ -445,7 +474,7 @@
#define DDRSS0_CTL_426_DATA 0x00000000
#define DDRSS0_CTL_427_DATA 0x02000000
#define DDRSS0_CTL_428_DATA 0x01000404
-#define DDRSS0_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS0_CTL_429_DATA 0x0B220B22
#define DDRSS0_CTL_430_DATA 0x00000105
#define DDRSS0_CTL_431_DATA 0x00010101
#define DDRSS0_CTL_432_DATA 0x00010101
@@ -488,8 +517,8 @@
#define DDRSS0_PI_09_DATA 0x00000000
#define DDRSS0_PI_10_DATA 0x00000000
#define DDRSS0_PI_11_DATA 0x00000000
-#define DDRSS0_PI_12_DATA 0x00000007
-#define DDRSS0_PI_13_DATA 0x00010002
+#define DDRSS0_PI_12_DATA 0x00000003
+#define DDRSS0_PI_13_DATA 0x00010001
#define DDRSS0_PI_14_DATA 0x0800000F
#define DDRSS0_PI_15_DATA 0x00000103
#define DDRSS0_PI_16_DATA 0x00000005
@@ -537,18 +566,18 @@
#define DDRSS0_PI_58_DATA 0x00000000
#define DDRSS0_PI_59_DATA 0x00000000
#define DDRSS0_PI_60_DATA 0x0A0A140A
-#define DDRSS0_PI_61_DATA 0x10020101
+#define DDRSS0_PI_61_DATA 0x10020201
#define DDRSS0_PI_62_DATA 0x00020805
#define DDRSS0_PI_63_DATA 0x01000404
#define DDRSS0_PI_64_DATA 0x00000000
#define DDRSS0_PI_65_DATA 0x00000000
#define DDRSS0_PI_66_DATA 0x00000100
-#define DDRSS0_PI_67_DATA 0x0001010F
+#define DDRSS0_PI_67_DATA 0x0002020F
#define DDRSS0_PI_68_DATA 0x00340000
#define DDRSS0_PI_69_DATA 0x00000000
#define DDRSS0_PI_70_DATA 0x00000000
#define DDRSS0_PI_71_DATA 0x0000FFFF
-#define DDRSS0_PI_72_DATA 0x00000000
+#define DDRSS0_PI_72_DATA 0x01000000
#define DDRSS0_PI_73_DATA 0x00080000
#define DDRSS0_PI_74_DATA 0x02000200
#define DDRSS0_PI_75_DATA 0x01000100
@@ -637,37 +666,37 @@
#define DDRSS0_PI_158_DATA 0x00000000
#define DDRSS0_PI_159_DATA 0x00000401
#define DDRSS0_PI_160_DATA 0x00000000
-#define DDRSS0_PI_161_DATA 0x00010000
-#define DDRSS0_PI_162_DATA 0x00000000
-#define DDRSS0_PI_163_DATA 0x2B2B0200
+#define DDRSS0_PI_161_DATA 0x05010000
+#define DDRSS0_PI_162_DATA 0x00000001
+#define DDRSS0_PI_163_DATA 0x2B2B0201
#define DDRSS0_PI_164_DATA 0x00000034
-#define DDRSS0_PI_165_DATA 0x00000064
-#define DDRSS0_PI_166_DATA 0x00020064
+#define DDRSS0_PI_165_DATA 0x00000068
+#define DDRSS0_PI_166_DATA 0x00020068
#define DDRSS0_PI_167_DATA 0x02000200
-#define DDRSS0_PI_168_DATA 0x48120C04
-#define DDRSS0_PI_169_DATA 0x00154812
-#define DDRSS0_PI_170_DATA 0x00000063
+#define DDRSS0_PI_168_DATA 0x50120C04
+#define DDRSS0_PI_169_DATA 0x00155012
+#define DDRSS0_PI_170_DATA 0x00000068
#define DDRSS0_PI_171_DATA 0x0000032B
#define DDRSS0_PI_172_DATA 0x00001035
#define DDRSS0_PI_173_DATA 0x0000032B
#define DDRSS0_PI_174_DATA 0x04001035
#define DDRSS0_PI_175_DATA 0x01010404
-#define DDRSS0_PI_176_DATA 0x00001501
+#define DDRSS0_PI_176_DATA 0x00001500
#define DDRSS0_PI_177_DATA 0x00150015
#define DDRSS0_PI_178_DATA 0x01000100
#define DDRSS0_PI_179_DATA 0x00000100
#define DDRSS0_PI_180_DATA 0x00000000
#define DDRSS0_PI_181_DATA 0x01010101
-#define DDRSS0_PI_182_DATA 0x00000101
+#define DDRSS0_PI_182_DATA 0x00000000
#define DDRSS0_PI_183_DATA 0x00000000
#define DDRSS0_PI_184_DATA 0x00000000
-#define DDRSS0_PI_185_DATA 0x15040000
-#define DDRSS0_PI_186_DATA 0x0E0E0215
+#define DDRSS0_PI_185_DATA 0x19040000
+#define DDRSS0_PI_186_DATA 0x0E0E0219
#define DDRSS0_PI_187_DATA 0x00040402
#define DDRSS0_PI_188_DATA 0x000D0035
#define DDRSS0_PI_189_DATA 0x00218049
#define DDRSS0_PI_190_DATA 0x00218049
-#define DDRSS0_PI_191_DATA 0x01010101
+#define DDRSS0_PI_191_DATA 0x01000101
#define DDRSS0_PI_192_DATA 0x0004000E
#define DDRSS0_PI_193_DATA 0x00040216
#define DDRSS0_PI_194_DATA 0x01000216
@@ -675,8 +704,8 @@
#define DDRSS0_PI_196_DATA 0x02170100
#define DDRSS0_PI_197_DATA 0x01000217
#define DDRSS0_PI_198_DATA 0x02170217
-#define DDRSS0_PI_199_DATA 0x32103200
-#define DDRSS0_PI_200_DATA 0x01013210
+#define DDRSS0_PI_199_DATA 0x2F1B3200
+#define DDRSS0_PI_200_DATA 0x01012F1B
#define DDRSS0_PI_201_DATA 0x0A070601
#define DDRSS0_PI_202_DATA 0x1F130A0D
#define DDRSS0_PI_203_DATA 0x1F130A14
@@ -688,13 +717,13 @@
#define DDRSS0_PI_209_DATA 0x00240216
#define DDRSS0_PI_210_DATA 0x00110216
#define DDRSS0_PI_211_DATA 0x32000056
-#define DDRSS0_PI_212_DATA 0x00000301
-#define DDRSS0_PI_213_DATA 0x005B0036
+#define DDRSS0_PI_212_DATA 0x00000101
+#define DDRSS0_PI_213_DATA 0x005F0036
#define DDRSS0_PI_214_DATA 0x03013212
#define DDRSS0_PI_215_DATA 0x00003600
-#define DDRSS0_PI_216_DATA 0x3212005B
-#define DDRSS0_PI_217_DATA 0x09000301
-#define DDRSS0_PI_218_DATA 0x04010504
+#define DDRSS0_PI_216_DATA 0x3212005F
+#define DDRSS0_PI_217_DATA 0x09000001
+#define DDRSS0_PI_218_DATA 0x06010504
#define DDRSS0_PI_219_DATA 0x04000364
#define DDRSS0_PI_220_DATA 0x0A032001
#define DDRSS0_PI_221_DATA 0x2C31110A
@@ -751,29 +780,29 @@
#define DDRSS0_PI_272_DATA 0x00080804
#define DDRSS0_PI_273_DATA 0x00000000
#define DDRSS0_PI_274_DATA 0x00000000
-#define DDRSS0_PI_275_DATA 0x00330084
+#define DDRSS0_PI_275_DATA 0x00F30084
#define DDRSS0_PI_276_DATA 0x00160000
-#define DDRSS0_PI_277_DATA 0x35333FF4
+#define DDRSS0_PI_277_DATA 0x35F33FF4
#define DDRSS0_PI_278_DATA 0x00160F27
-#define DDRSS0_PI_279_DATA 0x35333FF4
+#define DDRSS0_PI_279_DATA 0x35F33FF4
#define DDRSS0_PI_280_DATA 0x00160F27
-#define DDRSS0_PI_281_DATA 0x00330084
+#define DDRSS0_PI_281_DATA 0x00F30084
#define DDRSS0_PI_282_DATA 0x00160000
-#define DDRSS0_PI_283_DATA 0x35333FF4
+#define DDRSS0_PI_283_DATA 0x35F33FF4
#define DDRSS0_PI_284_DATA 0x00160F27
-#define DDRSS0_PI_285_DATA 0x35333FF4
+#define DDRSS0_PI_285_DATA 0x35F33FF4
#define DDRSS0_PI_286_DATA 0x00160F27
-#define DDRSS0_PI_287_DATA 0x00330084
+#define DDRSS0_PI_287_DATA 0x00F30084
#define DDRSS0_PI_288_DATA 0x00160000
-#define DDRSS0_PI_289_DATA 0x35333FF4
+#define DDRSS0_PI_289_DATA 0x35F33FF4
#define DDRSS0_PI_290_DATA 0x00160F27
-#define DDRSS0_PI_291_DATA 0x35333FF4
+#define DDRSS0_PI_291_DATA 0x35F33FF4
#define DDRSS0_PI_292_DATA 0x00160F27
-#define DDRSS0_PI_293_DATA 0x00330084
+#define DDRSS0_PI_293_DATA 0x00F30084
#define DDRSS0_PI_294_DATA 0x00160000
-#define DDRSS0_PI_295_DATA 0x35333FF4
+#define DDRSS0_PI_295_DATA 0x35F33FF4
#define DDRSS0_PI_296_DATA 0x00160F27
-#define DDRSS0_PI_297_DATA 0x35333FF4
+#define DDRSS0_PI_297_DATA 0x35F33FF4
#define DDRSS0_PI_298_DATA 0x00160F27
#define DDRSS0_PI_299_DATA 0x00000000
@@ -789,7 +818,7 @@
#define DDRSS0_PHY_09_DATA 0x00000000
#define DDRSS0_PHY_10_DATA 0x00000000
#define DDRSS0_PHY_11_DATA 0x01000001
-#define DDRSS0_PHY_12_DATA 0x00000100
+#define DDRSS0_PHY_12_DATA 0x00000200
#define DDRSS0_PHY_13_DATA 0x000800C0
#define DDRSS0_PHY_14_DATA 0x060100CC
#define DDRSS0_PHY_15_DATA 0x00030066
@@ -808,7 +837,7 @@
#define DDRSS0_PHY_28_DATA 0x2A000000
#define DDRSS0_PHY_29_DATA 0x00000808
#define DDRSS0_PHY_30_DATA 0x0F000000
-#define DDRSS0_PHY_31_DATA 0x00000F0F
+#define DDRSS0_PHY_31_DATA 0x00000F08
#define DDRSS0_PHY_32_DATA 0x10400000
#define DDRSS0_PHY_33_DATA 0x0C002006
#define DDRSS0_PHY_34_DATA 0x00000000
@@ -877,9 +906,9 @@
#define DDRSS0_PHY_97_DATA 0x00050010
#define DDRSS0_PHY_98_DATA 0x51517041
#define DDRSS0_PHY_99_DATA 0x31C06001
-#define DDRSS0_PHY_100_DATA 0x07AB0340
+#define DDRSS0_PHY_100_DATA 0x07AB01AB
#define DDRSS0_PHY_101_DATA 0x00C0C001
-#define DDRSS0_PHY_102_DATA 0x0E0D0001
+#define DDRSS0_PHY_102_DATA 0x0E0D0101
#define DDRSS0_PHY_103_DATA 0x10001000
#define DDRSS0_PHY_104_DATA 0x0C083E42
#define DDRSS0_PHY_105_DATA 0x0F0C3701
@@ -1045,7 +1074,7 @@
#define DDRSS0_PHY_265_DATA 0x00000000
#define DDRSS0_PHY_266_DATA 0x00000000
#define DDRSS0_PHY_267_DATA 0x01000001
-#define DDRSS0_PHY_268_DATA 0x00000100
+#define DDRSS0_PHY_268_DATA 0x00000200
#define DDRSS0_PHY_269_DATA 0x000800C0
#define DDRSS0_PHY_270_DATA 0x060100CC
#define DDRSS0_PHY_271_DATA 0x00030066
@@ -1064,7 +1093,7 @@
#define DDRSS0_PHY_284_DATA 0x2A000000
#define DDRSS0_PHY_285_DATA 0x00000808
#define DDRSS0_PHY_286_DATA 0x0F000000
-#define DDRSS0_PHY_287_DATA 0x00000F0F
+#define DDRSS0_PHY_287_DATA 0x00000F08
#define DDRSS0_PHY_288_DATA 0x10400000
#define DDRSS0_PHY_289_DATA 0x0C002006
#define DDRSS0_PHY_290_DATA 0x00000000
@@ -1133,9 +1162,9 @@
#define DDRSS0_PHY_353_DATA 0x00050010
#define DDRSS0_PHY_354_DATA 0x51517041
#define DDRSS0_PHY_355_DATA 0x31C06001
-#define DDRSS0_PHY_356_DATA 0x07AB0340
+#define DDRSS0_PHY_356_DATA 0x07AB01AB
#define DDRSS0_PHY_357_DATA 0x00C0C001
-#define DDRSS0_PHY_358_DATA 0x0E0D0001
+#define DDRSS0_PHY_358_DATA 0x0E0D0101
#define DDRSS0_PHY_359_DATA 0x10001000
#define DDRSS0_PHY_360_DATA 0x0C083E42
#define DDRSS0_PHY_361_DATA 0x0F0C3701
@@ -1301,7 +1330,7 @@
#define DDRSS0_PHY_521_DATA 0x00000000
#define DDRSS0_PHY_522_DATA 0x00000000
#define DDRSS0_PHY_523_DATA 0x01000001
-#define DDRSS0_PHY_524_DATA 0x00000100
+#define DDRSS0_PHY_524_DATA 0x00000200
#define DDRSS0_PHY_525_DATA 0x000800C0
#define DDRSS0_PHY_526_DATA 0x060100CC
#define DDRSS0_PHY_527_DATA 0x00030066
@@ -1320,7 +1349,7 @@
#define DDRSS0_PHY_540_DATA 0x2A000000
#define DDRSS0_PHY_541_DATA 0x00000808
#define DDRSS0_PHY_542_DATA 0x0F000000
-#define DDRSS0_PHY_543_DATA 0x00000F0F
+#define DDRSS0_PHY_543_DATA 0x00000F08
#define DDRSS0_PHY_544_DATA 0x10400000
#define DDRSS0_PHY_545_DATA 0x0C002006
#define DDRSS0_PHY_546_DATA 0x00000000
@@ -1389,9 +1418,9 @@
#define DDRSS0_PHY_609_DATA 0x00050010
#define DDRSS0_PHY_610_DATA 0x51517041
#define DDRSS0_PHY_611_DATA 0x31C06001
-#define DDRSS0_PHY_612_DATA 0x07AB0340
+#define DDRSS0_PHY_612_DATA 0x07AB01AB
#define DDRSS0_PHY_613_DATA 0x00C0C001
-#define DDRSS0_PHY_614_DATA 0x0E0D0001
+#define DDRSS0_PHY_614_DATA 0x0E0D0101
#define DDRSS0_PHY_615_DATA 0x10001000
#define DDRSS0_PHY_616_DATA 0x0C083E42
#define DDRSS0_PHY_617_DATA 0x0F0C3701
@@ -1557,7 +1586,7 @@
#define DDRSS0_PHY_777_DATA 0x00000000
#define DDRSS0_PHY_778_DATA 0x00000000
#define DDRSS0_PHY_779_DATA 0x01000001
-#define DDRSS0_PHY_780_DATA 0x00000100
+#define DDRSS0_PHY_780_DATA 0x00000200
#define DDRSS0_PHY_781_DATA 0x000800C0
#define DDRSS0_PHY_782_DATA 0x060100CC
#define DDRSS0_PHY_783_DATA 0x00030066
@@ -1576,7 +1605,7 @@
#define DDRSS0_PHY_796_DATA 0x2A000000
#define DDRSS0_PHY_797_DATA 0x00000808
#define DDRSS0_PHY_798_DATA 0x0F000000
-#define DDRSS0_PHY_799_DATA 0x00000F0F
+#define DDRSS0_PHY_799_DATA 0x00000F08
#define DDRSS0_PHY_800_DATA 0x10400000
#define DDRSS0_PHY_801_DATA 0x0C002006
#define DDRSS0_PHY_802_DATA 0x00000000
@@ -1645,9 +1674,9 @@
#define DDRSS0_PHY_865_DATA 0x00050010
#define DDRSS0_PHY_866_DATA 0x51517041
#define DDRSS0_PHY_867_DATA 0x31C06001
-#define DDRSS0_PHY_868_DATA 0x07AB0340
+#define DDRSS0_PHY_868_DATA 0x07AB01AB
#define DDRSS0_PHY_869_DATA 0x00C0C001
-#define DDRSS0_PHY_870_DATA 0x0E0D0001
+#define DDRSS0_PHY_870_DATA 0x0E0D0101
#define DDRSS0_PHY_871_DATA 0x10001000
#define DDRSS0_PHY_872_DATA 0x0C083E42
#define DDRSS0_PHY_873_DATA 0x0F0C3701
@@ -1832,7 +1861,7 @@
#define DDRSS0_PHY_1052_DATA 0x00000033
#define DDRSS0_PHY_1053_DATA 0x00543210
#define DDRSS0_PHY_1054_DATA 0x003F0000
-#define DDRSS0_PHY_1055_DATA 0x000F013F
+#define DDRSS0_PHY_1055_DATA 0x000F3F3F
#define DDRSS0_PHY_1056_DATA 0x20202003
#define DDRSS0_PHY_1057_DATA 0x00202020
#define DDRSS0_PHY_1058_DATA 0x20008008
@@ -2080,7 +2109,7 @@
#define DDRSS0_PHY_1300_DATA 0x00040101
#define DDRSS0_PHY_1301_DATA 0x0000010F
#define DDRSS0_PHY_1302_DATA 0x00000000
-#define DDRSS0_PHY_1303_DATA 0x0000FFFF
+#define DDRSS0_PHY_1303_DATA 0x00000064
#define DDRSS0_PHY_1304_DATA 0x00000000
#define DDRSS0_PHY_1305_DATA 0x01010000
#define DDRSS0_PHY_1306_DATA 0x01080402
@@ -2174,7 +2203,7 @@
#define DDRSS0_PHY_1394_DATA 0x00000003
#define DDRSS0_PHY_1395_DATA 0x00000000
#define DDRSS0_PHY_1396_DATA 0x00001142
-#define DDRSS0_PHY_1397_DATA 0x010207AB
+#define DDRSS0_PHY_1397_DATA 0x040207AB
#define DDRSS0_PHY_1398_DATA 0x01000080
#define DDRSS0_PHY_1399_DATA 0x03900390
#define DDRSS0_PHY_1400_DATA 0x03900390
@@ -2221,7 +2250,7 @@
#define DDRSS1_CTL_17_DATA 0x00000005
#define DDRSS1_CTL_18_DATA 0x000010A9
#define DDRSS1_CTL_19_DATA 0x01010000
-#define DDRSS1_CTL_20_DATA 0x02011001
+#define DDRSS1_CTL_20_DATA 0x01011001
#define DDRSS1_CTL_21_DATA 0x02010000
#define DDRSS1_CTL_22_DATA 0x00020100
#define DDRSS1_CTL_23_DATA 0x0000000B
@@ -2236,7 +2265,7 @@
#define DDRSS1_CTL_32_DATA 0x00000000
#define DDRSS1_CTL_33_DATA 0x00000000
#define DDRSS1_CTL_34_DATA 0x040C0000
-#define DDRSS1_CTL_35_DATA 0x12481248
+#define DDRSS1_CTL_35_DATA 0x12501250
#define DDRSS1_CTL_36_DATA 0x00050804
#define DDRSS1_CTL_37_DATA 0x09040008
#define DDRSS1_CTL_38_DATA 0x15000204
@@ -2251,27 +2280,27 @@
#define DDRSS1_CTL_47_DATA 0x1E161110
#define DDRSS1_CTL_48_DATA 0x1000922C
#define DDRSS1_CTL_49_DATA 0x02030410
-#define DDRSS1_CTL_50_DATA 0x2C040500
+#define DDRSS1_CTL_50_DATA 0x2C060500
#define DDRSS1_CTL_51_DATA 0x08292C29
#define DDRSS1_CTL_52_DATA 0x14000E0A
#define DDRSS1_CTL_53_DATA 0x04010A0A
#define DDRSS1_CTL_54_DATA 0x01010004
-#define DDRSS1_CTL_55_DATA 0x04545408
+#define DDRSS1_CTL_55_DATA 0x0454540A
#define DDRSS1_CTL_56_DATA 0x04313104
#define DDRSS1_CTL_57_DATA 0x00003131
#define DDRSS1_CTL_58_DATA 0x00010100
#define DDRSS1_CTL_59_DATA 0x03010000
#define DDRSS1_CTL_60_DATA 0x00001508
-#define DDRSS1_CTL_61_DATA 0x00000063
+#define DDRSS1_CTL_61_DATA 0x00000068
#define DDRSS1_CTL_62_DATA 0x0000032B
#define DDRSS1_CTL_63_DATA 0x00001035
#define DDRSS1_CTL_64_DATA 0x0000032B
#define DDRSS1_CTL_65_DATA 0x00001035
#define DDRSS1_CTL_66_DATA 0x00000005
#define DDRSS1_CTL_67_DATA 0x00050000
-#define DDRSS1_CTL_68_DATA 0x00CB0012
-#define DDRSS1_CTL_69_DATA 0x00CB0408
-#define DDRSS1_CTL_70_DATA 0x00400408
+#define DDRSS1_CTL_68_DATA 0x00CB0005
+#define DDRSS1_CTL_69_DATA 0x00CB0200
+#define DDRSS1_CTL_70_DATA 0x00400200
#define DDRSS1_CTL_71_DATA 0x00120103
#define DDRSS1_CTL_72_DATA 0x00100005
#define DDRSS1_CTL_73_DATA 0x2F080010
@@ -2377,22 +2406,22 @@
#define DDRSS1_CTL_173_DATA 0x00000000
#define DDRSS1_CTL_174_DATA 0x00000000
#define DDRSS1_CTL_175_DATA 0x3FF40084
-#define DDRSS1_CTL_176_DATA 0x33003FF4
-#define DDRSS1_CTL_177_DATA 0x00003333
+#define DDRSS1_CTL_176_DATA 0xF3003FF4
+#define DDRSS1_CTL_177_DATA 0x0000F3F3
#define DDRSS1_CTL_178_DATA 0x35000000
#define DDRSS1_CTL_179_DATA 0x27270035
#define DDRSS1_CTL_180_DATA 0x0F0F0000
#define DDRSS1_CTL_181_DATA 0x16000000
#define DDRSS1_CTL_182_DATA 0x00841616
#define DDRSS1_CTL_183_DATA 0x3FF43FF4
-#define DDRSS1_CTL_184_DATA 0x33333300
+#define DDRSS1_CTL_184_DATA 0xF3F3F300
#define DDRSS1_CTL_185_DATA 0x00000000
#define DDRSS1_CTL_186_DATA 0x00353500
#define DDRSS1_CTL_187_DATA 0x00002727
#define DDRSS1_CTL_188_DATA 0x00000F0F
#define DDRSS1_CTL_189_DATA 0x16161600
#define DDRSS1_CTL_190_DATA 0x00000020
-#define DDRSS1_CTL_191_DATA 0x00000000
+#define DDRSS1_CTL_191_DATA 0x01000000
#define DDRSS1_CTL_192_DATA 0x00000001
#define DDRSS1_CTL_193_DATA 0x00000000
#define DDRSS1_CTL_194_DATA 0x01000000
@@ -2492,14 +2521,14 @@
#define DDRSS1_CTL_288_DATA 0x00000000
#define DDRSS1_CTL_289_DATA 0x00000000
#define DDRSS1_CTL_290_DATA 0x03030300
-#define DDRSS1_CTL_291_DATA 0x00000001
+#define DDRSS1_CTL_291_DATA 0x00010101
#define DDRSS1_CTL_292_DATA 0x00000000
#define DDRSS1_CTL_293_DATA 0x00000000
#define DDRSS1_CTL_294_DATA 0x00000000
#define DDRSS1_CTL_295_DATA 0x00000000
#define DDRSS1_CTL_296_DATA 0x00000000
-#define DDRSS1_CTL_297_DATA 0x00000000
-#define DDRSS1_CTL_298_DATA 0x00000000
+#define DDRSS1_CTL_297_DATA 0xFFFFFFFF
+#define DDRSS1_CTL_298_DATA 0x00000FFF
#define DDRSS1_CTL_299_DATA 0x00000000
#define DDRSS1_CTL_300_DATA 0x00000000
#define DDRSS1_CTL_301_DATA 0x00000000
@@ -2520,7 +2549,7 @@
#define DDRSS1_CTL_316_DATA 0x01010001
#define DDRSS1_CTL_317_DATA 0x00010101
#define DDRSS1_CTL_318_DATA 0x050A0A03
-#define DDRSS1_CTL_319_DATA 0x10081F1F
+#define DDRSS1_CTL_319_DATA 0x10082323
#define DDRSS1_CTL_320_DATA 0x00090310
#define DDRSS1_CTL_321_DATA 0x0B0C030F
#define DDRSS1_CTL_322_DATA 0x0B0C0306
@@ -2595,7 +2624,7 @@
#define DDRSS1_CTL_391_DATA 0x00000200
#define DDRSS1_CTL_392_DATA 0x00000200
#define DDRSS1_CTL_393_DATA 0x00000200
-#define DDRSS1_CTL_394_DATA 0x00000252
+#define DDRSS1_CTL_394_DATA 0x00000270
#define DDRSS1_CTL_395_DATA 0x000007BC
#define DDRSS1_CTL_396_DATA 0x00000204
#define DDRSS1_CTL_397_DATA 0x0000206A
@@ -2605,7 +2634,7 @@
#define DDRSS1_CTL_401_DATA 0x00000200
#define DDRSS1_CTL_402_DATA 0x0000613E
#define DDRSS1_CTL_403_DATA 0x00014424
-#define DDRSS1_CTL_404_DATA 0x00000E15
+#define DDRSS1_CTL_404_DATA 0x00000E19
#define DDRSS1_CTL_405_DATA 0x0000206A
#define DDRSS1_CTL_406_DATA 0x00000200
#define DDRSS1_CTL_407_DATA 0x00000200
@@ -2613,7 +2642,7 @@
#define DDRSS1_CTL_409_DATA 0x00000200
#define DDRSS1_CTL_410_DATA 0x0000613E
#define DDRSS1_CTL_411_DATA 0x00014424
-#define DDRSS1_CTL_412_DATA 0x02020E15
+#define DDRSS1_CTL_412_DATA 0x02020E19
#define DDRSS1_CTL_413_DATA 0x03030202
#define DDRSS1_CTL_414_DATA 0x00000022
#define DDRSS1_CTL_415_DATA 0x00000000
@@ -2630,7 +2659,7 @@
#define DDRSS1_CTL_426_DATA 0x00000000
#define DDRSS1_CTL_427_DATA 0x02000000
#define DDRSS1_CTL_428_DATA 0x01000404
-#define DDRSS1_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS1_CTL_429_DATA 0x0B220B22
#define DDRSS1_CTL_430_DATA 0x00000105
#define DDRSS1_CTL_431_DATA 0x00010101
#define DDRSS1_CTL_432_DATA 0x00010101
@@ -2673,8 +2702,8 @@
#define DDRSS1_PI_09_DATA 0x00000000
#define DDRSS1_PI_10_DATA 0x00000000
#define DDRSS1_PI_11_DATA 0x00000000
-#define DDRSS1_PI_12_DATA 0x00000007
-#define DDRSS1_PI_13_DATA 0x00010002
+#define DDRSS1_PI_12_DATA 0x00000003
+#define DDRSS1_PI_13_DATA 0x00010001
#define DDRSS1_PI_14_DATA 0x0800000F
#define DDRSS1_PI_15_DATA 0x00000103
#define DDRSS1_PI_16_DATA 0x00000005
@@ -2722,18 +2751,18 @@
#define DDRSS1_PI_58_DATA 0x00000000
#define DDRSS1_PI_59_DATA 0x00000000
#define DDRSS1_PI_60_DATA 0x0A0A140A
-#define DDRSS1_PI_61_DATA 0x10020101
+#define DDRSS1_PI_61_DATA 0x10020201
#define DDRSS1_PI_62_DATA 0x00020805
#define DDRSS1_PI_63_DATA 0x01000404
#define DDRSS1_PI_64_DATA 0x00000000
#define DDRSS1_PI_65_DATA 0x00000000
#define DDRSS1_PI_66_DATA 0x00000100
-#define DDRSS1_PI_67_DATA 0x0001010F
+#define DDRSS1_PI_67_DATA 0x0002020F
#define DDRSS1_PI_68_DATA 0x00340000
#define DDRSS1_PI_69_DATA 0x00000000
#define DDRSS1_PI_70_DATA 0x00000000
#define DDRSS1_PI_71_DATA 0x0000FFFF
-#define DDRSS1_PI_72_DATA 0x00000000
+#define DDRSS1_PI_72_DATA 0x01000000
#define DDRSS1_PI_73_DATA 0x00080000
#define DDRSS1_PI_74_DATA 0x02000200
#define DDRSS1_PI_75_DATA 0x01000100
@@ -2822,37 +2851,37 @@
#define DDRSS1_PI_158_DATA 0x00000000
#define DDRSS1_PI_159_DATA 0x00000401
#define DDRSS1_PI_160_DATA 0x00000000
-#define DDRSS1_PI_161_DATA 0x00010000
-#define DDRSS1_PI_162_DATA 0x00000000
-#define DDRSS1_PI_163_DATA 0x2B2B0200
+#define DDRSS1_PI_161_DATA 0x05010000
+#define DDRSS1_PI_162_DATA 0x00000001
+#define DDRSS1_PI_163_DATA 0x2B2B0201
#define DDRSS1_PI_164_DATA 0x00000034
-#define DDRSS1_PI_165_DATA 0x00000064
-#define DDRSS1_PI_166_DATA 0x00020064
+#define DDRSS1_PI_165_DATA 0x00000068
+#define DDRSS1_PI_166_DATA 0x00020068
#define DDRSS1_PI_167_DATA 0x02000200
-#define DDRSS1_PI_168_DATA 0x48120C04
-#define DDRSS1_PI_169_DATA 0x00154812
-#define DDRSS1_PI_170_DATA 0x00000063
+#define DDRSS1_PI_168_DATA 0x50120C04
+#define DDRSS1_PI_169_DATA 0x00155012
+#define DDRSS1_PI_170_DATA 0x00000068
#define DDRSS1_PI_171_DATA 0x0000032B
#define DDRSS1_PI_172_DATA 0x00001035
#define DDRSS1_PI_173_DATA 0x0000032B
#define DDRSS1_PI_174_DATA 0x04001035
#define DDRSS1_PI_175_DATA 0x01010404
-#define DDRSS1_PI_176_DATA 0x00001501
+#define DDRSS1_PI_176_DATA 0x00001500
#define DDRSS1_PI_177_DATA 0x00150015
#define DDRSS1_PI_178_DATA 0x01000100
#define DDRSS1_PI_179_DATA 0x00000100
#define DDRSS1_PI_180_DATA 0x00000000
#define DDRSS1_PI_181_DATA 0x01010101
-#define DDRSS1_PI_182_DATA 0x00000101
+#define DDRSS1_PI_182_DATA 0x00000000
#define DDRSS1_PI_183_DATA 0x00000000
#define DDRSS1_PI_184_DATA 0x00000000
-#define DDRSS1_PI_185_DATA 0x15040000
-#define DDRSS1_PI_186_DATA 0x0E0E0215
+#define DDRSS1_PI_185_DATA 0x19040000
+#define DDRSS1_PI_186_DATA 0x0E0E0219
#define DDRSS1_PI_187_DATA 0x00040402
#define DDRSS1_PI_188_DATA 0x000D0035
#define DDRSS1_PI_189_DATA 0x00218049
#define DDRSS1_PI_190_DATA 0x00218049
-#define DDRSS1_PI_191_DATA 0x01010101
+#define DDRSS1_PI_191_DATA 0x01000101
#define DDRSS1_PI_192_DATA 0x0004000E
#define DDRSS1_PI_193_DATA 0x00040216
#define DDRSS1_PI_194_DATA 0x01000216
@@ -2860,8 +2889,8 @@
#define DDRSS1_PI_196_DATA 0x02170100
#define DDRSS1_PI_197_DATA 0x01000217
#define DDRSS1_PI_198_DATA 0x02170217
-#define DDRSS1_PI_199_DATA 0x32103200
-#define DDRSS1_PI_200_DATA 0x01013210
+#define DDRSS1_PI_199_DATA 0x2F1B3200
+#define DDRSS1_PI_200_DATA 0x01012F1B
#define DDRSS1_PI_201_DATA 0x0A070601
#define DDRSS1_PI_202_DATA 0x1F130A0D
#define DDRSS1_PI_203_DATA 0x1F130A14
@@ -2873,13 +2902,13 @@
#define DDRSS1_PI_209_DATA 0x00240216
#define DDRSS1_PI_210_DATA 0x00110216
#define DDRSS1_PI_211_DATA 0x32000056
-#define DDRSS1_PI_212_DATA 0x00000301
-#define DDRSS1_PI_213_DATA 0x005B0036
+#define DDRSS1_PI_212_DATA 0x00000101
+#define DDRSS1_PI_213_DATA 0x005F0036
#define DDRSS1_PI_214_DATA 0x03013212
#define DDRSS1_PI_215_DATA 0x00003600
-#define DDRSS1_PI_216_DATA 0x3212005B
-#define DDRSS1_PI_217_DATA 0x09000301
-#define DDRSS1_PI_218_DATA 0x04010504
+#define DDRSS1_PI_216_DATA 0x3212005F
+#define DDRSS1_PI_217_DATA 0x09000001
+#define DDRSS1_PI_218_DATA 0x06010504
#define DDRSS1_PI_219_DATA 0x04000364
#define DDRSS1_PI_220_DATA 0x0A032001
#define DDRSS1_PI_221_DATA 0x2C31110A
@@ -2936,29 +2965,29 @@
#define DDRSS1_PI_272_DATA 0x00080804
#define DDRSS1_PI_273_DATA 0x00000000
#define DDRSS1_PI_274_DATA 0x00000000
-#define DDRSS1_PI_275_DATA 0x00330084
+#define DDRSS1_PI_275_DATA 0x00F30084
#define DDRSS1_PI_276_DATA 0x00160000
-#define DDRSS1_PI_277_DATA 0x35333FF4
+#define DDRSS1_PI_277_DATA 0x35F33FF4
#define DDRSS1_PI_278_DATA 0x00160F27
-#define DDRSS1_PI_279_DATA 0x35333FF4
+#define DDRSS1_PI_279_DATA 0x35F33FF4
#define DDRSS1_PI_280_DATA 0x00160F27
-#define DDRSS1_PI_281_DATA 0x00330084
+#define DDRSS1_PI_281_DATA 0x00F30084
#define DDRSS1_PI_282_DATA 0x00160000
-#define DDRSS1_PI_283_DATA 0x35333FF4
+#define DDRSS1_PI_283_DATA 0x35F33FF4
#define DDRSS1_PI_284_DATA 0x00160F27
-#define DDRSS1_PI_285_DATA 0x35333FF4
+#define DDRSS1_PI_285_DATA 0x35F33FF4
#define DDRSS1_PI_286_DATA 0x00160F27
-#define DDRSS1_PI_287_DATA 0x00330084
+#define DDRSS1_PI_287_DATA 0x00F30084
#define DDRSS1_PI_288_DATA 0x00160000
-#define DDRSS1_PI_289_DATA 0x35333FF4
+#define DDRSS1_PI_289_DATA 0x35F33FF4
#define DDRSS1_PI_290_DATA 0x00160F27
-#define DDRSS1_PI_291_DATA 0x35333FF4
+#define DDRSS1_PI_291_DATA 0x35F33FF4
#define DDRSS1_PI_292_DATA 0x00160F27
-#define DDRSS1_PI_293_DATA 0x00330084
+#define DDRSS1_PI_293_DATA 0x00F30084
#define DDRSS1_PI_294_DATA 0x00160000
-#define DDRSS1_PI_295_DATA 0x35333FF4
+#define DDRSS1_PI_295_DATA 0x35F33FF4
#define DDRSS1_PI_296_DATA 0x00160F27
-#define DDRSS1_PI_297_DATA 0x35333FF4
+#define DDRSS1_PI_297_DATA 0x35F33FF4
#define DDRSS1_PI_298_DATA 0x00160F27
#define DDRSS1_PI_299_DATA 0x00000000
@@ -2974,7 +3003,7 @@
#define DDRSS1_PHY_09_DATA 0x00000000
#define DDRSS1_PHY_10_DATA 0x00000000
#define DDRSS1_PHY_11_DATA 0x01000001
-#define DDRSS1_PHY_12_DATA 0x00000100
+#define DDRSS1_PHY_12_DATA 0x00000200
#define DDRSS1_PHY_13_DATA 0x000800C0
#define DDRSS1_PHY_14_DATA 0x060100CC
#define DDRSS1_PHY_15_DATA 0x00030066
@@ -2993,7 +3022,7 @@
#define DDRSS1_PHY_28_DATA 0x2A000000
#define DDRSS1_PHY_29_DATA 0x00000808
#define DDRSS1_PHY_30_DATA 0x0F000000
-#define DDRSS1_PHY_31_DATA 0x00000F0F
+#define DDRSS1_PHY_31_DATA 0x00000F08
#define DDRSS1_PHY_32_DATA 0x10400000
#define DDRSS1_PHY_33_DATA 0x0C002006
#define DDRSS1_PHY_34_DATA 0x00000000
@@ -3062,9 +3091,9 @@
#define DDRSS1_PHY_97_DATA 0x00050010
#define DDRSS1_PHY_98_DATA 0x51517041
#define DDRSS1_PHY_99_DATA 0x31C06001
-#define DDRSS1_PHY_100_DATA 0x07AB0340
+#define DDRSS1_PHY_100_DATA 0x07AB01AB
#define DDRSS1_PHY_101_DATA 0x00C0C001
-#define DDRSS1_PHY_102_DATA 0x0E0D0001
+#define DDRSS1_PHY_102_DATA 0x0E0D0101
#define DDRSS1_PHY_103_DATA 0x10001000
#define DDRSS1_PHY_104_DATA 0x0C083E42
#define DDRSS1_PHY_105_DATA 0x0F0C3701
@@ -3230,7 +3259,7 @@
#define DDRSS1_PHY_265_DATA 0x00000000
#define DDRSS1_PHY_266_DATA 0x00000000
#define DDRSS1_PHY_267_DATA 0x01000001
-#define DDRSS1_PHY_268_DATA 0x00000100
+#define DDRSS1_PHY_268_DATA 0x00000200
#define DDRSS1_PHY_269_DATA 0x000800C0
#define DDRSS1_PHY_270_DATA 0x060100CC
#define DDRSS1_PHY_271_DATA 0x00030066
@@ -3249,7 +3278,7 @@
#define DDRSS1_PHY_284_DATA 0x2A000000
#define DDRSS1_PHY_285_DATA 0x00000808
#define DDRSS1_PHY_286_DATA 0x0F000000
-#define DDRSS1_PHY_287_DATA 0x00000F0F
+#define DDRSS1_PHY_287_DATA 0x00000F08
#define DDRSS1_PHY_288_DATA 0x10400000
#define DDRSS1_PHY_289_DATA 0x0C002006
#define DDRSS1_PHY_290_DATA 0x00000000
@@ -3318,9 +3347,9 @@
#define DDRSS1_PHY_353_DATA 0x00050010
#define DDRSS1_PHY_354_DATA 0x51517041
#define DDRSS1_PHY_355_DATA 0x31C06001
-#define DDRSS1_PHY_356_DATA 0x07AB0340
+#define DDRSS1_PHY_356_DATA 0x07AB01AB
#define DDRSS1_PHY_357_DATA 0x00C0C001
-#define DDRSS1_PHY_358_DATA 0x0E0D0001
+#define DDRSS1_PHY_358_DATA 0x0E0D0101
#define DDRSS1_PHY_359_DATA 0x10001000
#define DDRSS1_PHY_360_DATA 0x0C083E42
#define DDRSS1_PHY_361_DATA 0x0F0C3701
@@ -3486,7 +3515,7 @@
#define DDRSS1_PHY_521_DATA 0x00000000
#define DDRSS1_PHY_522_DATA 0x00000000
#define DDRSS1_PHY_523_DATA 0x01000001
-#define DDRSS1_PHY_524_DATA 0x00000100
+#define DDRSS1_PHY_524_DATA 0x00000200
#define DDRSS1_PHY_525_DATA 0x000800C0
#define DDRSS1_PHY_526_DATA 0x060100CC
#define DDRSS1_PHY_527_DATA 0x00030066
@@ -3505,7 +3534,7 @@
#define DDRSS1_PHY_540_DATA 0x2A000000
#define DDRSS1_PHY_541_DATA 0x00000808
#define DDRSS1_PHY_542_DATA 0x0F000000
-#define DDRSS1_PHY_543_DATA 0x00000F0F
+#define DDRSS1_PHY_543_DATA 0x00000F08
#define DDRSS1_PHY_544_DATA 0x10400000
#define DDRSS1_PHY_545_DATA 0x0C002006
#define DDRSS1_PHY_546_DATA 0x00000000
@@ -3574,9 +3603,9 @@
#define DDRSS1_PHY_609_DATA 0x00050010
#define DDRSS1_PHY_610_DATA 0x51517041
#define DDRSS1_PHY_611_DATA 0x31C06001
-#define DDRSS1_PHY_612_DATA 0x07AB0340
+#define DDRSS1_PHY_612_DATA 0x07AB01AB
#define DDRSS1_PHY_613_DATA 0x00C0C001
-#define DDRSS1_PHY_614_DATA 0x0E0D0001
+#define DDRSS1_PHY_614_DATA 0x0E0D0101
#define DDRSS1_PHY_615_DATA 0x10001000
#define DDRSS1_PHY_616_DATA 0x0C083E42
#define DDRSS1_PHY_617_DATA 0x0F0C3701
@@ -3742,7 +3771,7 @@
#define DDRSS1_PHY_777_DATA 0x00000000
#define DDRSS1_PHY_778_DATA 0x00000000
#define DDRSS1_PHY_779_DATA 0x01000001
-#define DDRSS1_PHY_780_DATA 0x00000100
+#define DDRSS1_PHY_780_DATA 0x00000200
#define DDRSS1_PHY_781_DATA 0x000800C0
#define DDRSS1_PHY_782_DATA 0x060100CC
#define DDRSS1_PHY_783_DATA 0x00030066
@@ -3761,7 +3790,7 @@
#define DDRSS1_PHY_796_DATA 0x2A000000
#define DDRSS1_PHY_797_DATA 0x00000808
#define DDRSS1_PHY_798_DATA 0x0F000000
-#define DDRSS1_PHY_799_DATA 0x00000F0F
+#define DDRSS1_PHY_799_DATA 0x00000F08
#define DDRSS1_PHY_800_DATA 0x10400000
#define DDRSS1_PHY_801_DATA 0x0C002006
#define DDRSS1_PHY_802_DATA 0x00000000
@@ -3830,9 +3859,9 @@
#define DDRSS1_PHY_865_DATA 0x00050010
#define DDRSS1_PHY_866_DATA 0x51517041
#define DDRSS1_PHY_867_DATA 0x31C06001
-#define DDRSS1_PHY_868_DATA 0x07AB0340
+#define DDRSS1_PHY_868_DATA 0x07AB01AB
#define DDRSS1_PHY_869_DATA 0x00C0C001
-#define DDRSS1_PHY_870_DATA 0x0E0D0001
+#define DDRSS1_PHY_870_DATA 0x0E0D0101
#define DDRSS1_PHY_871_DATA 0x10001000
#define DDRSS1_PHY_872_DATA 0x0C083E42
#define DDRSS1_PHY_873_DATA 0x0F0C3701
@@ -4017,7 +4046,7 @@
#define DDRSS1_PHY_1052_DATA 0x00000033
#define DDRSS1_PHY_1053_DATA 0x00543210
#define DDRSS1_PHY_1054_DATA 0x003F0000
-#define DDRSS1_PHY_1055_DATA 0x000F013F
+#define DDRSS1_PHY_1055_DATA 0x000F3F3F
#define DDRSS1_PHY_1056_DATA 0x20202003
#define DDRSS1_PHY_1057_DATA 0x00202020
#define DDRSS1_PHY_1058_DATA 0x20008008
@@ -4265,7 +4294,7 @@
#define DDRSS1_PHY_1300_DATA 0x00040101
#define DDRSS1_PHY_1301_DATA 0x0000010F
#define DDRSS1_PHY_1302_DATA 0x00000000
-#define DDRSS1_PHY_1303_DATA 0x0000FFFF
+#define DDRSS1_PHY_1303_DATA 0x00000064
#define DDRSS1_PHY_1304_DATA 0x00000000
#define DDRSS1_PHY_1305_DATA 0x01010000
#define DDRSS1_PHY_1306_DATA 0x01080402
@@ -4359,7 +4388,7 @@
#define DDRSS1_PHY_1394_DATA 0x00000003
#define DDRSS1_PHY_1395_DATA 0x00000000
#define DDRSS1_PHY_1396_DATA 0x00001142
-#define DDRSS1_PHY_1397_DATA 0x010207AB
+#define DDRSS1_PHY_1397_DATA 0x040207AB
#define DDRSS1_PHY_1398_DATA 0x01000080
#define DDRSS1_PHY_1399_DATA 0x03900390
#define DDRSS1_PHY_1400_DATA 0x03900390
@@ -4406,7 +4435,7 @@
#define DDRSS2_CTL_17_DATA 0x00000005
#define DDRSS2_CTL_18_DATA 0x000010A9
#define DDRSS2_CTL_19_DATA 0x01010000
-#define DDRSS2_CTL_20_DATA 0x02011001
+#define DDRSS2_CTL_20_DATA 0x01011001
#define DDRSS2_CTL_21_DATA 0x02010000
#define DDRSS2_CTL_22_DATA 0x00020100
#define DDRSS2_CTL_23_DATA 0x0000000B
@@ -4421,7 +4450,7 @@
#define DDRSS2_CTL_32_DATA 0x00000000
#define DDRSS2_CTL_33_DATA 0x00000000
#define DDRSS2_CTL_34_DATA 0x040C0000
-#define DDRSS2_CTL_35_DATA 0x12481248
+#define DDRSS2_CTL_35_DATA 0x12501250
#define DDRSS2_CTL_36_DATA 0x00050804
#define DDRSS2_CTL_37_DATA 0x09040008
#define DDRSS2_CTL_38_DATA 0x15000204
@@ -4436,27 +4465,27 @@
#define DDRSS2_CTL_47_DATA 0x1E161110
#define DDRSS2_CTL_48_DATA 0x1000922C
#define DDRSS2_CTL_49_DATA 0x02030410
-#define DDRSS2_CTL_50_DATA 0x2C040500
+#define DDRSS2_CTL_50_DATA 0x2C060500
#define DDRSS2_CTL_51_DATA 0x08292C29
#define DDRSS2_CTL_52_DATA 0x14000E0A
#define DDRSS2_CTL_53_DATA 0x04010A0A
#define DDRSS2_CTL_54_DATA 0x01010004
-#define DDRSS2_CTL_55_DATA 0x04545408
+#define DDRSS2_CTL_55_DATA 0x0454540A
#define DDRSS2_CTL_56_DATA 0x04313104
#define DDRSS2_CTL_57_DATA 0x00003131
#define DDRSS2_CTL_58_DATA 0x00010100
#define DDRSS2_CTL_59_DATA 0x03010000
#define DDRSS2_CTL_60_DATA 0x00001508
-#define DDRSS2_CTL_61_DATA 0x00000063
+#define DDRSS2_CTL_61_DATA 0x00000068
#define DDRSS2_CTL_62_DATA 0x0000032B
#define DDRSS2_CTL_63_DATA 0x00001035
#define DDRSS2_CTL_64_DATA 0x0000032B
#define DDRSS2_CTL_65_DATA 0x00001035
#define DDRSS2_CTL_66_DATA 0x00000005
#define DDRSS2_CTL_67_DATA 0x00050000
-#define DDRSS2_CTL_68_DATA 0x00CB0012
-#define DDRSS2_CTL_69_DATA 0x00CB0408
-#define DDRSS2_CTL_70_DATA 0x00400408
+#define DDRSS2_CTL_68_DATA 0x00CB0005
+#define DDRSS2_CTL_69_DATA 0x00CB0200
+#define DDRSS2_CTL_70_DATA 0x00400200
#define DDRSS2_CTL_71_DATA 0x00120103
#define DDRSS2_CTL_72_DATA 0x00100005
#define DDRSS2_CTL_73_DATA 0x2F080010
@@ -4562,22 +4591,22 @@
#define DDRSS2_CTL_173_DATA 0x00000000
#define DDRSS2_CTL_174_DATA 0x00000000
#define DDRSS2_CTL_175_DATA 0x3FF40084
-#define DDRSS2_CTL_176_DATA 0x33003FF4
-#define DDRSS2_CTL_177_DATA 0x00003333
+#define DDRSS2_CTL_176_DATA 0xF3003FF4
+#define DDRSS2_CTL_177_DATA 0x0000F3F3
#define DDRSS2_CTL_178_DATA 0x35000000
#define DDRSS2_CTL_179_DATA 0x27270035
#define DDRSS2_CTL_180_DATA 0x0F0F0000
#define DDRSS2_CTL_181_DATA 0x16000000
#define DDRSS2_CTL_182_DATA 0x00841616
#define DDRSS2_CTL_183_DATA 0x3FF43FF4
-#define DDRSS2_CTL_184_DATA 0x33333300
+#define DDRSS2_CTL_184_DATA 0xF3F3F300
#define DDRSS2_CTL_185_DATA 0x00000000
#define DDRSS2_CTL_186_DATA 0x00353500
#define DDRSS2_CTL_187_DATA 0x00002727
#define DDRSS2_CTL_188_DATA 0x00000F0F
#define DDRSS2_CTL_189_DATA 0x16161600
#define DDRSS2_CTL_190_DATA 0x00000020
-#define DDRSS2_CTL_191_DATA 0x00000000
+#define DDRSS2_CTL_191_DATA 0x01000000
#define DDRSS2_CTL_192_DATA 0x00000001
#define DDRSS2_CTL_193_DATA 0x00000000
#define DDRSS2_CTL_194_DATA 0x01000000
@@ -4677,14 +4706,14 @@
#define DDRSS2_CTL_288_DATA 0x00000000
#define DDRSS2_CTL_289_DATA 0x00000000
#define DDRSS2_CTL_290_DATA 0x03030300
-#define DDRSS2_CTL_291_DATA 0x00000001
+#define DDRSS2_CTL_291_DATA 0x00010101
#define DDRSS2_CTL_292_DATA 0x00000000
#define DDRSS2_CTL_293_DATA 0x00000000
#define DDRSS2_CTL_294_DATA 0x00000000
#define DDRSS2_CTL_295_DATA 0x00000000
#define DDRSS2_CTL_296_DATA 0x00000000
-#define DDRSS2_CTL_297_DATA 0x00000000
-#define DDRSS2_CTL_298_DATA 0x00000000
+#define DDRSS2_CTL_297_DATA 0xFFFFFFFF
+#define DDRSS2_CTL_298_DATA 0x00000FFF
#define DDRSS2_CTL_299_DATA 0x00000000
#define DDRSS2_CTL_300_DATA 0x00000000
#define DDRSS2_CTL_301_DATA 0x00000000
@@ -4705,7 +4734,7 @@
#define DDRSS2_CTL_316_DATA 0x01010001
#define DDRSS2_CTL_317_DATA 0x00010101
#define DDRSS2_CTL_318_DATA 0x050A0A03
-#define DDRSS2_CTL_319_DATA 0x10081F1F
+#define DDRSS2_CTL_319_DATA 0x10082323
#define DDRSS2_CTL_320_DATA 0x00090310
#define DDRSS2_CTL_321_DATA 0x0B0C030F
#define DDRSS2_CTL_322_DATA 0x0B0C0306
@@ -4780,7 +4809,7 @@
#define DDRSS2_CTL_391_DATA 0x00000200
#define DDRSS2_CTL_392_DATA 0x00000200
#define DDRSS2_CTL_393_DATA 0x00000200
-#define DDRSS2_CTL_394_DATA 0x00000252
+#define DDRSS2_CTL_394_DATA 0x00000270
#define DDRSS2_CTL_395_DATA 0x000007BC
#define DDRSS2_CTL_396_DATA 0x00000204
#define DDRSS2_CTL_397_DATA 0x0000206A
@@ -4790,7 +4819,7 @@
#define DDRSS2_CTL_401_DATA 0x00000200
#define DDRSS2_CTL_402_DATA 0x0000613E
#define DDRSS2_CTL_403_DATA 0x00014424
-#define DDRSS2_CTL_404_DATA 0x00000E15
+#define DDRSS2_CTL_404_DATA 0x00000E19
#define DDRSS2_CTL_405_DATA 0x0000206A
#define DDRSS2_CTL_406_DATA 0x00000200
#define DDRSS2_CTL_407_DATA 0x00000200
@@ -4798,7 +4827,7 @@
#define DDRSS2_CTL_409_DATA 0x00000200
#define DDRSS2_CTL_410_DATA 0x0000613E
#define DDRSS2_CTL_411_DATA 0x00014424
-#define DDRSS2_CTL_412_DATA 0x02020E15
+#define DDRSS2_CTL_412_DATA 0x02020E19
#define DDRSS2_CTL_413_DATA 0x03030202
#define DDRSS2_CTL_414_DATA 0x00000022
#define DDRSS2_CTL_415_DATA 0x00000000
@@ -4815,7 +4844,7 @@
#define DDRSS2_CTL_426_DATA 0x00000000
#define DDRSS2_CTL_427_DATA 0x02000000
#define DDRSS2_CTL_428_DATA 0x01000404
-#define DDRSS2_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS2_CTL_429_DATA 0x0B220B22
#define DDRSS2_CTL_430_DATA 0x00000105
#define DDRSS2_CTL_431_DATA 0x00010101
#define DDRSS2_CTL_432_DATA 0x00010101
@@ -4858,8 +4887,8 @@
#define DDRSS2_PI_09_DATA 0x00000000
#define DDRSS2_PI_10_DATA 0x00000000
#define DDRSS2_PI_11_DATA 0x00000000
-#define DDRSS2_PI_12_DATA 0x00000007
-#define DDRSS2_PI_13_DATA 0x00010002
+#define DDRSS2_PI_12_DATA 0x00000003
+#define DDRSS2_PI_13_DATA 0x00010001
#define DDRSS2_PI_14_DATA 0x0800000F
#define DDRSS2_PI_15_DATA 0x00000103
#define DDRSS2_PI_16_DATA 0x00000005
@@ -4907,18 +4936,18 @@
#define DDRSS2_PI_58_DATA 0x00000000
#define DDRSS2_PI_59_DATA 0x00000000
#define DDRSS2_PI_60_DATA 0x0A0A140A
-#define DDRSS2_PI_61_DATA 0x10020101
+#define DDRSS2_PI_61_DATA 0x10020201
#define DDRSS2_PI_62_DATA 0x00020805
#define DDRSS2_PI_63_DATA 0x01000404
#define DDRSS2_PI_64_DATA 0x00000000
#define DDRSS2_PI_65_DATA 0x00000000
#define DDRSS2_PI_66_DATA 0x00000100
-#define DDRSS2_PI_67_DATA 0x0001010F
+#define DDRSS2_PI_67_DATA 0x0002020F
#define DDRSS2_PI_68_DATA 0x00340000
#define DDRSS2_PI_69_DATA 0x00000000
#define DDRSS2_PI_70_DATA 0x00000000
#define DDRSS2_PI_71_DATA 0x0000FFFF
-#define DDRSS2_PI_72_DATA 0x00000000
+#define DDRSS2_PI_72_DATA 0x01000000
#define DDRSS2_PI_73_DATA 0x00080000
#define DDRSS2_PI_74_DATA 0x02000200
#define DDRSS2_PI_75_DATA 0x01000100
@@ -5007,37 +5036,37 @@
#define DDRSS2_PI_158_DATA 0x00000000
#define DDRSS2_PI_159_DATA 0x00000401
#define DDRSS2_PI_160_DATA 0x00000000
-#define DDRSS2_PI_161_DATA 0x00010000
-#define DDRSS2_PI_162_DATA 0x00000000
-#define DDRSS2_PI_163_DATA 0x2B2B0200
+#define DDRSS2_PI_161_DATA 0x05010000
+#define DDRSS2_PI_162_DATA 0x00000001
+#define DDRSS2_PI_163_DATA 0x2B2B0201
#define DDRSS2_PI_164_DATA 0x00000034
-#define DDRSS2_PI_165_DATA 0x00000064
-#define DDRSS2_PI_166_DATA 0x00020064
+#define DDRSS2_PI_165_DATA 0x00000068
+#define DDRSS2_PI_166_DATA 0x00020068
#define DDRSS2_PI_167_DATA 0x02000200
-#define DDRSS2_PI_168_DATA 0x48120C04
-#define DDRSS2_PI_169_DATA 0x00154812
-#define DDRSS2_PI_170_DATA 0x00000063
+#define DDRSS2_PI_168_DATA 0x50120C04
+#define DDRSS2_PI_169_DATA 0x00155012
+#define DDRSS2_PI_170_DATA 0x00000068
#define DDRSS2_PI_171_DATA 0x0000032B
#define DDRSS2_PI_172_DATA 0x00001035
#define DDRSS2_PI_173_DATA 0x0000032B
#define DDRSS2_PI_174_DATA 0x04001035
#define DDRSS2_PI_175_DATA 0x01010404
-#define DDRSS2_PI_176_DATA 0x00001501
+#define DDRSS2_PI_176_DATA 0x00001500
#define DDRSS2_PI_177_DATA 0x00150015
#define DDRSS2_PI_178_DATA 0x01000100
#define DDRSS2_PI_179_DATA 0x00000100
#define DDRSS2_PI_180_DATA 0x00000000
#define DDRSS2_PI_181_DATA 0x01010101
-#define DDRSS2_PI_182_DATA 0x00000101
+#define DDRSS2_PI_182_DATA 0x00000000
#define DDRSS2_PI_183_DATA 0x00000000
#define DDRSS2_PI_184_DATA 0x00000000
-#define DDRSS2_PI_185_DATA 0x15040000
-#define DDRSS2_PI_186_DATA 0x0E0E0215
+#define DDRSS2_PI_185_DATA 0x19040000
+#define DDRSS2_PI_186_DATA 0x0E0E0219
#define DDRSS2_PI_187_DATA 0x00040402
#define DDRSS2_PI_188_DATA 0x000D0035
#define DDRSS2_PI_189_DATA 0x00218049
#define DDRSS2_PI_190_DATA 0x00218049
-#define DDRSS2_PI_191_DATA 0x01010101
+#define DDRSS2_PI_191_DATA 0x01000101
#define DDRSS2_PI_192_DATA 0x0004000E
#define DDRSS2_PI_193_DATA 0x00040216
#define DDRSS2_PI_194_DATA 0x01000216
@@ -5045,8 +5074,8 @@
#define DDRSS2_PI_196_DATA 0x02170100
#define DDRSS2_PI_197_DATA 0x01000217
#define DDRSS2_PI_198_DATA 0x02170217
-#define DDRSS2_PI_199_DATA 0x32103200
-#define DDRSS2_PI_200_DATA 0x01013210
+#define DDRSS2_PI_199_DATA 0x2F1B3200
+#define DDRSS2_PI_200_DATA 0x01012F1B
#define DDRSS2_PI_201_DATA 0x0A070601
#define DDRSS2_PI_202_DATA 0x1F130A0D
#define DDRSS2_PI_203_DATA 0x1F130A14
@@ -5058,13 +5087,13 @@
#define DDRSS2_PI_209_DATA 0x00240216
#define DDRSS2_PI_210_DATA 0x00110216
#define DDRSS2_PI_211_DATA 0x32000056
-#define DDRSS2_PI_212_DATA 0x00000301
-#define DDRSS2_PI_213_DATA 0x005B0036
+#define DDRSS2_PI_212_DATA 0x00000101
+#define DDRSS2_PI_213_DATA 0x005F0036
#define DDRSS2_PI_214_DATA 0x03013212
#define DDRSS2_PI_215_DATA 0x00003600
-#define DDRSS2_PI_216_DATA 0x3212005B
-#define DDRSS2_PI_217_DATA 0x09000301
-#define DDRSS2_PI_218_DATA 0x04010504
+#define DDRSS2_PI_216_DATA 0x3212005F
+#define DDRSS2_PI_217_DATA 0x09000001
+#define DDRSS2_PI_218_DATA 0x06010504
#define DDRSS2_PI_219_DATA 0x04000364
#define DDRSS2_PI_220_DATA 0x0A032001
#define DDRSS2_PI_221_DATA 0x2C31110A
@@ -5121,29 +5150,29 @@
#define DDRSS2_PI_272_DATA 0x00080804
#define DDRSS2_PI_273_DATA 0x00000000
#define DDRSS2_PI_274_DATA 0x00000000
-#define DDRSS2_PI_275_DATA 0x00330084
+#define DDRSS2_PI_275_DATA 0x00F30084
#define DDRSS2_PI_276_DATA 0x00160000
-#define DDRSS2_PI_277_DATA 0x35333FF4
+#define DDRSS2_PI_277_DATA 0x35F33FF4
#define DDRSS2_PI_278_DATA 0x00160F27
-#define DDRSS2_PI_279_DATA 0x35333FF4
+#define DDRSS2_PI_279_DATA 0x35F33FF4
#define DDRSS2_PI_280_DATA 0x00160F27
-#define DDRSS2_PI_281_DATA 0x00330084
+#define DDRSS2_PI_281_DATA 0x00F30084
#define DDRSS2_PI_282_DATA 0x00160000
-#define DDRSS2_PI_283_DATA 0x35333FF4
+#define DDRSS2_PI_283_DATA 0x35F33FF4
#define DDRSS2_PI_284_DATA 0x00160F27
-#define DDRSS2_PI_285_DATA 0x35333FF4
+#define DDRSS2_PI_285_DATA 0x35F33FF4
#define DDRSS2_PI_286_DATA 0x00160F27
-#define DDRSS2_PI_287_DATA 0x00330084
+#define DDRSS2_PI_287_DATA 0x00F30084
#define DDRSS2_PI_288_DATA 0x00160000
-#define DDRSS2_PI_289_DATA 0x35333FF4
+#define DDRSS2_PI_289_DATA 0x35F33FF4
#define DDRSS2_PI_290_DATA 0x00160F27
-#define DDRSS2_PI_291_DATA 0x35333FF4
+#define DDRSS2_PI_291_DATA 0x35F33FF4
#define DDRSS2_PI_292_DATA 0x00160F27
-#define DDRSS2_PI_293_DATA 0x00330084
+#define DDRSS2_PI_293_DATA 0x00F30084
#define DDRSS2_PI_294_DATA 0x00160000
-#define DDRSS2_PI_295_DATA 0x35333FF4
+#define DDRSS2_PI_295_DATA 0x35F33FF4
#define DDRSS2_PI_296_DATA 0x00160F27
-#define DDRSS2_PI_297_DATA 0x35333FF4
+#define DDRSS2_PI_297_DATA 0x35F33FF4
#define DDRSS2_PI_298_DATA 0x00160F27
#define DDRSS2_PI_299_DATA 0x00000000
@@ -5159,7 +5188,7 @@
#define DDRSS2_PHY_09_DATA 0x00000000
#define DDRSS2_PHY_10_DATA 0x00000000
#define DDRSS2_PHY_11_DATA 0x01000001
-#define DDRSS2_PHY_12_DATA 0x00000100
+#define DDRSS2_PHY_12_DATA 0x00000200
#define DDRSS2_PHY_13_DATA 0x000800C0
#define DDRSS2_PHY_14_DATA 0x060100CC
#define DDRSS2_PHY_15_DATA 0x00030066
@@ -5178,7 +5207,7 @@
#define DDRSS2_PHY_28_DATA 0x2A000000
#define DDRSS2_PHY_29_DATA 0x00000808
#define DDRSS2_PHY_30_DATA 0x0F000000
-#define DDRSS2_PHY_31_DATA 0x00000F0F
+#define DDRSS2_PHY_31_DATA 0x00000F08
#define DDRSS2_PHY_32_DATA 0x10400000
#define DDRSS2_PHY_33_DATA 0x0C002006
#define DDRSS2_PHY_34_DATA 0x00000000
@@ -5247,9 +5276,9 @@
#define DDRSS2_PHY_97_DATA 0x00050010
#define DDRSS2_PHY_98_DATA 0x51517041
#define DDRSS2_PHY_99_DATA 0x31C06001
-#define DDRSS2_PHY_100_DATA 0x07AB0340
+#define DDRSS2_PHY_100_DATA 0x07AB01AB
#define DDRSS2_PHY_101_DATA 0x00C0C001
-#define DDRSS2_PHY_102_DATA 0x0E0D0001
+#define DDRSS2_PHY_102_DATA 0x0E0D0101
#define DDRSS2_PHY_103_DATA 0x10001000
#define DDRSS2_PHY_104_DATA 0x0C083E42
#define DDRSS2_PHY_105_DATA 0x0F0C3701
@@ -5415,7 +5444,7 @@
#define DDRSS2_PHY_265_DATA 0x00000000
#define DDRSS2_PHY_266_DATA 0x00000000
#define DDRSS2_PHY_267_DATA 0x01000001
-#define DDRSS2_PHY_268_DATA 0x00000100
+#define DDRSS2_PHY_268_DATA 0x00000200
#define DDRSS2_PHY_269_DATA 0x000800C0
#define DDRSS2_PHY_270_DATA 0x060100CC
#define DDRSS2_PHY_271_DATA 0x00030066
@@ -5434,7 +5463,7 @@
#define DDRSS2_PHY_284_DATA 0x2A000000
#define DDRSS2_PHY_285_DATA 0x00000808
#define DDRSS2_PHY_286_DATA 0x0F000000
-#define DDRSS2_PHY_287_DATA 0x00000F0F
+#define DDRSS2_PHY_287_DATA 0x00000F08
#define DDRSS2_PHY_288_DATA 0x10400000
#define DDRSS2_PHY_289_DATA 0x0C002006
#define DDRSS2_PHY_290_DATA 0x00000000
@@ -5503,9 +5532,9 @@
#define DDRSS2_PHY_353_DATA 0x00050010
#define DDRSS2_PHY_354_DATA 0x51517041
#define DDRSS2_PHY_355_DATA 0x31C06001
-#define DDRSS2_PHY_356_DATA 0x07AB0340
+#define DDRSS2_PHY_356_DATA 0x07AB01AB
#define DDRSS2_PHY_357_DATA 0x00C0C001
-#define DDRSS2_PHY_358_DATA 0x0E0D0001
+#define DDRSS2_PHY_358_DATA 0x0E0D0101
#define DDRSS2_PHY_359_DATA 0x10001000
#define DDRSS2_PHY_360_DATA 0x0C083E42
#define DDRSS2_PHY_361_DATA 0x0F0C3701
@@ -5671,7 +5700,7 @@
#define DDRSS2_PHY_521_DATA 0x00000000
#define DDRSS2_PHY_522_DATA 0x00000000
#define DDRSS2_PHY_523_DATA 0x01000001
-#define DDRSS2_PHY_524_DATA 0x00000100
+#define DDRSS2_PHY_524_DATA 0x00000200
#define DDRSS2_PHY_525_DATA 0x000800C0
#define DDRSS2_PHY_526_DATA 0x060100CC
#define DDRSS2_PHY_527_DATA 0x00030066
@@ -5690,7 +5719,7 @@
#define DDRSS2_PHY_540_DATA 0x2A000000
#define DDRSS2_PHY_541_DATA 0x00000808
#define DDRSS2_PHY_542_DATA 0x0F000000
-#define DDRSS2_PHY_543_DATA 0x00000F0F
+#define DDRSS2_PHY_543_DATA 0x00000F08
#define DDRSS2_PHY_544_DATA 0x10400000
#define DDRSS2_PHY_545_DATA 0x0C002006
#define DDRSS2_PHY_546_DATA 0x00000000
@@ -5759,9 +5788,9 @@
#define DDRSS2_PHY_609_DATA 0x00050010
#define DDRSS2_PHY_610_DATA 0x51517041
#define DDRSS2_PHY_611_DATA 0x31C06001
-#define DDRSS2_PHY_612_DATA 0x07AB0340
+#define DDRSS2_PHY_612_DATA 0x07AB01AB
#define DDRSS2_PHY_613_DATA 0x00C0C001
-#define DDRSS2_PHY_614_DATA 0x0E0D0001
+#define DDRSS2_PHY_614_DATA 0x0E0D0101
#define DDRSS2_PHY_615_DATA 0x10001000
#define DDRSS2_PHY_616_DATA 0x0C083E42
#define DDRSS2_PHY_617_DATA 0x0F0C3701
@@ -5927,7 +5956,7 @@
#define DDRSS2_PHY_777_DATA 0x00000000
#define DDRSS2_PHY_778_DATA 0x00000000
#define DDRSS2_PHY_779_DATA 0x01000001
-#define DDRSS2_PHY_780_DATA 0x00000100
+#define DDRSS2_PHY_780_DATA 0x00000200
#define DDRSS2_PHY_781_DATA 0x000800C0
#define DDRSS2_PHY_782_DATA 0x060100CC
#define DDRSS2_PHY_783_DATA 0x00030066
@@ -5946,7 +5975,7 @@
#define DDRSS2_PHY_796_DATA 0x2A000000
#define DDRSS2_PHY_797_DATA 0x00000808
#define DDRSS2_PHY_798_DATA 0x0F000000
-#define DDRSS2_PHY_799_DATA 0x00000F0F
+#define DDRSS2_PHY_799_DATA 0x00000F08
#define DDRSS2_PHY_800_DATA 0x10400000
#define DDRSS2_PHY_801_DATA 0x0C002006
#define DDRSS2_PHY_802_DATA 0x00000000
@@ -6015,9 +6044,9 @@
#define DDRSS2_PHY_865_DATA 0x00050010
#define DDRSS2_PHY_866_DATA 0x51517041
#define DDRSS2_PHY_867_DATA 0x31C06001
-#define DDRSS2_PHY_868_DATA 0x07AB0340
+#define DDRSS2_PHY_868_DATA 0x07AB01AB
#define DDRSS2_PHY_869_DATA 0x00C0C001
-#define DDRSS2_PHY_870_DATA 0x0E0D0001
+#define DDRSS2_PHY_870_DATA 0x0E0D0101
#define DDRSS2_PHY_871_DATA 0x10001000
#define DDRSS2_PHY_872_DATA 0x0C083E42
#define DDRSS2_PHY_873_DATA 0x0F0C3701
@@ -6202,7 +6231,7 @@
#define DDRSS2_PHY_1052_DATA 0x00000033
#define DDRSS2_PHY_1053_DATA 0x00543210
#define DDRSS2_PHY_1054_DATA 0x003F0000
-#define DDRSS2_PHY_1055_DATA 0x000F013F
+#define DDRSS2_PHY_1055_DATA 0x000F3F3F
#define DDRSS2_PHY_1056_DATA 0x20202003
#define DDRSS2_PHY_1057_DATA 0x00202020
#define DDRSS2_PHY_1058_DATA 0x20008008
@@ -6450,7 +6479,7 @@
#define DDRSS2_PHY_1300_DATA 0x00040101
#define DDRSS2_PHY_1301_DATA 0x0000010F
#define DDRSS2_PHY_1302_DATA 0x00000000
-#define DDRSS2_PHY_1303_DATA 0x0000FFFF
+#define DDRSS2_PHY_1303_DATA 0x00000064
#define DDRSS2_PHY_1304_DATA 0x00000000
#define DDRSS2_PHY_1305_DATA 0x01010000
#define DDRSS2_PHY_1306_DATA 0x01080402
@@ -6544,7 +6573,7 @@
#define DDRSS2_PHY_1394_DATA 0x00000003
#define DDRSS2_PHY_1395_DATA 0x00000000
#define DDRSS2_PHY_1396_DATA 0x00001142
-#define DDRSS2_PHY_1397_DATA 0x010207AB
+#define DDRSS2_PHY_1397_DATA 0x040207AB
#define DDRSS2_PHY_1398_DATA 0x01000080
#define DDRSS2_PHY_1399_DATA 0x03900390
#define DDRSS2_PHY_1400_DATA 0x03900390
@@ -6591,7 +6620,7 @@
#define DDRSS3_CTL_17_DATA 0x00000005
#define DDRSS3_CTL_18_DATA 0x000010A9
#define DDRSS3_CTL_19_DATA 0x01010000
-#define DDRSS3_CTL_20_DATA 0x02011001
+#define DDRSS3_CTL_20_DATA 0x01011001
#define DDRSS3_CTL_21_DATA 0x02010000
#define DDRSS3_CTL_22_DATA 0x00020100
#define DDRSS3_CTL_23_DATA 0x0000000B
@@ -6606,7 +6635,7 @@
#define DDRSS3_CTL_32_DATA 0x00000000
#define DDRSS3_CTL_33_DATA 0x00000000
#define DDRSS3_CTL_34_DATA 0x040C0000
-#define DDRSS3_CTL_35_DATA 0x12481248
+#define DDRSS3_CTL_35_DATA 0x12501250
#define DDRSS3_CTL_36_DATA 0x00050804
#define DDRSS3_CTL_37_DATA 0x09040008
#define DDRSS3_CTL_38_DATA 0x15000204
@@ -6621,27 +6650,27 @@
#define DDRSS3_CTL_47_DATA 0x1E161110
#define DDRSS3_CTL_48_DATA 0x1000922C
#define DDRSS3_CTL_49_DATA 0x02030410
-#define DDRSS3_CTL_50_DATA 0x2C040500
+#define DDRSS3_CTL_50_DATA 0x2C060500
#define DDRSS3_CTL_51_DATA 0x08292C29
#define DDRSS3_CTL_52_DATA 0x14000E0A
#define DDRSS3_CTL_53_DATA 0x04010A0A
#define DDRSS3_CTL_54_DATA 0x01010004
-#define DDRSS3_CTL_55_DATA 0x04545408
+#define DDRSS3_CTL_55_DATA 0x0454540A
#define DDRSS3_CTL_56_DATA 0x04313104
#define DDRSS3_CTL_57_DATA 0x00003131
#define DDRSS3_CTL_58_DATA 0x00010100
#define DDRSS3_CTL_59_DATA 0x03010000
#define DDRSS3_CTL_60_DATA 0x00001508
-#define DDRSS3_CTL_61_DATA 0x00000063
+#define DDRSS3_CTL_61_DATA 0x00000068
#define DDRSS3_CTL_62_DATA 0x0000032B
#define DDRSS3_CTL_63_DATA 0x00001035
#define DDRSS3_CTL_64_DATA 0x0000032B
#define DDRSS3_CTL_65_DATA 0x00001035
#define DDRSS3_CTL_66_DATA 0x00000005
#define DDRSS3_CTL_67_DATA 0x00050000
-#define DDRSS3_CTL_68_DATA 0x00CB0012
-#define DDRSS3_CTL_69_DATA 0x00CB0408
-#define DDRSS3_CTL_70_DATA 0x00400408
+#define DDRSS3_CTL_68_DATA 0x00CB0005
+#define DDRSS3_CTL_69_DATA 0x00CB0200
+#define DDRSS3_CTL_70_DATA 0x00400200
#define DDRSS3_CTL_71_DATA 0x00120103
#define DDRSS3_CTL_72_DATA 0x00100005
#define DDRSS3_CTL_73_DATA 0x2F080010
@@ -6747,22 +6776,22 @@
#define DDRSS3_CTL_173_DATA 0x00000000
#define DDRSS3_CTL_174_DATA 0x00000000
#define DDRSS3_CTL_175_DATA 0x3FF40084
-#define DDRSS3_CTL_176_DATA 0x33003FF4
-#define DDRSS3_CTL_177_DATA 0x00003333
-#define DDRSS3_CTL_178_DATA 0x35000000
+#define DDRSS3_CTL_176_DATA 0xF3003FF4
+#define DDRSS3_CTL_177_DATA 0x0000F3F3
+#define DDRSS3_CTL_178_DATA 0x35350000
#define DDRSS3_CTL_179_DATA 0x27270035
#define DDRSS3_CTL_180_DATA 0x0F0F0000
#define DDRSS3_CTL_181_DATA 0x16000000
#define DDRSS3_CTL_182_DATA 0x00841616
#define DDRSS3_CTL_183_DATA 0x3FF43FF4
-#define DDRSS3_CTL_184_DATA 0x33333300
+#define DDRSS3_CTL_184_DATA 0xF3F3F300
#define DDRSS3_CTL_185_DATA 0x00000000
-#define DDRSS3_CTL_186_DATA 0x00353500
+#define DDRSS3_CTL_186_DATA 0x00353535
#define DDRSS3_CTL_187_DATA 0x00002727
#define DDRSS3_CTL_188_DATA 0x00000F0F
#define DDRSS3_CTL_189_DATA 0x16161600
#define DDRSS3_CTL_190_DATA 0x00000020
-#define DDRSS3_CTL_191_DATA 0x00000000
+#define DDRSS3_CTL_191_DATA 0x01000000
#define DDRSS3_CTL_192_DATA 0x00000001
#define DDRSS3_CTL_193_DATA 0x00000000
#define DDRSS3_CTL_194_DATA 0x01000000
@@ -6862,14 +6891,14 @@
#define DDRSS3_CTL_288_DATA 0x00000000
#define DDRSS3_CTL_289_DATA 0x00000000
#define DDRSS3_CTL_290_DATA 0x03030300
-#define DDRSS3_CTL_291_DATA 0x00000001
+#define DDRSS3_CTL_291_DATA 0x00010101
#define DDRSS3_CTL_292_DATA 0x00000000
#define DDRSS3_CTL_293_DATA 0x00000000
#define DDRSS3_CTL_294_DATA 0x00000000
#define DDRSS3_CTL_295_DATA 0x00000000
#define DDRSS3_CTL_296_DATA 0x00000000
-#define DDRSS3_CTL_297_DATA 0x00000000
-#define DDRSS3_CTL_298_DATA 0x00000000
+#define DDRSS3_CTL_297_DATA 0xFFFFFFFF
+#define DDRSS3_CTL_298_DATA 0x00000FFF
#define DDRSS3_CTL_299_DATA 0x00000000
#define DDRSS3_CTL_300_DATA 0x00000000
#define DDRSS3_CTL_301_DATA 0x00000000
@@ -6890,7 +6919,7 @@
#define DDRSS3_CTL_316_DATA 0x01010001
#define DDRSS3_CTL_317_DATA 0x00010101
#define DDRSS3_CTL_318_DATA 0x050A0A03
-#define DDRSS3_CTL_319_DATA 0x10081F1F
+#define DDRSS3_CTL_319_DATA 0x10082323
#define DDRSS3_CTL_320_DATA 0x00090310
#define DDRSS3_CTL_321_DATA 0x0B0C030F
#define DDRSS3_CTL_322_DATA 0x0B0C0306
@@ -6965,7 +6994,7 @@
#define DDRSS3_CTL_391_DATA 0x00000200
#define DDRSS3_CTL_392_DATA 0x00000200
#define DDRSS3_CTL_393_DATA 0x00000200
-#define DDRSS3_CTL_394_DATA 0x00000252
+#define DDRSS3_CTL_394_DATA 0x00000270
#define DDRSS3_CTL_395_DATA 0x000007BC
#define DDRSS3_CTL_396_DATA 0x00000204
#define DDRSS3_CTL_397_DATA 0x0000206A
@@ -6975,7 +7004,7 @@
#define DDRSS3_CTL_401_DATA 0x00000200
#define DDRSS3_CTL_402_DATA 0x0000613E
#define DDRSS3_CTL_403_DATA 0x00014424
-#define DDRSS3_CTL_404_DATA 0x00000E15
+#define DDRSS3_CTL_404_DATA 0x00000E19
#define DDRSS3_CTL_405_DATA 0x0000206A
#define DDRSS3_CTL_406_DATA 0x00000200
#define DDRSS3_CTL_407_DATA 0x00000200
@@ -6983,7 +7012,7 @@
#define DDRSS3_CTL_409_DATA 0x00000200
#define DDRSS3_CTL_410_DATA 0x0000613E
#define DDRSS3_CTL_411_DATA 0x00014424
-#define DDRSS3_CTL_412_DATA 0x02020E15
+#define DDRSS3_CTL_412_DATA 0x02020E19
#define DDRSS3_CTL_413_DATA 0x03030202
#define DDRSS3_CTL_414_DATA 0x00000022
#define DDRSS3_CTL_415_DATA 0x00000000
@@ -7000,7 +7029,7 @@
#define DDRSS3_CTL_426_DATA 0x00000000
#define DDRSS3_CTL_427_DATA 0x02000000
#define DDRSS3_CTL_428_DATA 0x01000404
-#define DDRSS3_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS3_CTL_429_DATA 0x0B220B22
#define DDRSS3_CTL_430_DATA 0x00000105
#define DDRSS3_CTL_431_DATA 0x00010101
#define DDRSS3_CTL_432_DATA 0x00010101
@@ -7043,8 +7072,8 @@
#define DDRSS3_PI_09_DATA 0x00000000
#define DDRSS3_PI_10_DATA 0x00000000
#define DDRSS3_PI_11_DATA 0x00000000
-#define DDRSS3_PI_12_DATA 0x00000007
-#define DDRSS3_PI_13_DATA 0x00010002
+#define DDRSS3_PI_12_DATA 0x00000003
+#define DDRSS3_PI_13_DATA 0x00010001
#define DDRSS3_PI_14_DATA 0x0800000F
#define DDRSS3_PI_15_DATA 0x00000103
#define DDRSS3_PI_16_DATA 0x00000005
@@ -7092,18 +7121,18 @@
#define DDRSS3_PI_58_DATA 0x00000000
#define DDRSS3_PI_59_DATA 0x00000000
#define DDRSS3_PI_60_DATA 0x0A0A140A
-#define DDRSS3_PI_61_DATA 0x10020101
+#define DDRSS3_PI_61_DATA 0x10020201
#define DDRSS3_PI_62_DATA 0x00020805
#define DDRSS3_PI_63_DATA 0x01000404
#define DDRSS3_PI_64_DATA 0x00000000
#define DDRSS3_PI_65_DATA 0x00000000
#define DDRSS3_PI_66_DATA 0x00000100
-#define DDRSS3_PI_67_DATA 0x0001010F
+#define DDRSS3_PI_67_DATA 0x0002020F
#define DDRSS3_PI_68_DATA 0x00340000
#define DDRSS3_PI_69_DATA 0x00000000
#define DDRSS3_PI_70_DATA 0x00000000
#define DDRSS3_PI_71_DATA 0x0000FFFF
-#define DDRSS3_PI_72_DATA 0x00000000
+#define DDRSS3_PI_72_DATA 0x01000000
#define DDRSS3_PI_73_DATA 0x00080000
#define DDRSS3_PI_74_DATA 0x02000200
#define DDRSS3_PI_75_DATA 0x01000100
@@ -7192,37 +7221,37 @@
#define DDRSS3_PI_158_DATA 0x00000000
#define DDRSS3_PI_159_DATA 0x00000401
#define DDRSS3_PI_160_DATA 0x00000000
-#define DDRSS3_PI_161_DATA 0x00010000
-#define DDRSS3_PI_162_DATA 0x00000000
-#define DDRSS3_PI_163_DATA 0x2B2B0200
+#define DDRSS3_PI_161_DATA 0x05010000
+#define DDRSS3_PI_162_DATA 0x00000001
+#define DDRSS3_PI_163_DATA 0x2B2B0201
#define DDRSS3_PI_164_DATA 0x00000034
-#define DDRSS3_PI_165_DATA 0x00000064
-#define DDRSS3_PI_166_DATA 0x00020064
+#define DDRSS3_PI_165_DATA 0x00000068
+#define DDRSS3_PI_166_DATA 0x00020068
#define DDRSS3_PI_167_DATA 0x02000200
-#define DDRSS3_PI_168_DATA 0x48120C04
-#define DDRSS3_PI_169_DATA 0x00154812
-#define DDRSS3_PI_170_DATA 0x00000063
+#define DDRSS3_PI_168_DATA 0x50120C04
+#define DDRSS3_PI_169_DATA 0x00155012
+#define DDRSS3_PI_170_DATA 0x00000068
#define DDRSS3_PI_171_DATA 0x0000032B
#define DDRSS3_PI_172_DATA 0x00001035
#define DDRSS3_PI_173_DATA 0x0000032B
#define DDRSS3_PI_174_DATA 0x04001035
#define DDRSS3_PI_175_DATA 0x01010404
-#define DDRSS3_PI_176_DATA 0x00001501
+#define DDRSS3_PI_176_DATA 0x00001500
#define DDRSS3_PI_177_DATA 0x00150015
#define DDRSS3_PI_178_DATA 0x01000100
#define DDRSS3_PI_179_DATA 0x00000100
#define DDRSS3_PI_180_DATA 0x00000000
#define DDRSS3_PI_181_DATA 0x01010101
-#define DDRSS3_PI_182_DATA 0x00000101
+#define DDRSS3_PI_182_DATA 0x00000000
#define DDRSS3_PI_183_DATA 0x00000000
#define DDRSS3_PI_184_DATA 0x00000000
-#define DDRSS3_PI_185_DATA 0x15040000
-#define DDRSS3_PI_186_DATA 0x0E0E0215
+#define DDRSS3_PI_185_DATA 0x19040000
+#define DDRSS3_PI_186_DATA 0x0E0E0219
#define DDRSS3_PI_187_DATA 0x00040402
#define DDRSS3_PI_188_DATA 0x000D0035
#define DDRSS3_PI_189_DATA 0x00218049
#define DDRSS3_PI_190_DATA 0x00218049
-#define DDRSS3_PI_191_DATA 0x01010101
+#define DDRSS3_PI_191_DATA 0x01000101
#define DDRSS3_PI_192_DATA 0x0004000E
#define DDRSS3_PI_193_DATA 0x00040216
#define DDRSS3_PI_194_DATA 0x01000216
@@ -7230,8 +7259,8 @@
#define DDRSS3_PI_196_DATA 0x02170100
#define DDRSS3_PI_197_DATA 0x01000217
#define DDRSS3_PI_198_DATA 0x02170217
-#define DDRSS3_PI_199_DATA 0x32103200
-#define DDRSS3_PI_200_DATA 0x01013210
+#define DDRSS3_PI_199_DATA 0x2F1B3200
+#define DDRSS3_PI_200_DATA 0x01012F1B
#define DDRSS3_PI_201_DATA 0x0A070601
#define DDRSS3_PI_202_DATA 0x1F130A0D
#define DDRSS3_PI_203_DATA 0x1F130A14
@@ -7243,13 +7272,13 @@
#define DDRSS3_PI_209_DATA 0x00240216
#define DDRSS3_PI_210_DATA 0x00110216
#define DDRSS3_PI_211_DATA 0x32000056
-#define DDRSS3_PI_212_DATA 0x00000301
-#define DDRSS3_PI_213_DATA 0x005B0036
+#define DDRSS3_PI_212_DATA 0x00000101
+#define DDRSS3_PI_213_DATA 0x005F0036
#define DDRSS3_PI_214_DATA 0x03013212
#define DDRSS3_PI_215_DATA 0x00003600
-#define DDRSS3_PI_216_DATA 0x3212005B
-#define DDRSS3_PI_217_DATA 0x09000301
-#define DDRSS3_PI_218_DATA 0x04010504
+#define DDRSS3_PI_216_DATA 0x3212005F
+#define DDRSS3_PI_217_DATA 0x09000001
+#define DDRSS3_PI_218_DATA 0x06010504
#define DDRSS3_PI_219_DATA 0x04000364
#define DDRSS3_PI_220_DATA 0x0A032001
#define DDRSS3_PI_221_DATA 0x2C31110A
@@ -7306,29 +7335,29 @@
#define DDRSS3_PI_272_DATA 0x00080804
#define DDRSS3_PI_273_DATA 0x00000000
#define DDRSS3_PI_274_DATA 0x00000000
-#define DDRSS3_PI_275_DATA 0x00330084
+#define DDRSS3_PI_275_DATA 0x35F30084
#define DDRSS3_PI_276_DATA 0x00160000
-#define DDRSS3_PI_277_DATA 0x35333FF4
+#define DDRSS3_PI_277_DATA 0x35F33FF4
#define DDRSS3_PI_278_DATA 0x00160F27
-#define DDRSS3_PI_279_DATA 0x35333FF4
+#define DDRSS3_PI_279_DATA 0x35F33FF4
#define DDRSS3_PI_280_DATA 0x00160F27
-#define DDRSS3_PI_281_DATA 0x00330084
+#define DDRSS3_PI_281_DATA 0x35F30084
#define DDRSS3_PI_282_DATA 0x00160000
-#define DDRSS3_PI_283_DATA 0x35333FF4
+#define DDRSS3_PI_283_DATA 0x35F33FF4
#define DDRSS3_PI_284_DATA 0x00160F27
-#define DDRSS3_PI_285_DATA 0x35333FF4
+#define DDRSS3_PI_285_DATA 0x35F33FF4
#define DDRSS3_PI_286_DATA 0x00160F27
-#define DDRSS3_PI_287_DATA 0x00330084
+#define DDRSS3_PI_287_DATA 0x35F30084
#define DDRSS3_PI_288_DATA 0x00160000
-#define DDRSS3_PI_289_DATA 0x35333FF4
+#define DDRSS3_PI_289_DATA 0x35F33FF4
#define DDRSS3_PI_290_DATA 0x00160F27
-#define DDRSS3_PI_291_DATA 0x35333FF4
+#define DDRSS3_PI_291_DATA 0x35F33FF4
#define DDRSS3_PI_292_DATA 0x00160F27
-#define DDRSS3_PI_293_DATA 0x00330084
+#define DDRSS3_PI_293_DATA 0x35F30084
#define DDRSS3_PI_294_DATA 0x00160000
-#define DDRSS3_PI_295_DATA 0x35333FF4
+#define DDRSS3_PI_295_DATA 0x35F33FF4
#define DDRSS3_PI_296_DATA 0x00160F27
-#define DDRSS3_PI_297_DATA 0x35333FF4
+#define DDRSS3_PI_297_DATA 0x35F33FF4
#define DDRSS3_PI_298_DATA 0x00160F27
#define DDRSS3_PI_299_DATA 0x00000000
@@ -7344,7 +7373,7 @@
#define DDRSS3_PHY_09_DATA 0x00000000
#define DDRSS3_PHY_10_DATA 0x00000000
#define DDRSS3_PHY_11_DATA 0x01000001
-#define DDRSS3_PHY_12_DATA 0x00000100
+#define DDRSS3_PHY_12_DATA 0x00000200
#define DDRSS3_PHY_13_DATA 0x000800C0
#define DDRSS3_PHY_14_DATA 0x060100CC
#define DDRSS3_PHY_15_DATA 0x00030066
@@ -7363,7 +7392,7 @@
#define DDRSS3_PHY_28_DATA 0x2A000000
#define DDRSS3_PHY_29_DATA 0x00000808
#define DDRSS3_PHY_30_DATA 0x0F000000
-#define DDRSS3_PHY_31_DATA 0x00000F0F
+#define DDRSS3_PHY_31_DATA 0x00000F08
#define DDRSS3_PHY_32_DATA 0x10400000
#define DDRSS3_PHY_33_DATA 0x0C002006
#define DDRSS3_PHY_34_DATA 0x00000000
@@ -7432,9 +7461,9 @@
#define DDRSS3_PHY_97_DATA 0x00050010
#define DDRSS3_PHY_98_DATA 0x51517041
#define DDRSS3_PHY_99_DATA 0x31C06001
-#define DDRSS3_PHY_100_DATA 0x07AB0340
+#define DDRSS3_PHY_100_DATA 0x07AB01AB
#define DDRSS3_PHY_101_DATA 0x00C0C001
-#define DDRSS3_PHY_102_DATA 0x0E0D0001
+#define DDRSS3_PHY_102_DATA 0x0E0D0101
#define DDRSS3_PHY_103_DATA 0x10001000
#define DDRSS3_PHY_104_DATA 0x0C083E42
#define DDRSS3_PHY_105_DATA 0x0F0C3701
@@ -7600,7 +7629,7 @@
#define DDRSS3_PHY_265_DATA 0x00000000
#define DDRSS3_PHY_266_DATA 0x00000000
#define DDRSS3_PHY_267_DATA 0x01000001
-#define DDRSS3_PHY_268_DATA 0x00000100
+#define DDRSS3_PHY_268_DATA 0x00000200
#define DDRSS3_PHY_269_DATA 0x000800C0
#define DDRSS3_PHY_270_DATA 0x060100CC
#define DDRSS3_PHY_271_DATA 0x00030066
@@ -7619,7 +7648,7 @@
#define DDRSS3_PHY_284_DATA 0x2A000000
#define DDRSS3_PHY_285_DATA 0x00000808
#define DDRSS3_PHY_286_DATA 0x0F000000
-#define DDRSS3_PHY_287_DATA 0x00000F0F
+#define DDRSS3_PHY_287_DATA 0x00000F08
#define DDRSS3_PHY_288_DATA 0x10400000
#define DDRSS3_PHY_289_DATA 0x0C002006
#define DDRSS3_PHY_290_DATA 0x00000000
@@ -7688,9 +7717,9 @@
#define DDRSS3_PHY_353_DATA 0x00050010
#define DDRSS3_PHY_354_DATA 0x51517041
#define DDRSS3_PHY_355_DATA 0x31C06001
-#define DDRSS3_PHY_356_DATA 0x07AB0340
+#define DDRSS3_PHY_356_DATA 0x07AB01AB
#define DDRSS3_PHY_357_DATA 0x00C0C001
-#define DDRSS3_PHY_358_DATA 0x0E0D0001
+#define DDRSS3_PHY_358_DATA 0x0E0D0101
#define DDRSS3_PHY_359_DATA 0x10001000
#define DDRSS3_PHY_360_DATA 0x0C083E42
#define DDRSS3_PHY_361_DATA 0x0F0C3701
@@ -7856,7 +7885,7 @@
#define DDRSS3_PHY_521_DATA 0x00000000
#define DDRSS3_PHY_522_DATA 0x00000000
#define DDRSS3_PHY_523_DATA 0x01000001
-#define DDRSS3_PHY_524_DATA 0x00000100
+#define DDRSS3_PHY_524_DATA 0x00000200
#define DDRSS3_PHY_525_DATA 0x000800C0
#define DDRSS3_PHY_526_DATA 0x060100CC
#define DDRSS3_PHY_527_DATA 0x00030066
@@ -7875,7 +7904,7 @@
#define DDRSS3_PHY_540_DATA 0x2A000000
#define DDRSS3_PHY_541_DATA 0x00000808
#define DDRSS3_PHY_542_DATA 0x0F000000
-#define DDRSS3_PHY_543_DATA 0x00000F0F
+#define DDRSS3_PHY_543_DATA 0x00000F08
#define DDRSS3_PHY_544_DATA 0x10400000
#define DDRSS3_PHY_545_DATA 0x0C002006
#define DDRSS3_PHY_546_DATA 0x00000000
@@ -7944,9 +7973,9 @@
#define DDRSS3_PHY_609_DATA 0x00050010
#define DDRSS3_PHY_610_DATA 0x51517041
#define DDRSS3_PHY_611_DATA 0x31C06001
-#define DDRSS3_PHY_612_DATA 0x07AB0340
+#define DDRSS3_PHY_612_DATA 0x07AB01AB
#define DDRSS3_PHY_613_DATA 0x00C0C001
-#define DDRSS3_PHY_614_DATA 0x0E0D0001
+#define DDRSS3_PHY_614_DATA 0x0E0D0101
#define DDRSS3_PHY_615_DATA 0x10001000
#define DDRSS3_PHY_616_DATA 0x0C083E42
#define DDRSS3_PHY_617_DATA 0x0F0C3701
@@ -8112,7 +8141,7 @@
#define DDRSS3_PHY_777_DATA 0x00000000
#define DDRSS3_PHY_778_DATA 0x00000000
#define DDRSS3_PHY_779_DATA 0x01000001
-#define DDRSS3_PHY_780_DATA 0x00000100
+#define DDRSS3_PHY_780_DATA 0x00000200
#define DDRSS3_PHY_781_DATA 0x000800C0
#define DDRSS3_PHY_782_DATA 0x060100CC
#define DDRSS3_PHY_783_DATA 0x00030066
@@ -8131,7 +8160,7 @@
#define DDRSS3_PHY_796_DATA 0x2A000000
#define DDRSS3_PHY_797_DATA 0x00000808
#define DDRSS3_PHY_798_DATA 0x0F000000
-#define DDRSS3_PHY_799_DATA 0x00000F0F
+#define DDRSS3_PHY_799_DATA 0x00000F08
#define DDRSS3_PHY_800_DATA 0x10400000
#define DDRSS3_PHY_801_DATA 0x0C002006
#define DDRSS3_PHY_802_DATA 0x00000000
@@ -8200,9 +8229,9 @@
#define DDRSS3_PHY_865_DATA 0x00050010
#define DDRSS3_PHY_866_DATA 0x51517041
#define DDRSS3_PHY_867_DATA 0x31C06001
-#define DDRSS3_PHY_868_DATA 0x07AB0340
+#define DDRSS3_PHY_868_DATA 0x07AB01AB
#define DDRSS3_PHY_869_DATA 0x00C0C001
-#define DDRSS3_PHY_870_DATA 0x0E0D0001
+#define DDRSS3_PHY_870_DATA 0x0E0D0101
#define DDRSS3_PHY_871_DATA 0x10001000
#define DDRSS3_PHY_872_DATA 0x0C083E42
#define DDRSS3_PHY_873_DATA 0x0F0C3701
@@ -8387,7 +8416,7 @@
#define DDRSS3_PHY_1052_DATA 0x00000033
#define DDRSS3_PHY_1053_DATA 0x00543210
#define DDRSS3_PHY_1054_DATA 0x003F0000
-#define DDRSS3_PHY_1055_DATA 0x000F013F
+#define DDRSS3_PHY_1055_DATA 0x000F3F3F
#define DDRSS3_PHY_1056_DATA 0x20202003
#define DDRSS3_PHY_1057_DATA 0x00202020
#define DDRSS3_PHY_1058_DATA 0x20008008
@@ -8635,7 +8664,7 @@
#define DDRSS3_PHY_1300_DATA 0x00040101
#define DDRSS3_PHY_1301_DATA 0x0000010F
#define DDRSS3_PHY_1302_DATA 0x00000000
-#define DDRSS3_PHY_1303_DATA 0x0000FFFF
+#define DDRSS3_PHY_1303_DATA 0x00000064
#define DDRSS3_PHY_1304_DATA 0x00000000
#define DDRSS3_PHY_1305_DATA 0x01010000
#define DDRSS3_PHY_1306_DATA 0x01080402
@@ -8729,7 +8758,7 @@
#define DDRSS3_PHY_1394_DATA 0x00000003
#define DDRSS3_PHY_1395_DATA 0x00000000
#define DDRSS3_PHY_1396_DATA 0x00001142
-#define DDRSS3_PHY_1397_DATA 0x010207AB
+#define DDRSS3_PHY_1397_DATA 0x040207AB
#define DDRSS3_PHY_1398_DATA 0x01000080
#define DDRSS3_PHY_1399_DATA 0x03900390
#define DDRSS3_PHY_1400_DATA 0x03900390
--
2.34.1
next prev parent reply other threads:[~2025-11-03 7:11 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-03 7:10 [PATCH v2 0/7] ti: j7: Update to v0.12.0 of DDR config tool Neha Malcom Francis
2025-11-03 7:10 ` [PATCH v2 1/7] arm: dts: k3-j7200: ddr: " Neha Malcom Francis
2025-11-03 7:10 ` [PATCH v2 2/7] arm: dts: k3-j721s2: " Neha Malcom Francis
2025-11-03 7:10 ` [PATCH v2 3/7] arm: dts: k3-am68: " Neha Malcom Francis
2025-11-03 7:10 ` Neha Malcom Francis [this message]
2025-11-03 7:10 ` [PATCH v2 5/7] arm: dts: k3-am69: " Neha Malcom Francis
2025-11-07 15:44 ` Franz Schnyder
2025-11-10 4:25 ` Neha Malcom Francis
2025-11-20 8:16 ` Francesco Dolcini
2025-11-20 14:23 ` [EXTERNAL] " Scholz, Kevin
2025-11-20 14:48 ` Francesco Dolcini
2026-04-21 10:10 ` Neha Malcom Francis
2026-05-20 21:52 ` Scholz, Kevin
2026-05-21 5:47 ` Neha Malcom Francis
2026-05-21 6:26 ` Francesco Dolcini
2026-06-09 4:25 ` Kumar, Udit
2025-11-03 7:10 ` [PATCH v2 6/7] arm: dts: k3-j742s2: " Neha Malcom Francis
2025-11-03 7:10 ` [PATCH v2 7/7] doc: ti: k3: Add section for DDR configuration Neha Malcom Francis
2025-11-03 14:35 ` Romain Naour
2026-05-21 5:45 ` Neha Malcom Francis
2026-06-09 19:17 ` [PATCH v2 0/7] ti: j7: Update to v0.12.0 of DDR config tool Tom Rini
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