From: Neha Malcom Francis <n-francis@ti.com>
To: "Scholz, Kevin" <k-scholz@ti.com>,
Franz Schnyder <fra.schnyder@gmail.com>
Cc: <trini@konsulko.com>, <s-k6@ti.com>, <bb@ti.com>,
<m-chawdhry@ti.com>, <u-boot@lists.denx.de>, <u-kumar1@ti.com>,
<gehariprasath@ti.com>, "Franz Schnyder" <fra.schnyder@gmail.com>
Subject: Re: [PATCH v2 5/7] arm: dts: k3-am69: ddr: Update to v0.12.0 of DDR config tool
Date: Mon, 10 Nov 2025 09:55:08 +0530 [thread overview]
Message-ID: <2b1b5496-cbd2-4ac4-85cc-2b8da653bbdd@ti.com> (raw)
In-Reply-To: <btgc6fvqwkqlnnmqicvobikkyjpib5lgvda7tfyguwn25bmd2s@hdhibzylbig7>
+ Kevin
On 07/11/25 21:14, Franz Schnyder wrote:
> Hi Neha,
>
> On Mon, Nov 03, 2025 at 12:40:33PM +0530, Neha Malcom Francis wrote:
>> +#define DDRSS0_CTL_178_DATA 0x35000000
>> +#define DDRSS0_CTL_186_DATA 0x00353500
>> +#define DDRSS0_PI_275_DATA 0x00F30084
>> +#define DDRSS0_PI_281_DATA 0x00F30084
>> +#define DDRSS0_PI_287_DATA 0x00F30084
>> +#define DDRSS0_PI_293_DATA 0x00F30084
>> ....
>> +#define DDRSS1_CTL_178_DATA 0x35000000
>> +#define DDRSS1_CTL_186_DATA 0x00353500
>> +#define DDRSS1_PI_275_DATA 0x00F30084
>> +#define DDRSS1_PI_281_DATA 0x00F30084
>> +#define DDRSS1_PI_287_DATA 0x00F30084
>> +#define DDRSS1_PI_293_DATA 0x00F30084
>> ....
>> +#define DDRSS2_CTL_178_DATA 0x35000000
>> +#define DDRSS2_CTL_186_DATA 0x00353500
>> +#define DDRSS2_PI_275_DATA 0x00F30084
>> +#define DDRSS2_PI_281_DATA 0x00F30084
>> +#define DDRSS2_PI_287_DATA 0x00F30084
>> +#define DDRSS2_PI_293_DATA 0x00F30084
>> ....
>> +#define DDRSS3_CTL_178_DATA 0x35350000
>> +#define DDRSS3_CTL_186_DATA 0x00353535
>> +#define DDRSS3_PI_275_DATA 0x35F30084
>> +#define DDRSS3_PI_281_DATA 0x35F30084
>> +#define DDRSS3_PI_287_DATA 0x35F30084
>> +#define DDRSS3_PI_293_DATA 0x35F30084
>
> When I compare the updated configuration to the one for our Aquila AM69
> board, I can observe that you have set an on-die termination at boot
> frequency only for DRAM3. DRAM, DRAM1 and DRAM2 do not seem to have any
> termination enabled. Is this a mistake or is it intentional?
Kevin, could you explain the reasoning for this?
>
> kind regards,
>
> Franz
>
--
Thanking You
Neha Malcom Francis
next prev parent reply other threads:[~2025-11-10 4:25 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-03 7:10 [PATCH v2 0/7] ti: j7: Update to v0.12.0 of DDR config tool Neha Malcom Francis
2025-11-03 7:10 ` [PATCH v2 1/7] arm: dts: k3-j7200: ddr: " Neha Malcom Francis
2025-11-03 7:10 ` [PATCH v2 2/7] arm: dts: k3-j721s2: " Neha Malcom Francis
2025-11-03 7:10 ` [PATCH v2 3/7] arm: dts: k3-am68: " Neha Malcom Francis
2025-11-03 7:10 ` [PATCH v2 4/7] arm: dts: k3-j784s4: " Neha Malcom Francis
2025-11-03 7:10 ` [PATCH v2 5/7] arm: dts: k3-am69: " Neha Malcom Francis
2025-11-07 15:44 ` Franz Schnyder
2025-11-10 4:25 ` Neha Malcom Francis [this message]
2025-11-20 8:16 ` Francesco Dolcini
2025-11-20 14:23 ` [EXTERNAL] " Scholz, Kevin
2025-11-20 14:48 ` Francesco Dolcini
2026-04-21 10:10 ` Neha Malcom Francis
2026-05-20 21:52 ` Scholz, Kevin
2026-05-21 5:47 ` Neha Malcom Francis
2026-05-21 6:26 ` Francesco Dolcini
2026-06-09 4:25 ` Kumar, Udit
2025-11-03 7:10 ` [PATCH v2 6/7] arm: dts: k3-j742s2: " Neha Malcom Francis
2025-11-03 7:10 ` [PATCH v2 7/7] doc: ti: k3: Add section for DDR configuration Neha Malcom Francis
2025-11-03 14:35 ` Romain Naour
2026-05-21 5:45 ` Neha Malcom Francis
2026-06-09 19:17 ` [PATCH v2 0/7] ti: j7: Update to v0.12.0 of DDR config tool Tom Rini
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