From: Sairaj Kodilkar <sarunkod@amd.com>
To: <qemu-devel@nongnu.org>
Cc: <alejandro.j.jimenez@oracle.com>, <pbonzini@redhat.com>,
<richard.henderson@linaro.org>, <eduardo@habkost.net>,
<mst@redhat.com>, <marcel.apfelbaum@gmail.com>,
Sairaj Kodilkar <sarunkod@amd.com>
Subject: [PATCH 1/3] amd_iommu: Use switch case to determine mmio register name
Date: Tue, 18 Nov 2025 13:54:01 +0530 [thread overview]
Message-ID: <20251118082403.3455-2-sarunkod@amd.com> (raw)
In-Reply-To: <20251118082403.3455-1-sarunkod@amd.com>
This makes it easier to add new MMIO registers for tracing and removes
the unnecessary complexity introduced by amdvi_mmio_(low/high) array.
Signed-off-by: Sairaj Kodilkar <sarunkod@amd.com>
---
hw/i386/amd_iommu.c | 76 +++++++++++++++++++++++----------------------
1 file changed, 39 insertions(+), 37 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index d689a06eca46..a9ee7150ef17 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -35,28 +35,13 @@
#include "kvm/kvm_i386.h"
#include "qemu/iova-tree.h"
-/* used AMD-Vi MMIO registers */
-const char *amdvi_mmio_low[] = {
- "AMDVI_MMIO_DEVTAB_BASE",
- "AMDVI_MMIO_CMDBUF_BASE",
- "AMDVI_MMIO_EVTLOG_BASE",
- "AMDVI_MMIO_CONTROL",
- "AMDVI_MMIO_EXCL_BASE",
- "AMDVI_MMIO_EXCL_LIMIT",
- "AMDVI_MMIO_EXT_FEATURES",
- "AMDVI_MMIO_PPR_BASE",
- "UNHANDLED"
-};
-const char *amdvi_mmio_high[] = {
- "AMDVI_MMIO_COMMAND_HEAD",
- "AMDVI_MMIO_COMMAND_TAIL",
- "AMDVI_MMIO_EVTLOG_HEAD",
- "AMDVI_MMIO_EVTLOG_TAIL",
- "AMDVI_MMIO_STATUS",
- "AMDVI_MMIO_PPR_HEAD",
- "AMDVI_MMIO_PPR_TAIL",
- "UNHANDLED"
-};
+#define MMIO_REG_TO_STRING(mmio_reg, name) {\
+ case mmio_reg: \
+ name = #mmio_reg; \
+ break; \
+}
+
+#define MMIO_NAME_SIZE 50
struct AMDVIAddressSpace {
PCIBus *bus; /* PCIBus (for bus number) */
@@ -1484,31 +1469,48 @@ static void amdvi_cmdbuf_run(AMDVIState *s)
}
}
-static inline uint8_t amdvi_mmio_get_index(hwaddr addr)
-{
- uint8_t index = (addr & ~0x2000) / 8;
-
- if ((addr & 0x2000)) {
- /* high table */
- index = index >= AMDVI_MMIO_REGS_HIGH ? AMDVI_MMIO_REGS_HIGH : index;
- } else {
- index = index >= AMDVI_MMIO_REGS_LOW ? AMDVI_MMIO_REGS_LOW : index;
+static inline void amdvi_mmio_get_name(hwaddr addr,
+ char mmio_name[MMIO_NAME_SIZE])
+{
+ const char *name = NULL;
+
+ switch (addr) {
+ MMIO_REG_TO_STRING(AMDVI_MMIO_DEVICE_TABLE, name)
+ MMIO_REG_TO_STRING(AMDVI_MMIO_COMMAND_BASE, name)
+ MMIO_REG_TO_STRING(AMDVI_MMIO_EVENT_BASE, name)
+ MMIO_REG_TO_STRING(AMDVI_MMIO_CONTROL, name)
+ MMIO_REG_TO_STRING(AMDVI_MMIO_EXCL_BASE, name)
+ MMIO_REG_TO_STRING(AMDVI_MMIO_EXCL_LIMIT, name)
+ MMIO_REG_TO_STRING(AMDVI_MMIO_EXT_FEATURES, name)
+ MMIO_REG_TO_STRING(AMDVI_MMIO_COMMAND_HEAD, name)
+ MMIO_REG_TO_STRING(AMDVI_MMIO_COMMAND_TAIL, name)
+ MMIO_REG_TO_STRING(AMDVI_MMIO_EVENT_HEAD, name)
+ MMIO_REG_TO_STRING(AMDVI_MMIO_EVENT_TAIL, name)
+ MMIO_REG_TO_STRING(AMDVI_MMIO_STATUS, name)
+ MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_BASE, name)
+ MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_HEAD, name)
+ MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_TAIL, name)
+ default:
+ name = "UNHANDLED";
}
- return index;
+ strncpy(mmio_name, name, MMIO_NAME_SIZE);
}
static void amdvi_mmio_trace_read(hwaddr addr, unsigned size)
{
- uint8_t index = amdvi_mmio_get_index(addr);
- trace_amdvi_mmio_read(amdvi_mmio_low[index], addr, size, addr & ~0x07);
+ char mmio_name[MMIO_NAME_SIZE];
+
+ amdvi_mmio_get_name(addr, mmio_name);
+ trace_amdvi_mmio_read(mmio_name, addr, size, addr & ~0x07);
}
static void amdvi_mmio_trace_write(hwaddr addr, unsigned size, uint64_t val)
{
- uint8_t index = amdvi_mmio_get_index(addr);
- trace_amdvi_mmio_write(amdvi_mmio_low[index], addr, size, val,
- addr & ~0x07);
+ char mmio_name[MMIO_NAME_SIZE];
+
+ amdvi_mmio_get_name(addr, mmio_name);
+ trace_amdvi_mmio_write(mmio_name, addr, size, val, addr & ~0x07);
}
static uint64_t amdvi_mmio_read(void *opaque, hwaddr addr, unsigned size)
--
2.34.1
next prev parent reply other threads:[~2025-11-18 8:25 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-18 8:24 [PATCH 0/3] amd_iommu: Support Generation of IOMMU XT interrupts Sairaj Kodilkar
2025-11-18 8:24 ` Sairaj Kodilkar [this message]
2025-11-20 1:36 ` [PATCH 1/3] amd_iommu: Use switch case to determine mmio register name Alejandro Jimenez
2025-11-20 4:43 ` Sairaj Kodilkar
2025-11-20 13:31 ` Alejandro Jimenez
2025-11-21 5:20 ` Sairaj Kodilkar
2025-11-21 16:36 ` Alejandro Jimenez
2025-11-18 8:24 ` [PATCH 2/3] amd_iommu: Turn on XT support only when guest has enabled it Sairaj Kodilkar
2025-11-25 23:04 ` Alejandro Jimenez
2025-11-26 5:12 ` Sairaj Kodilkar
2025-11-26 12:13 ` Sairaj Kodilkar
2025-11-26 22:16 ` Alejandro Jimenez
2025-11-27 6:18 ` Sairaj Kodilkar
2025-11-18 8:24 ` [PATCH 3/3] amd_iommu: Generate XT interrupts when xt support is enabled Sairaj Kodilkar
2025-12-03 18:09 ` Alejandro Jimenez
2025-12-04 8:17 ` Sairaj Kodilkar
2025-11-19 10:38 ` [PATCH 0/3] amd_iommu: Support Generation of IOMMU XT interrupts Vasant Hegde
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