From: Sairaj Kodilkar <sarunkod@amd.com>
To: <qemu-devel@nongnu.org>
Cc: <alejandro.j.jimenez@oracle.com>, <pbonzini@redhat.com>,
<richard.henderson@linaro.org>, <eduardo@habkost.net>,
<mst@redhat.com>, <marcel.apfelbaum@gmail.com>,
Sairaj Kodilkar <sarunkod@amd.com>
Subject: [PATCH 2/3] amd_iommu: Turn on XT support only when guest has enabled it
Date: Tue, 18 Nov 2025 13:54:02 +0530 [thread overview]
Message-ID: <20251118082403.3455-3-sarunkod@amd.com> (raw)
In-Reply-To: <20251118082403.3455-1-sarunkod@amd.com>
Current code uses 32 bit cpu destination irrespective of the fact that
guest has enabled xt support through control register[XTEn] and
completely depends on command line parameter xtsup=on. This is not a
correct hardware behaviour and can cause problems in the guest which has
not enabled XT mode.
Introduce new flag "xten", which is enabled when guest writes 1 to the
control register bit 50 (XTEn).
Signed-off-by: Sairaj Kodilkar <sarunkod@amd.com>
---
hw/i386/amd_iommu.c | 3 ++-
hw/i386/amd_iommu.h | 4 +++-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index a9ee7150ef17..7f08fc31111a 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -1548,6 +1548,7 @@ static void amdvi_handle_control_write(AMDVIState *s)
s->cmdbuf_enabled = s->enabled && !!(control &
AMDVI_MMIO_CONTROL_CMDBUFLEN);
s->ga_enabled = !!(control & AMDVI_MMIO_CONTROL_GAEN);
+ s->xten = !!(control & AMDVI_MMIO_CONTROL_XTEN) && s->xtsup;
/* update the flags depending on the control register */
if (s->cmdbuf_enabled) {
@@ -2020,7 +2021,7 @@ static int amdvi_int_remap_ga(AMDVIState *iommu,
irq->vector = irte.hi.fields.vector;
irq->dest_mode = irte.lo.fields_remap.dm;
irq->redir_hint = irte.lo.fields_remap.rq_eoi;
- if (iommu->xtsup) {
+ if (iommu->xten) {
irq->dest = irte.lo.fields_remap.destination |
(irte.hi.fields.destination_hi << 24);
} else {
diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h
index 302ccca5121f..32467d0bc241 100644
--- a/hw/i386/amd_iommu.h
+++ b/hw/i386/amd_iommu.h
@@ -106,6 +106,7 @@
#define AMDVI_MMIO_CONTROL_COMWAITINTEN (1ULL << 4)
#define AMDVI_MMIO_CONTROL_CMDBUFLEN (1ULL << 12)
#define AMDVI_MMIO_CONTROL_GAEN (1ULL << 17)
+#define AMDVI_MMIO_CONTROL_XTEN (1ULL << 50)
/* MMIO status register bits */
#define AMDVI_MMIO_STATUS_CMDBUF_RUN (1 << 4)
@@ -418,7 +419,8 @@ struct AMDVIState {
/* Interrupt remapping */
bool ga_enabled;
- bool xtsup;
+ bool xtsup; /* xtsup=on command line */
+ bool xten; /* Enable x2apic */
/* DMA address translation */
bool dma_remap;
--
2.34.1
next prev parent reply other threads:[~2025-11-18 8:25 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-18 8:24 [PATCH 0/3] amd_iommu: Support Generation of IOMMU XT interrupts Sairaj Kodilkar
2025-11-18 8:24 ` [PATCH 1/3] amd_iommu: Use switch case to determine mmio register name Sairaj Kodilkar
2025-11-20 1:36 ` Alejandro Jimenez
2025-11-20 4:43 ` Sairaj Kodilkar
2025-11-20 13:31 ` Alejandro Jimenez
2025-11-21 5:20 ` Sairaj Kodilkar
2025-11-21 16:36 ` Alejandro Jimenez
2025-11-18 8:24 ` Sairaj Kodilkar [this message]
2025-11-25 23:04 ` [PATCH 2/3] amd_iommu: Turn on XT support only when guest has enabled it Alejandro Jimenez
2025-11-26 5:12 ` Sairaj Kodilkar
2025-11-26 12:13 ` Sairaj Kodilkar
2025-11-26 22:16 ` Alejandro Jimenez
2025-11-27 6:18 ` Sairaj Kodilkar
2025-11-18 8:24 ` [PATCH 3/3] amd_iommu: Generate XT interrupts when xt support is enabled Sairaj Kodilkar
2025-12-03 18:09 ` Alejandro Jimenez
2025-12-04 8:17 ` Sairaj Kodilkar
2025-11-19 10:38 ` [PATCH 0/3] amd_iommu: Support Generation of IOMMU XT interrupts Vasant Hegde
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