Re: [PATCH v4 3/5] hw/riscv: experimental server platform reference machine

[Andrew Jones <ajones@ventanamicro.com>]

On Tue, Nov 25, 2025 at 08:24:22AM -0300, Daniel Henrique Barboza wrote:
...
> So, in the latest spec, section 2.1 RISC-V Harts:
> 
> https://github.com/riscv-non-isa/riscv-server-platform/releases/download/v0.9-rc3/riscv-server-platform.pdf
> 
> There's a set of "rules" that each hart should or can follow. Rule RVA_010 states:
> 
> "The RISC-V application processor harts in the SoC MUST support the RVA23S64 ISA
> profile [6]."
> 
> The next rule, RVA_020:
> 
> "The RISC-V application processor harts in the SoC MUST support the following
> extensions:
> - Sv48
> - Sdtrig [7]
> - Sdext [7]
> - Zkr
> - Ssccfg
> - Ssstrict [6]
> - Ssaia [8]"
> 
> 
> I take it that the wording used, **MUST**, indicates that RVA_020 is mandatory so we should
> in fact support sv48. In this case we can change the default to sv48 without problems
> 
> 
> Drew, is this a fair interpretation? Thanks,

Yes. The server platform spec is based on rva23, but also mandates
additional extensions beyond what's mandated by the profile, including
sv48. (And this is why I stated the default should be sv48 when pointing
out that it shouldn't be sv57[1]).

[1] https://lore.kernel.org/all/20251111-e4f4062f326aef78ef820d00@orel/

Thanks,
drew