* Re: [PATCH v3 5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90
@ 2025-12-21 14:35 kernel test robot
0 siblings, 0 replies; 3+ messages in thread
From: kernel test robot @ 2025-12-21 14:35 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp
::::::
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
::::::
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20251216-dr1v90-cru-v3-5-52cc938d1db0@pigmoral.tech>
References: <20251216-dr1v90-cru-v3-5-52cc938d1db0@pigmoral.tech>
TO: Junhui Liu <junhui.liu@pigmoral.tech>
TO: Michael Turquette <mturquette@baylibre.com>
TO: Stephen Boyd <sboyd@kernel.org>
TO: Rob Herring <robh@kernel.org>
TO: Krzysztof Kozlowski <krzk@kernel.org>
TO: Conor Dooley <conor+dt@kernel.org>
TO: Philipp Zabel <p.zabel@pengutronix.de>
TO: Junhui Liu <junhui.liu@pigmoral.tech>
TO: Paul Walmsley <pjw@kernel.org>
TO: Palmer Dabbelt <palmer@dabbelt.com>
TO: Albert Ou <aou@eecs.berkeley.edu>
TO: Alexandre Ghiti <alex@ghiti.fr>
CC: linux-clk@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-riscv@lists.infradead.org
CC: devicetree@vger.kernel.org
Hi Junhui,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 8f0b4cce4481fb22653697cced8d0d04027cb1e8]
url: https://github.com/intel-lab-lkp/linux/commits/Junhui-Liu/clk-correct-clk_div_mask-return-value-for-width-32/20251216-115101
base: 8f0b4cce4481fb22653697cced8d0d04027cb1e8
patch link: https://lore.kernel.org/r/20251216-dr1v90-cru-v3-5-52cc938d1db0%40pigmoral.tech
patch subject: [PATCH v3 5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90
:::::: branch date: 5 days ago
:::::: commit date: 5 days ago
config: riscv-randconfig-2051-20251217 (https://download.01.org/0day-ci/archive/20251221/202512211545.fkHSicDM-lkp@intel.com/config)
compiler: riscv64-linux-gcc (GCC) 15.1.0
dtschema version: 2025.12
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251221/202512211545.fkHSicDM-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202512211545.fkHSicDM-lkp@intel.com/
dtcheck warnings: (new ones prefixed by >>)
>> arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dtb: clock-ext-can (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
>> arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dtb: clock-ext-wdt (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v3 0/6] clk/reset: anlogic: add support for DR1V90 SoC
@ 2025-12-16 3:39 Junhui Liu
2025-12-16 3:39 ` Junhui Liu
0 siblings, 1 reply; 3+ messages in thread
From: Junhui Liu @ 2025-12-16 3:39 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Junhui Liu, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: linux-clk, linux-kernel, linux-riscv, devicetree, Troy Mitchell,
Conor Dooley
Add Clock and Reset Unit (CRU) support for the Anlogic DR1V90 SoC, as
well as corresponding dts bindings and dts integration.
The CRU driver framework is built around the clock controller as the
primary device, with the reset controller implemented as an auxiliary
device. The clock part refers to the vendor's code [1] to determine the
structure of the clock tree.
The Anlogic DR1 series includes not only the DR1V90 (based on the Nuclei
UX900 RISC-V core), but also the DR1M90 (based on the Cortex-A35 ARM64
core). Most of the clock tree and CRU design can be shared between them.
This series only adds CRU support for DR1V90. Nevertheless, the driver
is structured to make future extension to other DR1 variants like
DR1M90.
Link: https://gitee.com/anlogic/linux/blob/anlogic-6.1.54/drivers/clk/anlogic/anl_dr1x90_crp.c [1]
---
Changes in v3:
- Remove incorrect __free(kfree) usage for auxiliary_device in clock
driver
- Replace __clk_get_enable_count with __clk_is_enabled in clock driver
- Add a lock to protect register read-modify-write in reset driver
- Rebase to v6.19-rc1
- Link to v2: https://lore.kernel.org/r/20251026-dr1v90-cru-v2-0-43b67acd6ddd@pigmoral.tech
Changes in v2:
- Update copyright infomation
- Add the original vendor author's infomation to the clock driver
- Rebase on the v3 basic DT patch, which is based on v6.18-rc1
- Link to v1: https://lore.kernel.org/r/20250922-dr1v90-cru-v1-0-e393d758de4e@pigmoral.tech
---
Junhui Liu (6):
clk: correct clk_div_mask() return value for width == 32
dt-bindings: clock: add Anlogic DR1V90 CRU
clk: anlogic: add cru support for Anlogic DR1V90 SoC
reset: anlogic: add support for Anlogic DR1V90 resets
riscv: dts: anlogic: add clocks and CRU for DR1V90
MAINTAINERS: Add entry for Anlogic DR1V90 SoC drivers
.../bindings/clock/anlogic,dr1v90-cru.yaml | 60 +++++
MAINTAINERS | 7 +
arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 41 +++-
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/anlogic/Kconfig | 9 +
drivers/clk/anlogic/Makefile | 5 +
drivers/clk/anlogic/cru-dr1v90.c | 191 +++++++++++++++
drivers/clk/anlogic/cru_dr1.c | 258 +++++++++++++++++++++
drivers/clk/anlogic/cru_dr1.h | 117 ++++++++++
drivers/reset/Kconfig | 9 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-dr1v90.c | 141 +++++++++++
include/dt-bindings/clock/anlogic,dr1v90-cru.h | 46 ++++
include/dt-bindings/reset/anlogic,dr1v90-cru.h | 41 ++++
include/linux/clk-provider.h | 2 +-
16 files changed, 927 insertions(+), 3 deletions(-)
---
base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8
change-id: 20250922-dr1v90-cru-74ab40c7f273
Best regards,
--
Junhui Liu <junhui.liu@pigmoral.tech>
^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH v3 5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90
2025-12-16 3:39 [PATCH v3 0/6] clk/reset: anlogic: add support for DR1V90 SoC Junhui Liu
@ 2025-12-16 3:39 ` Junhui Liu
0 siblings, 0 replies; 3+ messages in thread
From: Junhui Liu @ 2025-12-16 3:39 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Junhui Liu, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: linux-clk, linux-kernel, linux-riscv, devicetree
Add clocks and introduce the CRU (Clock and Reset) unit node
for Anlogic DR1V90 SoC, providing both clock and reset support.
The DR1V90 SoC uses three external clocks:
- A 33 MHz crystal oscillator as the main system clock.
- Two optional external clocks (via IO) for the CAN and WDT modules.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 41 +++++++++++++++++++++++++++++++--
1 file changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
index a5d0765ade3231ece0afbe8835d95cd918a44ad9..dc8358b3575124234f984c448547493d063e991f 100644
--- a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
+++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
@@ -3,6 +3,9 @@
* Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
*/
+#include <dt-bindings/clock/anlogic,dr1v90-cru.h>
+#include <dt-bindings/reset/anlogic,dr1v90-cru.h>
+
/dts-v1/;
/ {
#address-cells = <2>;
@@ -39,6 +42,27 @@ cpu0_intc: interrupt-controller {
};
};
+ clocks {
+ can_ext: clock-ext-can {
+ compatible = "fixed-clock";
+ clock-output-names = "can_ext";
+ #clock-cells = <0>;
+ };
+
+ osc_33m: clock-33m {
+ compatible = "fixed-clock";
+ clock-frequency = <33333333>;
+ clock-output-names = "osc_33m";
+ #clock-cells = <0>;
+ };
+
+ wdt_ext: clock-ext-wdt {
+ compatible = "fixed-clock";
+ clock-output-names = "wdt_ext";
+ #clock-cells = <0>;
+ };
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -80,21 +104,34 @@ plic: interrupt-controller@6c000000 {
uart0: serial@f8400000 {
compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
reg = <0x0 0xf8400000 0x0 0x1000>;
- clock-frequency = <50000000>;
+ clocks = <&cru CLK_IO_400M_DIV8>, <&cru CLK_CPU_1X>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <71>;
reg-io-width = <4>;
reg-shift = <2>;
+ resets = <&cru RESET_UART0>;
status = "disabled";
};
uart1: serial@f8401000 {
compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
reg = <0x0 0xf8401000 0x0 0x1000>;
- clock-frequency = <50000000>;
+ clocks = <&cru CLK_IO_400M_DIV8>, <&cru CLK_CPU_1X>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <72>;
reg-io-width = <4>;
reg-shift = <2>;
+ resets = <&cru RESET_UART1>;
status = "disabled";
};
+
+ cru: clock-controller@f8801000 {
+ compatible = "anlogic,dr1v90-cru";
+ reg = <0x0 0xf8801000 0 0x400>;
+ clocks = <&osc_33m>, <&can_ext>, <&wdt_ext>;
+ clock-names = "osc_33m", "can_ext", "wdt_ext";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
};
};
--
2.52.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH v3 5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90
@ 2025-12-16 3:39 ` Junhui Liu
0 siblings, 0 replies; 3+ messages in thread
From: Junhui Liu @ 2025-12-16 3:39 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Junhui Liu, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: linux-clk, linux-kernel, linux-riscv, devicetree
Add clocks and introduce the CRU (Clock and Reset) unit node
for Anlogic DR1V90 SoC, providing both clock and reset support.
The DR1V90 SoC uses three external clocks:
- A 33 MHz crystal oscillator as the main system clock.
- Two optional external clocks (via IO) for the CAN and WDT modules.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 41 +++++++++++++++++++++++++++++++--
1 file changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
index a5d0765ade3231ece0afbe8835d95cd918a44ad9..dc8358b3575124234f984c448547493d063e991f 100644
--- a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
+++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
@@ -3,6 +3,9 @@
* Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
*/
+#include <dt-bindings/clock/anlogic,dr1v90-cru.h>
+#include <dt-bindings/reset/anlogic,dr1v90-cru.h>
+
/dts-v1/;
/ {
#address-cells = <2>;
@@ -39,6 +42,27 @@ cpu0_intc: interrupt-controller {
};
};
+ clocks {
+ can_ext: clock-ext-can {
+ compatible = "fixed-clock";
+ clock-output-names = "can_ext";
+ #clock-cells = <0>;
+ };
+
+ osc_33m: clock-33m {
+ compatible = "fixed-clock";
+ clock-frequency = <33333333>;
+ clock-output-names = "osc_33m";
+ #clock-cells = <0>;
+ };
+
+ wdt_ext: clock-ext-wdt {
+ compatible = "fixed-clock";
+ clock-output-names = "wdt_ext";
+ #clock-cells = <0>;
+ };
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -80,21 +104,34 @@ plic: interrupt-controller@6c000000 {
uart0: serial@f8400000 {
compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
reg = <0x0 0xf8400000 0x0 0x1000>;
- clock-frequency = <50000000>;
+ clocks = <&cru CLK_IO_400M_DIV8>, <&cru CLK_CPU_1X>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <71>;
reg-io-width = <4>;
reg-shift = <2>;
+ resets = <&cru RESET_UART0>;
status = "disabled";
};
uart1: serial@f8401000 {
compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
reg = <0x0 0xf8401000 0x0 0x1000>;
- clock-frequency = <50000000>;
+ clocks = <&cru CLK_IO_400M_DIV8>, <&cru CLK_CPU_1X>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <72>;
reg-io-width = <4>;
reg-shift = <2>;
+ resets = <&cru RESET_UART1>;
status = "disabled";
};
+
+ cru: clock-controller@f8801000 {
+ compatible = "anlogic,dr1v90-cru";
+ reg = <0x0 0xf8801000 0 0x400>;
+ clocks = <&osc_33m>, <&can_ext>, <&wdt_ext>;
+ clock-names = "osc_33m", "can_ext", "wdt_ext";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
};
};
--
2.52.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2025-12-21 14:36 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-12-21 14:35 [PATCH v3 5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90 kernel test robot
-- strict thread matches above, loose matches on Subject: below --
2025-12-16 3:39 [PATCH v3 0/6] clk/reset: anlogic: add support for DR1V90 SoC Junhui Liu
2025-12-16 3:39 ` [PATCH v3 5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90 Junhui Liu
2025-12-16 3:39 ` Junhui Liu
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.