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From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Weiwei Li <liwei1518@gmail.com>,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
	bin.meng@windriver.com, vivahavey@gmail.com,
	Alvin Chang <alvinga@andestech.com>,
	Yu-Ming Chang <yumin686@andestech.com>,
	Joel Stanley <joel@jms.id.au>
Subject: [RFC PATCH 11/25] target/riscv/debug: Fix breakpoint matching action
Date: Wed, 14 Jan 2026 14:46:44 +1000	[thread overview]
Message-ID: <20260114044701.1173347-12-npiggin@gmail.com> (raw)
In-Reply-To: <20260114044701.1173347-1-npiggin@gmail.com>

The debug exception callback is too late to find the action for the
trigger(s) which caused it, and it is actually passing the wrong thing
to do_trigger_action(), which expects a trigger index but is given
DBG_ACTION_BP (which will be interpreted as trigger 0 and use the
action set for that trigger).

It could be possible to derive the trigger index from the bp/wp address,
but that is clunky and it is really the action that determines whether
an exception should be raised, also multiple triggers may perform their
actions in the same cycle, so it is more consistent to check action
during the breakpoint matching phase. If a breakpoint exception is to be
taken then that is signaled at that time.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 target/riscv/debug.c | 35 +++++++++++++++++++++++------------
 1 file changed, 23 insertions(+), 12 deletions(-)

diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 7ae02fe2d2..bd61b7ff02 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -280,7 +280,8 @@ static target_ulong textra_validate(CPURISCVState *env, target_ulong tdata3)
     return textra;
 }
 
-static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index)
+/* Return true if an exception should be raised */
+static bool do_trigger_action(CPURISCVState *env, target_ulong trigger_index)
 {
     trigger_action_t action = get_trigger_action(env, trigger_index);
 
@@ -288,8 +289,7 @@ static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index)
     case DBG_ACTION_NONE:
         break;
     case DBG_ACTION_BP:
-        riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
-        break;
+        return true;
     case DBG_ACTION_DBG_MODE:
     case DBG_ACTION_TRACE0:
     case DBG_ACTION_TRACE1:
@@ -302,6 +302,7 @@ static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index)
     default:
         g_assert_not_reached();
     }
+    return false;
 }
 
 /*
@@ -718,7 +719,9 @@ void helper_itrigger_match(CPURISCVState *env)
         }
         itrigger_set_count(env, i, count--);
         if (!count) {
-            do_trigger_action(env, i);
+            if (do_trigger_action(env, i)) {
+                riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
+            }
         } else {
             enabled = true;
         }
@@ -965,11 +968,11 @@ void riscv_cpu_debug_excp_handler(CPUState *cs)
 
     if (cs->watchpoint_hit) {
         if (cs->watchpoint_hit->flags & BP_CPU) {
-            do_trigger_action(env, DBG_ACTION_BP);
+            riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
         }
     } else {
         if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) {
-            do_trigger_action(env, DBG_ACTION_BP);
+            riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
         }
     }
 }
@@ -1006,8 +1009,10 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                 pc = env->tdata2[i];
 
                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
-                    env->badaddr = pc;
-                    return true;
+                    if (do_trigger_action(env, i)) {
+                        env->badaddr = pc;
+                        return true;
+                    }
                 }
                 break;
             case TRIGGER_TYPE_AD_MATCH6:
@@ -1015,8 +1020,10 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                 pc = env->tdata2[i];
 
                 if ((ctrl & TYPE6_EXEC) && (bp->pc == pc)) {
-                    env->badaddr = pc;
-                    return true;
+                    if (do_trigger_action(env, i)) {
+                        env->badaddr = pc;
+                        return true;
+                    }
                 }
                 break;
             default:
@@ -1067,7 +1074,9 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
             }
 
             if ((wp->flags & flags) && (wp->vaddr == addr)) {
-                return true;
+                if (do_trigger_action(env, i)) {
+                    return true;
+                }
             }
             break;
         case TRIGGER_TYPE_AD_MATCH6:
@@ -1083,7 +1092,9 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
             }
 
             if ((wp->flags & flags) && (wp->vaddr == addr)) {
-                return true;
+                if (do_trigger_action(env, i)) {
+                    return true;
+                }
             }
             break;
         default:
-- 
2.51.0



  parent reply	other threads:[~2026-01-14  4:51 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-14  4:46 [RFC PATCH 00/25] target/riscv/debug: Sdtrig fixes and TT Ascalon support Nicholas Piggin
2026-01-14  4:46 ` [RFC PATCH 01/25] target/riscv/debug: Check only mcontrol triggers for break/watchpoint matching Nicholas Piggin
2026-06-04  9:55   ` Daniel Henrique Barboza
2026-06-08  2:57   ` Chao Liu
2026-01-14  4:46 ` [RFC PATCH 02/25] target/riscv/debug: Handle changing trigger types Nicholas Piggin
2026-07-06  6:13   ` Chao Liu
2026-01-14  4:46 ` [RFC PATCH 03/25] target/riscv/debug: Implement permissive type unavailable trigger Nicholas Piggin
2026-06-04 10:10   ` Daniel Henrique Barboza
2026-07-06  6:13   ` Chao Liu
2026-01-14  4:46 ` [RFC PATCH 04/25] target/riscv/debug: Fix icount trigger privilege check Nicholas Piggin
2026-06-04 10:12   ` Daniel Henrique Barboza
2026-07-06  5:00   ` Chao Liu
2026-01-14  4:46 ` [RFC PATCH 05/25] target/riscv/debug: Update itrigger_enabled after changing privilege Nicholas Piggin
2026-06-04 10:29   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 06/25] target/riscv/debug: Implement get_trigger_action for icount type trigger Nicholas Piggin
2026-06-04 10:29   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 07/25] target/riscv/debug: Fix migration post_load icount_enabled() test Nicholas Piggin
2026-06-04 10:30   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 08/25] target/riscv/debug: Fix icount privilege matching " Nicholas Piggin
2026-06-04 10:30   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 09/25] target/riscv/debug: Implement icount trigger textra matching Nicholas Piggin
2026-06-04 10:31   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 10/25] target/riscv/debug: Maintain itrigger_enabled in helper_itrigger_match() Nicholas Piggin
2026-06-04 10:32   ` Daniel Henrique Barboza
2026-01-14  4:46 ` Nicholas Piggin [this message]
2026-06-04 11:35   ` [RFC PATCH 11/25] target/riscv/debug: Fix breakpoint matching action Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 12/25] target/riscv/debug: Put mcontrol load/store match address into tval Nicholas Piggin
2026-06-04 11:38   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 13/25] target/riscv/debug: Remove breakpoints on reset Nicholas Piggin
2026-06-04 11:38   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 14/25] target/riscv/debug: Move debug CPU post_load details into debug.c Nicholas Piggin
2026-06-04 12:52   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 15/25] target/riscv/debug: Insert breakpoints after migration Nicholas Piggin
2026-06-04 12:53   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 16/25] target/riscv/debug: Remove itrigger icount-enabled mode Nicholas Piggin
2026-01-14  4:46 ` [RFC PATCH 17/25] target/riscv/debug: Advertise icount trigger type in tinfo Nicholas Piggin
2026-06-04 12:55   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 18/25] target/riscv/debug: Reset trigger type to unavailable Nicholas Piggin
2026-06-04 12:56   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 19/25] target/riscv/debug: Add new debug state format Nicholas Piggin
2026-01-14  4:46 ` [RFC PATCH 20/25] target/riscv/debug: Migrate mcontext using new sdtrig vmstate Nicholas Piggin
2026-01-14  4:46 ` [RFC PATCH 21/25] target/riscv/debug: Implementation specific Sdtrig configuration Nicholas Piggin
2026-01-14  4:46 ` [RFC PATCH 22/25] target/riscv/debug: Support heterogeneous trigger types Nicholas Piggin
2026-01-14  4:46 ` [RFC PATCH 23/25] target/riscv/debug: Support heterogeneous mcontrol access types Nicholas Piggin
2026-01-14  4:46 ` [RFC PATCH 24/25] target/riscv/debug: Emulate TT Ascalon Sdtrig Nicholas Piggin
2026-01-14  4:46 ` [RFC PATCH 25/25] target/riscv/debug: Fix minor comment typos Nicholas Piggin
2026-06-04 10:32   ` Daniel Henrique Barboza
2026-06-04 13:12 ` [RFC PATCH 00/25] target/riscv/debug: Sdtrig fixes and TT Ascalon support Daniel Henrique Barboza
2026-07-03 21:36 ` Daniel Henrique Barboza
2026-07-04  3:22   ` Chao Liu

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