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From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Weiwei Li <liwei1518@gmail.com>,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
	bin.meng@windriver.com, vivahavey@gmail.com,
	Alvin Chang <alvinga@andestech.com>,
	Yu-Ming Chang <yumin686@andestech.com>,
	Joel Stanley <joel@jms.id.au>
Subject: [RFC PATCH 04/25] target/riscv/debug: Fix icount trigger privilege check
Date: Wed, 14 Jan 2026 14:46:37 +1000	[thread overview]
Message-ID: <20260114044701.1173347-5-npiggin@gmail.com> (raw)
In-Reply-To: <20260114044701.1173347-1-npiggin@gmail.com>

The check_itrigger_priv() did not check privilege bits properly. Move
all priv checks into functions and have the icount check follow the same
form as the others.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 target/riscv/debug.c | 82 ++++++++++++++++++++------------------------
 1 file changed, 37 insertions(+), 45 deletions(-)

diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index c92bd9860e..2effbb49af 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -306,48 +306,50 @@ static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index)
  * Check the privilege level of specific trigger matches CPU's current privilege
  * level.
  */
+static bool type2_priv_match(CPURISCVState *env, target_ulong tdata1)
+{
+    /* type 2 trigger cannot be fired in VU/VS mode */
+    if (env->virt_enabled) {
+        return false;
+    }
+    /* check U/S/M bit against current privilege level */
+    return (((tdata1 >> 3) & 0b1011) & BIT(env->priv));
+}
+
+static bool type6_priv_match(CPURISCVState *env, target_ulong tdata1)
+{
+    if (env->virt_enabled) {
+        /* check VU/VS bit against current privilege level */
+        return (((tdata1 >> 23) & 0b11) & BIT(env->priv));
+    } else {
+        /* check U/S/M bit against current privilege level */
+        return (((tdata1 >> 3) & 0b1011) & BIT(env->priv));
+    }
+}
+
+static bool icount_priv_match(CPURISCVState *env, target_ulong tdata1)
+{
+    if (env->virt_enabled) {
+        /* check VU/VS bit against current privilege level */
+        return (((tdata1 >> 25) & 0b11) & BIT(env->priv));
+    } else {
+        /* check U/S/M bit against current privilege level */
+        return (((tdata1 >> 6) & 0b1011) & BIT(env->priv));
+    }
+}
+
 static bool trigger_priv_match(CPURISCVState *env, trigger_type_t type,
                                int trigger_index)
 {
-    target_ulong ctrl = env->tdata1[trigger_index];
+    target_ulong tdata1 = env->tdata1[trigger_index];
 
     switch (type) {
     case TRIGGER_TYPE_AD_MATCH:
-        /* type 2 trigger cannot be fired in VU/VS mode */
-        if (env->virt_enabled) {
-            return false;
-        }
-        /* check U/S/M bit against current privilege level */
-        if ((ctrl >> 3) & BIT(env->priv)) {
-            return true;
-        }
-        break;
+        return type2_priv_match(env, tdata1);
     case TRIGGER_TYPE_AD_MATCH6:
-        if (env->virt_enabled) {
-            /* check VU/VS bit against current privilege level */
-            if ((ctrl >> 23) & BIT(env->priv)) {
-                return true;
-            }
-        } else {
-            /* check U/S/M bit against current privilege level */
-            if ((ctrl >> 3) & BIT(env->priv)) {
-                return true;
-            }
-        }
-        break;
+        return type6_priv_match(env, tdata1);
     case TRIGGER_TYPE_INST_CNT:
-        if (env->virt_enabled) {
-            /* check VU/VS bit against current privilege level */
-            if ((ctrl >> 25) & BIT(env->priv)) {
-                return true;
-            }
-        } else {
-            /* check U/S/M bit against current privilege level */
-            if ((ctrl >> 6) & BIT(env->priv)) {
-                return true;
-            }
-        }
-        break;
+        return icount_priv_match(env, tdata1);
     case TRIGGER_TYPE_INT:
     case TRIGGER_TYPE_EXCP:
     case TRIGGER_TYPE_EXT_SRC:
@@ -665,17 +667,7 @@ itrigger_set_count(CPURISCVState *env, int index, int value)
 
 static bool check_itrigger_priv(CPURISCVState *env, int index)
 {
-    target_ulong tdata1 = env->tdata1[index];
-    if (env->virt_enabled) {
-        /* check VU/VS bit against current privilege level */
-        return (get_field(tdata1, ITRIGGER_VS) == env->priv) ||
-               (get_field(tdata1, ITRIGGER_VU) == env->priv);
-    } else {
-        /* check U/S/M bit against current privilege level */
-        return (get_field(tdata1, ITRIGGER_M) == env->priv) ||
-               (get_field(tdata1, ITRIGGER_S) == env->priv) ||
-               (get_field(tdata1, ITRIGGER_U) == env->priv);
-    }
+    return icount_priv_match(env, index);
 }
 
 bool riscv_itrigger_enabled(CPURISCVState *env)
-- 
2.51.0



  parent reply	other threads:[~2026-01-14  4:54 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-14  4:46 [RFC PATCH 00/25] target/riscv/debug: Sdtrig fixes and TT Ascalon support Nicholas Piggin
2026-01-14  4:46 ` [RFC PATCH 01/25] target/riscv/debug: Check only mcontrol triggers for break/watchpoint matching Nicholas Piggin
2026-06-04  9:55   ` Daniel Henrique Barboza
2026-06-08  2:57   ` Chao Liu
2026-01-14  4:46 ` [RFC PATCH 02/25] target/riscv/debug: Handle changing trigger types Nicholas Piggin
2026-07-06  6:13   ` Chao Liu
2026-01-14  4:46 ` [RFC PATCH 03/25] target/riscv/debug: Implement permissive type unavailable trigger Nicholas Piggin
2026-06-04 10:10   ` Daniel Henrique Barboza
2026-07-06  6:13   ` Chao Liu
2026-01-14  4:46 ` Nicholas Piggin [this message]
2026-06-04 10:12   ` [RFC PATCH 04/25] target/riscv/debug: Fix icount trigger privilege check Daniel Henrique Barboza
2026-07-06  5:00   ` Chao Liu
2026-01-14  4:46 ` [RFC PATCH 05/25] target/riscv/debug: Update itrigger_enabled after changing privilege Nicholas Piggin
2026-06-04 10:29   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 06/25] target/riscv/debug: Implement get_trigger_action for icount type trigger Nicholas Piggin
2026-06-04 10:29   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 07/25] target/riscv/debug: Fix migration post_load icount_enabled() test Nicholas Piggin
2026-06-04 10:30   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 08/25] target/riscv/debug: Fix icount privilege matching " Nicholas Piggin
2026-06-04 10:30   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 09/25] target/riscv/debug: Implement icount trigger textra matching Nicholas Piggin
2026-06-04 10:31   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 10/25] target/riscv/debug: Maintain itrigger_enabled in helper_itrigger_match() Nicholas Piggin
2026-06-04 10:32   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 11/25] target/riscv/debug: Fix breakpoint matching action Nicholas Piggin
2026-06-04 11:35   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 12/25] target/riscv/debug: Put mcontrol load/store match address into tval Nicholas Piggin
2026-06-04 11:38   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 13/25] target/riscv/debug: Remove breakpoints on reset Nicholas Piggin
2026-06-04 11:38   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 14/25] target/riscv/debug: Move debug CPU post_load details into debug.c Nicholas Piggin
2026-06-04 12:52   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 15/25] target/riscv/debug: Insert breakpoints after migration Nicholas Piggin
2026-06-04 12:53   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 16/25] target/riscv/debug: Remove itrigger icount-enabled mode Nicholas Piggin
2026-01-14  4:46 ` [RFC PATCH 17/25] target/riscv/debug: Advertise icount trigger type in tinfo Nicholas Piggin
2026-06-04 12:55   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 18/25] target/riscv/debug: Reset trigger type to unavailable Nicholas Piggin
2026-06-04 12:56   ` Daniel Henrique Barboza
2026-01-14  4:46 ` [RFC PATCH 19/25] target/riscv/debug: Add new debug state format Nicholas Piggin
2026-01-14  4:46 ` [RFC PATCH 20/25] target/riscv/debug: Migrate mcontext using new sdtrig vmstate Nicholas Piggin
2026-01-14  4:46 ` [RFC PATCH 21/25] target/riscv/debug: Implementation specific Sdtrig configuration Nicholas Piggin
2026-01-14  4:46 ` [RFC PATCH 22/25] target/riscv/debug: Support heterogeneous trigger types Nicholas Piggin
2026-01-14  4:46 ` [RFC PATCH 23/25] target/riscv/debug: Support heterogeneous mcontrol access types Nicholas Piggin
2026-01-14  4:46 ` [RFC PATCH 24/25] target/riscv/debug: Emulate TT Ascalon Sdtrig Nicholas Piggin
2026-01-14  4:46 ` [RFC PATCH 25/25] target/riscv/debug: Fix minor comment typos Nicholas Piggin
2026-06-04 10:32   ` Daniel Henrique Barboza
2026-06-04 13:12 ` [RFC PATCH 00/25] target/riscv/debug: Sdtrig fixes and TT Ascalon support Daniel Henrique Barboza
2026-07-03 21:36 ` Daniel Henrique Barboza
2026-07-04  3:22   ` Chao Liu

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