[PATCH] cxl/core: Fix cxl_dport debugfs EINJ entries

[PATCH] cxl/core: Fix cxl_dport debugfs EINJ entries

[Cheatham, Benjamin]

Protocol error injection is only valid for CXL 2.0+ root ports and CXL
1.1 memory-mapped downstream ports as per the ACPI v6.5 spec (Table
8-31). The core code currently creates an 'einj_inject' file in CXL debugfs
for all CXL 1.1 downstream ports and all PCI CXL 2.0+ downstream ports.
This results in debugfs EINJ files that won't work due to platform/spec
restrictions.

Fix by limiting 'einj_inject' file creation to only CXL 1.1 dports and
CXL 2.0+ root ports. Update the comment above the check to more accurately
represent the requirements expected by the EINJ module and ACPI spec.

Fixes: 8039804cfa73 ("cxl/core: Add CXL EINJ debugfs files")
Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 drivers/cxl/core/port.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index fef3aa0c6680..54f72452fb06 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -822,16 +822,18 @@ DEFINE_DEBUGFS_ATTRIBUTE(cxl_einj_inject_fops, NULL, cxl_einj_inject,
 
 static void cxl_debugfs_create_dport_dir(struct cxl_dport *dport)
 {
+	struct cxl_port *parent = parent_port_of(dport->port);
 	struct dentry *dir;
 
 	if (!einj_cxl_is_initialized())
 		return;
 
 	/*
-	 * dport_dev needs to be a PCIe port for CXL 2.0+ ports because
-	 * EINJ expects a dport SBDF to be specified for 2.0 error injection.
+	 * Protocol error injection is only available for CXL 2.0+ root ports
+	 * and CXL 1.1 downstream ports
 	 */
-	if (!dport->rch && !dev_is_pci(dport->dport_dev))
+	if (!dport->rch &&
+	    !(dev_is_pci(dport->dport_dev) && parent && is_cxl_root(parent)))
 		return;
 
 	dir = cxl_debugfs_create_dir(dev_name(dport->dport_dev));
-- 
2.52.0

Re: [PATCH] cxl/core: Fix cxl_dport debugfs EINJ entries

[Dave Jiang]

On 1/9/26 6:57 AM, Cheatham, Benjamin wrote:
> Protocol error injection is only valid for CXL 2.0+ root ports and CXL
> 1.1 memory-mapped downstream ports as per the ACPI v6.5 spec (Table
> 8-31). The core code currently creates an 'einj_inject' file in CXL debugfs
> for all CXL 1.1 downstream ports and all PCI CXL 2.0+ downstream ports.
> This results in debugfs EINJ files that won't work due to platform/spec
> restrictions.
> 
> Fix by limiting 'einj_inject' file creation to only CXL 1.1 dports and
> CXL 2.0+ root ports. Update the comment above the check to more accurately
> represent the requirements expected by the EINJ module and ACPI spec.
> 
> Fixes: 8039804cfa73 ("cxl/core: Add CXL EINJ debugfs files")
> Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>

Reviewed-by: Dave Jiang <dave.jiang@intel.com>


> ---
>  drivers/cxl/core/port.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index fef3aa0c6680..54f72452fb06 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -822,16 +822,18 @@ DEFINE_DEBUGFS_ATTRIBUTE(cxl_einj_inject_fops, NULL, cxl_einj_inject,
>  
>  static void cxl_debugfs_create_dport_dir(struct cxl_dport *dport)
>  {
> +	struct cxl_port *parent = parent_port_of(dport->port);
>  	struct dentry *dir;
>  
>  	if (!einj_cxl_is_initialized())
>  		return;
>  
>  	/*
> -	 * dport_dev needs to be a PCIe port for CXL 2.0+ ports because
> -	 * EINJ expects a dport SBDF to be specified for 2.0 error injection.
> +	 * Protocol error injection is only available for CXL 2.0+ root ports
> +	 * and CXL 1.1 downstream ports
>  	 */
> -	if (!dport->rch && !dev_is_pci(dport->dport_dev))
> +	if (!dport->rch &&
> +	    !(dev_is_pci(dport->dport_dev) && parent && is_cxl_root(parent)))
>  		return;
>  
>  	dir = cxl_debugfs_create_dir(dev_name(dport->dport_dev));

Re: [PATCH] cxl/core: Fix cxl_dport debugfs EINJ entries

[Alison Schofield]

On Fri, Jan 09, 2026 at 07:57:38AM -0600, Cheatham, Benjamin wrote:
> Protocol error injection is only valid for CXL 2.0+ root ports and CXL
> 1.1 memory-mapped downstream ports as per the ACPI v6.5 spec (Table
> 8-31). The core code currently creates an 'einj_inject' file in CXL debugfs
> for all CXL 1.1 downstream ports and all PCI CXL 2.0+ downstream ports.
> This results in debugfs EINJ files that won't work due to platform/spec
> restrictions.
> 
> Fix by limiting 'einj_inject' file creation to only CXL 1.1 dports and
> CXL 2.0+ root ports. Update the comment above the check to more accurately
> represent the requirements expected by the EINJ module and ACPI spec.
> 
> Fixes: 8039804cfa73 ("cxl/core: Add CXL EINJ debugfs files")
> Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>

Reviewed-by: Alison Schofield <alison.schofield@intel.com>

Re: [PATCH] cxl/core: Fix cxl_dport debugfs EINJ entries

[Jonathan Cameron]

On Fri, 9 Jan 2026 07:57:38 -0600
"Cheatham, Benjamin" <benjamin.cheatham@amd.com> wrote:

> Protocol error injection is only valid for CXL 2.0+ root ports and CXL
> 1.1 memory-mapped downstream ports as per the ACPI v6.5 spec (Table
> 8-31). The core code currently creates an 'einj_inject' file in CXL debugfs
> for all CXL 1.1 downstream ports and all PCI CXL 2.0+ downstream ports.
> This results in debugfs EINJ files that won't work due to platform/spec
> restrictions.
> 
> Fix by limiting 'einj_inject' file creation to only CXL 1.1 dports and
> CXL 2.0+ root ports. Update the comment above the check to more accurately
> represent the requirements expected by the EINJ module and ACPI spec.
> 
> Fixes: 8039804cfa73 ("cxl/core: Add CXL EINJ debugfs files")
> Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>

Re: [PATCH] cxl/core: Fix cxl_dport debugfs EINJ entries

[Dave Jiang]

On 1/9/26 6:57 AM, Cheatham, Benjamin wrote:
> Protocol error injection is only valid for CXL 2.0+ root ports and CXL
> 1.1 memory-mapped downstream ports as per the ACPI v6.5 spec (Table
> 8-31). The core code currently creates an 'einj_inject' file in CXL debugfs
> for all CXL 1.1 downstream ports and all PCI CXL 2.0+ downstream ports.
> This results in debugfs EINJ files that won't work due to platform/spec
> restrictions.
> 
> Fix by limiting 'einj_inject' file creation to only CXL 1.1 dports and
> CXL 2.0+ root ports. Update the comment above the check to more accurately
> represent the requirements expected by the EINJ module and ACPI spec.
> 
> Fixes: 8039804cfa73 ("cxl/core: Add CXL EINJ debugfs files")
> Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>

Applied to cxl/next
5c604e7a9f6c215a7942671f62b76461678960b1


> ---
>  drivers/cxl/core/port.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index fef3aa0c6680..54f72452fb06 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -822,16 +822,18 @@ DEFINE_DEBUGFS_ATTRIBUTE(cxl_einj_inject_fops, NULL, cxl_einj_inject,
>  
>  static void cxl_debugfs_create_dport_dir(struct cxl_dport *dport)
>  {
> +	struct cxl_port *parent = parent_port_of(dport->port);
>  	struct dentry *dir;
>  
>  	if (!einj_cxl_is_initialized())
>  		return;
>  
>  	/*
> -	 * dport_dev needs to be a PCIe port for CXL 2.0+ ports because
> -	 * EINJ expects a dport SBDF to be specified for 2.0 error injection.
> +	 * Protocol error injection is only available for CXL 2.0+ root ports
> +	 * and CXL 1.1 downstream ports
>  	 */
> -	if (!dport->rch && !dev_is_pci(dport->dport_dev))
> +	if (!dport->rch &&
> +	    !(dev_is_pci(dport->dport_dev) && parent && is_cxl_root(parent)))
>  		return;
>  
>  	dir = cxl_debugfs_create_dir(dev_name(dport->dport_dev));