* [PATCH v1 0/7] Update functional tests for AST2500/AST2600/AST103/AST1060
@ 2026-01-27 3:23 ` Jamin Lin via qemu development
0 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-27 3:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="UTF-8", Size: 1402 bytes --]
v1:
- Remove AST2600 PCIe root device and RC_L support
- Drop RC_H root-bus remap and bus number properties
- Expand AST2600 RC_H PCIe MMIO window to 0x60000000¡V0x80000000
- Update functional tests for AST2500, AST2600, AST1060, and AST1030
- AST2500 tests are updated to use SDK v10.00, as network support is known
to be broken in v11.00.
Jamin Lin (7):
tests/functional/arm/test_aspeed_ast2500: Update test ASPEED SDK
v10.00
hw/pci-host/aspeed_pcie: Drop AST2600 PCIe root device
hw/pci-host/aspeed_pcie: Drop AST2600 RC_H root-bus remap and bus-nr
property
hw/arm/aspeed_ast2600: Expand RC_H PCIe MMIO window to 0x60000000 -
0x80000000
tests/functional/arm/test_aspeed_ast2600_sdk: Update test ASPEED SDK
v11.00
tests/functional/arm/test_aspeed_ast1060: Update test
aspeed-zephyr-project v03.04
tests/functional/arm/test_aspeed_ast1030: Update test ASPEED Zephyr
SDK v03.05
include/hw/pci-host/aspeed_pcie.h | 11 ---
hw/arm/aspeed_ast2600.c | 8 +-
hw/pci-host/aspeed_pcie.c | 76 +------------------
tests/functional/arm/test_aspeed_ast1030.py | 12 +--
tests/functional/arm/test_aspeed_ast1060.py | 14 ++--
tests/functional/arm/test_aspeed_ast2500.py | 8 +-
.../functional/arm/test_aspeed_ast2600_sdk.py | 22 +++---
7 files changed, 31 insertions(+), 120 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v1 1/7] tests/functional/arm/test_aspeed_ast2500: Update test ASPEED SDK v10.00
2026-01-27 3:23 ` Jamin Lin via qemu development
@ 2026-01-27 3:23 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via @ 2026-01-27 3:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
tests/functional/arm/test_aspeed_ast2500.py | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tests/functional/arm/test_aspeed_ast2500.py b/tests/functional/arm/test_aspeed_ast2500.py
index 5efd104c2b..d8baed6fdb 100755
--- a/tests/functional/arm/test_aspeed_ast2500.py
+++ b/tests/functional/arm/test_aspeed_ast2500.py
@@ -37,14 +37,14 @@ def test_arm_ast2500_evb_buildroot(self):
self.do_test_arm_aspeed_buildroot_poweroff()
- ASSET_SDK_V908_AST2500 = Asset(
- 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.08/ast2500-default-obmc.tar.gz',
- 'c0a2ba169efd19be5eb77c50ec2a6afd9d826e196a0be3432f969fc72d4b7c0e')
+ ASSET_SDK_V1000_AST2500 = Asset(
+ 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v10.00/ast2500-default-obmc.tar.gz',
+ '7d71a3f71d5f4d9f3451f59a73bf9baf8fd9f6a24107eb504a3216151a8b2b5b')
def test_arm_ast2500_evb_sdk(self):
self.set_machine('ast2500-evb')
- self.archive_extract(self.ASSET_SDK_V908_AST2500)
+ self.archive_extract(self.ASSET_SDK_V1000_AST2500)
self.do_test_arm_aspeed_sdk_start(
self.scratch_file("ast2500-default", "image-bmc"))
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v1 1/7] tests/functional/arm/test_aspeed_ast2500: Update test ASPEED SDK v10.00
@ 2026-01-27 3:23 ` Jamin Lin via qemu development
0 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-27 3:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
tests/functional/arm/test_aspeed_ast2500.py | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tests/functional/arm/test_aspeed_ast2500.py b/tests/functional/arm/test_aspeed_ast2500.py
index 5efd104c2b..d8baed6fdb 100755
--- a/tests/functional/arm/test_aspeed_ast2500.py
+++ b/tests/functional/arm/test_aspeed_ast2500.py
@@ -37,14 +37,14 @@ def test_arm_ast2500_evb_buildroot(self):
self.do_test_arm_aspeed_buildroot_poweroff()
- ASSET_SDK_V908_AST2500 = Asset(
- 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.08/ast2500-default-obmc.tar.gz',
- 'c0a2ba169efd19be5eb77c50ec2a6afd9d826e196a0be3432f969fc72d4b7c0e')
+ ASSET_SDK_V1000_AST2500 = Asset(
+ 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v10.00/ast2500-default-obmc.tar.gz',
+ '7d71a3f71d5f4d9f3451f59a73bf9baf8fd9f6a24107eb504a3216151a8b2b5b')
def test_arm_ast2500_evb_sdk(self):
self.set_machine('ast2500-evb')
- self.archive_extract(self.ASSET_SDK_V908_AST2500)
+ self.archive_extract(self.ASSET_SDK_V1000_AST2500)
self.do_test_arm_aspeed_sdk_start(
self.scratch_file("ast2500-default", "image-bmc"))
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v1 2/7] hw/pci-host/aspeed_pcie: Drop AST2600 PCIe root device
2026-01-27 3:23 ` Jamin Lin via qemu development
@ 2026-01-27 3:23 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via @ 2026-01-27 3:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
AST2600 PCIe previously exposed a root bus at 0x80 with both a
root device at 80:00.0 and a root port at 80:08.0.
Recent ASPEED SDK PCIe driver updates decided to remove the root
device and keep only a single root port. This behavior has already
been accepted by the upstream Linux kernel.
Update the QEMU PCIe model accordingly by dropping the root device
implementation and related properties. AST2600 now matches the
AST2700 PCIe topology and no longer supports the legacy RC_L
layout.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/pci-host/aspeed_pcie.h | 9 -----
hw/pci-host/aspeed_pcie.c | 57 -------------------------------
2 files changed, 66 deletions(-)
diff --git a/include/hw/pci-host/aspeed_pcie.h b/include/hw/pci-host/aspeed_pcie.h
index e660119a45..fde5816ea3 100644
--- a/include/hw/pci-host/aspeed_pcie.h
+++ b/include/hw/pci-host/aspeed_pcie.h
@@ -50,13 +50,6 @@ typedef struct AspeedPCIERootPortState {
PCIESlot parent_obj;
} AspeedPCIERootPortState;
-#define TYPE_ASPEED_PCIE_ROOT_DEVICE "aspeed.pcie-root-device"
-OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERootDeviceState, ASPEED_PCIE_ROOT_DEVICE);
-
-struct AspeedPCIERootDeviceState {
- PCIBridge parent_obj;
-};
-
#define TYPE_ASPEED_PCIE_RC "aspeed.pcie-rc"
OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERcState, ASPEED_PCIE_RC);
@@ -78,10 +71,8 @@ struct AspeedPCIERcState {
uint32_t rp_addr;
uint32_t bus_nr;
char name[16];
- bool has_rd;
qemu_irq irq;
- AspeedPCIERootDeviceState root_device;
AspeedPCIERootPortState root_port;
};
diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c
index 83a1c7075c..4fdda95939 100644
--- a/hw/pci-host/aspeed_pcie.c
+++ b/hw/pci-host/aspeed_pcie.c
@@ -26,44 +26,6 @@
#include "hw/pci/msi.h"
#include "trace.h"
-/*
- * PCIe Root Device
- * This device exists only on AST2600.
- */
-
-static void aspeed_pcie_root_device_class_init(ObjectClass *klass,
- const void *data)
-{
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- DeviceClass *dc = DEVICE_CLASS(klass);
-
- set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
- dc->desc = "ASPEED PCIe Root Device";
- k->vendor_id = PCI_VENDOR_ID_ASPEED;
- k->device_id = 0x2600;
- k->class_id = PCI_CLASS_BRIDGE_HOST;
- k->subsystem_vendor_id = k->vendor_id;
- k->subsystem_id = k->device_id;
- k->revision = 0;
-
- /*
- * PCI-facing part of the host bridge,
- * not usable without the host-facing part
- */
- dc->user_creatable = false;
-}
-
-static const TypeInfo aspeed_pcie_root_device_info = {
- .name = TYPE_ASPEED_PCIE_ROOT_DEVICE,
- .parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(AspeedPCIERootDeviceState),
- .class_init = aspeed_pcie_root_device_class_init,
- .interfaces = (const InterfaceInfo[]) {
- { INTERFACE_CONVENTIONAL_PCI_DEVICE },
- { },
- },
-};
-
/*
* PCIe Root Port
*/
@@ -291,18 +253,6 @@ static void aspeed_pcie_rc_realize(DeviceState *dev, Error **errp)
&rc->dram_alias);
pci_setup_iommu(pci->bus, &aspeed_pcie_rc_iommu_ops, rc);
- /* setup root device */
- if (rc->has_rd) {
- object_initialize_child(OBJECT(rc), "root_device", &rc->root_device,
- TYPE_ASPEED_PCIE_ROOT_DEVICE);
- qdev_prop_set_int32(DEVICE(&rc->root_device), "addr",
- PCI_DEVFN(0, 0));
- qdev_prop_set_bit(DEVICE(&rc->root_device), "multifunction", false);
- if (!qdev_realize(DEVICE(&rc->root_device), BUS(pci->bus), errp)) {
- return;
- }
- }
-
/* setup root port */
qdev_prop_set_int32(DEVICE(&rc->root_port), "addr", rc->rp_addr);
qdev_prop_set_uint16(DEVICE(&rc->root_port), "chassis", cfg->id);
@@ -334,7 +284,6 @@ static void aspeed_pcie_rc_instance_init(Object *obj)
static const Property aspeed_pcie_rc_props[] = {
DEFINE_PROP_UINT32("bus-nr", AspeedPCIERcState, bus_nr, 0),
- DEFINE_PROP_BOOL("has-rd", AspeedPCIERcState, has_rd, 0),
DEFINE_PROP_UINT32("rp-addr", AspeedPCIERcState, rp_addr, 0),
DEFINE_PROP_UINT32("msi-addr", AspeedPCIERcState, msi_addr, 0),
DEFINE_PROP_UINT64("dram-base", AspeedPCIERcState, dram_base, 0),
@@ -704,9 +653,6 @@ static void aspeed_pcie_cfg_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(&s->rc), "bus-nr",
apc->rc_bus_nr,
&error_abort);
- object_property_set_bool(OBJECT(&s->rc), "has-rd",
- apc->rc_has_rd,
- &error_abort);
object_property_set_int(OBJECT(&s->rc), "rp-addr",
apc->rc_rp_addr,
&error_abort);
@@ -746,7 +692,6 @@ static void aspeed_pcie_cfg_class_init(ObjectClass *klass, const void *data)
apc->nr_regs = 0x100 >> 2;
apc->rc_msi_addr = 0x1e77005C;
apc->rc_bus_nr = 0x80;
- apc->rc_has_rd = true;
apc->rc_rp_addr = PCI_DEVFN(8, 0);
}
@@ -867,7 +812,6 @@ static void aspeed_2700_pcie_cfg_class_init(ObjectClass *klass,
apc->nr_regs = 0x100 >> 2;
apc->rc_msi_addr = 0x000000F0;
apc->rc_bus_nr = 0;
- apc->rc_has_rd = false;
apc->rc_rp_addr = PCI_DEVFN(0, 0);
}
@@ -1041,7 +985,6 @@ static const TypeInfo aspeed_2700_pcie_phy_info = {
static void aspeed_pcie_register_types(void)
{
type_register_static(&aspeed_pcie_rc_info);
- type_register_static(&aspeed_pcie_root_device_info);
type_register_static(&aspeed_pcie_root_port_info);
type_register_static(&aspeed_pcie_cfg_info);
type_register_static(&aspeed_2700_pcie_cfg_info);
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v1 2/7] hw/pci-host/aspeed_pcie: Drop AST2600 PCIe root device
@ 2026-01-27 3:23 ` Jamin Lin via qemu development
0 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-27 3:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
AST2600 PCIe previously exposed a root bus at 0x80 with both a
root device at 80:00.0 and a root port at 80:08.0.
Recent ASPEED SDK PCIe driver updates decided to remove the root
device and keep only a single root port. This behavior has already
been accepted by the upstream Linux kernel.
Update the QEMU PCIe model accordingly by dropping the root device
implementation and related properties. AST2600 now matches the
AST2700 PCIe topology and no longer supports the legacy RC_L
layout.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/pci-host/aspeed_pcie.h | 9 -----
hw/pci-host/aspeed_pcie.c | 57 -------------------------------
2 files changed, 66 deletions(-)
diff --git a/include/hw/pci-host/aspeed_pcie.h b/include/hw/pci-host/aspeed_pcie.h
index e660119a45..fde5816ea3 100644
--- a/include/hw/pci-host/aspeed_pcie.h
+++ b/include/hw/pci-host/aspeed_pcie.h
@@ -50,13 +50,6 @@ typedef struct AspeedPCIERootPortState {
PCIESlot parent_obj;
} AspeedPCIERootPortState;
-#define TYPE_ASPEED_PCIE_ROOT_DEVICE "aspeed.pcie-root-device"
-OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERootDeviceState, ASPEED_PCIE_ROOT_DEVICE);
-
-struct AspeedPCIERootDeviceState {
- PCIBridge parent_obj;
-};
-
#define TYPE_ASPEED_PCIE_RC "aspeed.pcie-rc"
OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERcState, ASPEED_PCIE_RC);
@@ -78,10 +71,8 @@ struct AspeedPCIERcState {
uint32_t rp_addr;
uint32_t bus_nr;
char name[16];
- bool has_rd;
qemu_irq irq;
- AspeedPCIERootDeviceState root_device;
AspeedPCIERootPortState root_port;
};
diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c
index 83a1c7075c..4fdda95939 100644
--- a/hw/pci-host/aspeed_pcie.c
+++ b/hw/pci-host/aspeed_pcie.c
@@ -26,44 +26,6 @@
#include "hw/pci/msi.h"
#include "trace.h"
-/*
- * PCIe Root Device
- * This device exists only on AST2600.
- */
-
-static void aspeed_pcie_root_device_class_init(ObjectClass *klass,
- const void *data)
-{
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- DeviceClass *dc = DEVICE_CLASS(klass);
-
- set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
- dc->desc = "ASPEED PCIe Root Device";
- k->vendor_id = PCI_VENDOR_ID_ASPEED;
- k->device_id = 0x2600;
- k->class_id = PCI_CLASS_BRIDGE_HOST;
- k->subsystem_vendor_id = k->vendor_id;
- k->subsystem_id = k->device_id;
- k->revision = 0;
-
- /*
- * PCI-facing part of the host bridge,
- * not usable without the host-facing part
- */
- dc->user_creatable = false;
-}
-
-static const TypeInfo aspeed_pcie_root_device_info = {
- .name = TYPE_ASPEED_PCIE_ROOT_DEVICE,
- .parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(AspeedPCIERootDeviceState),
- .class_init = aspeed_pcie_root_device_class_init,
- .interfaces = (const InterfaceInfo[]) {
- { INTERFACE_CONVENTIONAL_PCI_DEVICE },
- { },
- },
-};
-
/*
* PCIe Root Port
*/
@@ -291,18 +253,6 @@ static void aspeed_pcie_rc_realize(DeviceState *dev, Error **errp)
&rc->dram_alias);
pci_setup_iommu(pci->bus, &aspeed_pcie_rc_iommu_ops, rc);
- /* setup root device */
- if (rc->has_rd) {
- object_initialize_child(OBJECT(rc), "root_device", &rc->root_device,
- TYPE_ASPEED_PCIE_ROOT_DEVICE);
- qdev_prop_set_int32(DEVICE(&rc->root_device), "addr",
- PCI_DEVFN(0, 0));
- qdev_prop_set_bit(DEVICE(&rc->root_device), "multifunction", false);
- if (!qdev_realize(DEVICE(&rc->root_device), BUS(pci->bus), errp)) {
- return;
- }
- }
-
/* setup root port */
qdev_prop_set_int32(DEVICE(&rc->root_port), "addr", rc->rp_addr);
qdev_prop_set_uint16(DEVICE(&rc->root_port), "chassis", cfg->id);
@@ -334,7 +284,6 @@ static void aspeed_pcie_rc_instance_init(Object *obj)
static const Property aspeed_pcie_rc_props[] = {
DEFINE_PROP_UINT32("bus-nr", AspeedPCIERcState, bus_nr, 0),
- DEFINE_PROP_BOOL("has-rd", AspeedPCIERcState, has_rd, 0),
DEFINE_PROP_UINT32("rp-addr", AspeedPCIERcState, rp_addr, 0),
DEFINE_PROP_UINT32("msi-addr", AspeedPCIERcState, msi_addr, 0),
DEFINE_PROP_UINT64("dram-base", AspeedPCIERcState, dram_base, 0),
@@ -704,9 +653,6 @@ static void aspeed_pcie_cfg_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(&s->rc), "bus-nr",
apc->rc_bus_nr,
&error_abort);
- object_property_set_bool(OBJECT(&s->rc), "has-rd",
- apc->rc_has_rd,
- &error_abort);
object_property_set_int(OBJECT(&s->rc), "rp-addr",
apc->rc_rp_addr,
&error_abort);
@@ -746,7 +692,6 @@ static void aspeed_pcie_cfg_class_init(ObjectClass *klass, const void *data)
apc->nr_regs = 0x100 >> 2;
apc->rc_msi_addr = 0x1e77005C;
apc->rc_bus_nr = 0x80;
- apc->rc_has_rd = true;
apc->rc_rp_addr = PCI_DEVFN(8, 0);
}
@@ -867,7 +812,6 @@ static void aspeed_2700_pcie_cfg_class_init(ObjectClass *klass,
apc->nr_regs = 0x100 >> 2;
apc->rc_msi_addr = 0x000000F0;
apc->rc_bus_nr = 0;
- apc->rc_has_rd = false;
apc->rc_rp_addr = PCI_DEVFN(0, 0);
}
@@ -1041,7 +985,6 @@ static const TypeInfo aspeed_2700_pcie_phy_info = {
static void aspeed_pcie_register_types(void)
{
type_register_static(&aspeed_pcie_rc_info);
- type_register_static(&aspeed_pcie_root_device_info);
type_register_static(&aspeed_pcie_root_port_info);
type_register_static(&aspeed_pcie_cfg_info);
type_register_static(&aspeed_2700_pcie_cfg_info);
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v1 3/7] hw/pci-host/aspeed_pcie: Drop AST2600 RC_H root-bus remap and bus-nr property
2026-01-27 3:23 ` Jamin Lin via qemu development
@ 2026-01-27 3:23 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via @ 2026-01-27 3:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
The original AST2600 PCIe design supported both RC_L and RC_H, using root bus
number 0 for RC_L and 0x80 for RC_H. In that model, the root port appeared as
80:08.0 and QEMU carried a "bus-nr" property plus a config-space bus remap to
translate bus 0x80 to bus 0x00 for PCI enumeration.
Linux mainline has since dropped RC_L support and updated the RC_H root bus
number to start at 0. The root port is now enumerated as 00:08.0, matching the
default QEMU PCIe subsystem root bus numbering.
Remove the bus number setting and the AST2600 bus remap logic, and drop the
corresponding "bus-nr"/rc_bus_nr fields and property plumbing. QEMU now relies
on the default root bus 0 behavior.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/pci-host/aspeed_pcie.h | 2 --
hw/pci-host/aspeed_pcie.c | 19 +------------------
2 files changed, 1 insertion(+), 20 deletions(-)
diff --git a/include/hw/pci-host/aspeed_pcie.h b/include/hw/pci-host/aspeed_pcie.h
index fde5816ea3..143b356591 100644
--- a/include/hw/pci-host/aspeed_pcie.h
+++ b/include/hw/pci-host/aspeed_pcie.h
@@ -69,7 +69,6 @@ struct AspeedPCIERcState {
uint64_t dram_base;
uint32_t msi_addr;
uint32_t rp_addr;
- uint32_t bus_nr;
char name[16];
qemu_irq irq;
@@ -102,7 +101,6 @@ struct AspeedPCIECfgClass {
uint32_t rc_msi_addr;
uint32_t rc_rp_addr;
- uint64_t rc_bus_nr;
uint64_t nr_regs;
bool rc_has_rd;
};
diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c
index 4fdda95939..4f896f855c 100644
--- a/hw/pci-host/aspeed_pcie.c
+++ b/hw/pci-host/aspeed_pcie.c
@@ -268,7 +268,7 @@ static const char *aspeed_pcie_rc_root_bus_path(PCIHostState *host_bridge,
AspeedPCIECfgState *cfg =
container_of(rc, AspeedPCIECfgState, rc);
- snprintf(rc->name, sizeof(rc->name), "%04x:%02x", cfg->id, rc->bus_nr);
+ snprintf(rc->name, sizeof(rc->name), "%04x:00", cfg->id);
return rc->name;
}
@@ -283,7 +283,6 @@ static void aspeed_pcie_rc_instance_init(Object *obj)
}
static const Property aspeed_pcie_rc_props[] = {
- DEFINE_PROP_UINT32("bus-nr", AspeedPCIERcState, bus_nr, 0),
DEFINE_PROP_UINT32("rp-addr", AspeedPCIERcState, rp_addr, 0),
DEFINE_PROP_UINT32("msi-addr", AspeedPCIERcState, msi_addr, 0),
DEFINE_PROP_UINT64("dram-base", AspeedPCIERcState, dram_base, 0),
@@ -490,17 +489,6 @@ static void aspeed_pcie_cfg_readwrite(AspeedPCIECfgState *s,
offset = cfg_addr & 0xffc;
pci = PCI_HOST_BRIDGE(rc);
-
- /*
- * On the AST2600, the RC_H bus number range from 0x80 to 0xFF, with the
- * root device and root port assigned to bus 0x80 instead of the standard
- * 0x00. To allow the PCI subsystem to correctly discover devices on the
- * root bus, bus 0x80 is remapped to 0x00.
- */
- if (bus == rc->bus_nr) {
- bus = 0;
- }
-
pdev = pci_find_device(pci->bus, bus, devfn);
if (!pdev) {
s->regs[desc->rdata_reg] = ~0;
@@ -650,9 +638,6 @@ static void aspeed_pcie_cfg_realize(DeviceState *dev, Error **errp)
apc->nr_regs << 2);
sysbus_init_mmio(sbd, &s->mmio);
- object_property_set_int(OBJECT(&s->rc), "bus-nr",
- apc->rc_bus_nr,
- &error_abort);
object_property_set_int(OBJECT(&s->rc), "rp-addr",
apc->rc_rp_addr,
&error_abort);
@@ -691,7 +676,6 @@ static void aspeed_pcie_cfg_class_init(ObjectClass *klass, const void *data)
apc->reg_map = &aspeed_regmap;
apc->nr_regs = 0x100 >> 2;
apc->rc_msi_addr = 0x1e77005C;
- apc->rc_bus_nr = 0x80;
apc->rc_rp_addr = PCI_DEVFN(8, 0);
}
@@ -811,7 +795,6 @@ static void aspeed_2700_pcie_cfg_class_init(ObjectClass *klass,
apc->reg_map = &aspeed_2700_regmap;
apc->nr_regs = 0x100 >> 2;
apc->rc_msi_addr = 0x000000F0;
- apc->rc_bus_nr = 0;
apc->rc_rp_addr = PCI_DEVFN(0, 0);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v1 3/7] hw/pci-host/aspeed_pcie: Drop AST2600 RC_H root-bus remap and bus-nr property
@ 2026-01-27 3:23 ` Jamin Lin via qemu development
0 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-27 3:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
The original AST2600 PCIe design supported both RC_L and RC_H, using root bus
number 0 for RC_L and 0x80 for RC_H. In that model, the root port appeared as
80:08.0 and QEMU carried a "bus-nr" property plus a config-space bus remap to
translate bus 0x80 to bus 0x00 for PCI enumeration.
Linux mainline has since dropped RC_L support and updated the RC_H root bus
number to start at 0. The root port is now enumerated as 00:08.0, matching the
default QEMU PCIe subsystem root bus numbering.
Remove the bus number setting and the AST2600 bus remap logic, and drop the
corresponding "bus-nr"/rc_bus_nr fields and property plumbing. QEMU now relies
on the default root bus 0 behavior.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/pci-host/aspeed_pcie.h | 2 --
hw/pci-host/aspeed_pcie.c | 19 +------------------
2 files changed, 1 insertion(+), 20 deletions(-)
diff --git a/include/hw/pci-host/aspeed_pcie.h b/include/hw/pci-host/aspeed_pcie.h
index fde5816ea3..143b356591 100644
--- a/include/hw/pci-host/aspeed_pcie.h
+++ b/include/hw/pci-host/aspeed_pcie.h
@@ -69,7 +69,6 @@ struct AspeedPCIERcState {
uint64_t dram_base;
uint32_t msi_addr;
uint32_t rp_addr;
- uint32_t bus_nr;
char name[16];
qemu_irq irq;
@@ -102,7 +101,6 @@ struct AspeedPCIECfgClass {
uint32_t rc_msi_addr;
uint32_t rc_rp_addr;
- uint64_t rc_bus_nr;
uint64_t nr_regs;
bool rc_has_rd;
};
diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c
index 4fdda95939..4f896f855c 100644
--- a/hw/pci-host/aspeed_pcie.c
+++ b/hw/pci-host/aspeed_pcie.c
@@ -268,7 +268,7 @@ static const char *aspeed_pcie_rc_root_bus_path(PCIHostState *host_bridge,
AspeedPCIECfgState *cfg =
container_of(rc, AspeedPCIECfgState, rc);
- snprintf(rc->name, sizeof(rc->name), "%04x:%02x", cfg->id, rc->bus_nr);
+ snprintf(rc->name, sizeof(rc->name), "%04x:00", cfg->id);
return rc->name;
}
@@ -283,7 +283,6 @@ static void aspeed_pcie_rc_instance_init(Object *obj)
}
static const Property aspeed_pcie_rc_props[] = {
- DEFINE_PROP_UINT32("bus-nr", AspeedPCIERcState, bus_nr, 0),
DEFINE_PROP_UINT32("rp-addr", AspeedPCIERcState, rp_addr, 0),
DEFINE_PROP_UINT32("msi-addr", AspeedPCIERcState, msi_addr, 0),
DEFINE_PROP_UINT64("dram-base", AspeedPCIERcState, dram_base, 0),
@@ -490,17 +489,6 @@ static void aspeed_pcie_cfg_readwrite(AspeedPCIECfgState *s,
offset = cfg_addr & 0xffc;
pci = PCI_HOST_BRIDGE(rc);
-
- /*
- * On the AST2600, the RC_H bus number range from 0x80 to 0xFF, with the
- * root device and root port assigned to bus 0x80 instead of the standard
- * 0x00. To allow the PCI subsystem to correctly discover devices on the
- * root bus, bus 0x80 is remapped to 0x00.
- */
- if (bus == rc->bus_nr) {
- bus = 0;
- }
-
pdev = pci_find_device(pci->bus, bus, devfn);
if (!pdev) {
s->regs[desc->rdata_reg] = ~0;
@@ -650,9 +638,6 @@ static void aspeed_pcie_cfg_realize(DeviceState *dev, Error **errp)
apc->nr_regs << 2);
sysbus_init_mmio(sbd, &s->mmio);
- object_property_set_int(OBJECT(&s->rc), "bus-nr",
- apc->rc_bus_nr,
- &error_abort);
object_property_set_int(OBJECT(&s->rc), "rp-addr",
apc->rc_rp_addr,
&error_abort);
@@ -691,7 +676,6 @@ static void aspeed_pcie_cfg_class_init(ObjectClass *klass, const void *data)
apc->reg_map = &aspeed_regmap;
apc->nr_regs = 0x100 >> 2;
apc->rc_msi_addr = 0x1e77005C;
- apc->rc_bus_nr = 0x80;
apc->rc_rp_addr = PCI_DEVFN(8, 0);
}
@@ -811,7 +795,6 @@ static void aspeed_2700_pcie_cfg_class_init(ObjectClass *klass,
apc->reg_map = &aspeed_2700_regmap;
apc->nr_regs = 0x100 >> 2;
apc->rc_msi_addr = 0x000000F0;
- apc->rc_bus_nr = 0;
apc->rc_rp_addr = PCI_DEVFN(0, 0);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v1 3/7] hw/pci-host/aspeed_pcie: Drop AST2600 RC_H root-bus remap and bus-nr property
2026-01-27 3:23 ` Jamin Lin via qemu development
(?)
@ 2026-01-28 10:43 ` Cédric Le Goater
2026-01-29 2:10 ` Jamin Lin
-1 siblings, 1 reply; 20+ messages in thread
From: Cédric Le Goater @ 2026-01-28 10:43 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, kane_chen
On 1/27/26 04:23, Jamin Lin via qemu development wrote:
> The original AST2600 PCIe design supported both RC_L and RC_H, using root bus
> number 0 for RC_L and 0x80 for RC_H. In that model, the root port appeared as
> 80:08.0 and QEMU carried a "bus-nr" property plus a config-space bus remap to
> translate bus 0x80 to bus 0x00 for PCI enumeration.
>
> Linux mainline has since dropped RC_L support and updated the RC_H root bus
Was PCI support for the Aspeed SoC merged in mainline ?
Thanks,
C.
> number to start at 0. The root port is now enumerated as 00:08.0, matching the
> default QEMU PCIe subsystem root bus numbering.
>
> Remove the bus number setting and the AST2600 bus remap logic, and drop the
> corresponding "bus-nr"/rc_bus_nr fields and property plumbing. QEMU now relies
> on the default root bus 0 behavior.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> include/hw/pci-host/aspeed_pcie.h | 2 --
> hw/pci-host/aspeed_pcie.c | 19 +------------------
> 2 files changed, 1 insertion(+), 20 deletions(-)
>
> diff --git a/include/hw/pci-host/aspeed_pcie.h b/include/hw/pci-host/aspeed_pcie.h
> index fde5816ea3..143b356591 100644
> --- a/include/hw/pci-host/aspeed_pcie.h
> +++ b/include/hw/pci-host/aspeed_pcie.h
> @@ -69,7 +69,6 @@ struct AspeedPCIERcState {
> uint64_t dram_base;
> uint32_t msi_addr;
> uint32_t rp_addr;
> - uint32_t bus_nr;
> char name[16];
> qemu_irq irq;
>
> @@ -102,7 +101,6 @@ struct AspeedPCIECfgClass {
>
> uint32_t rc_msi_addr;
> uint32_t rc_rp_addr;
> - uint64_t rc_bus_nr;
> uint64_t nr_regs;
> bool rc_has_rd;
> };
> diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c
> index 4fdda95939..4f896f855c 100644
> --- a/hw/pci-host/aspeed_pcie.c
> +++ b/hw/pci-host/aspeed_pcie.c
> @@ -268,7 +268,7 @@ static const char *aspeed_pcie_rc_root_bus_path(PCIHostState *host_bridge,
> AspeedPCIECfgState *cfg =
> container_of(rc, AspeedPCIECfgState, rc);
>
> - snprintf(rc->name, sizeof(rc->name), "%04x:%02x", cfg->id, rc->bus_nr);
> + snprintf(rc->name, sizeof(rc->name), "%04x:00", cfg->id);
>
> return rc->name;
> }
> @@ -283,7 +283,6 @@ static void aspeed_pcie_rc_instance_init(Object *obj)
> }
>
> static const Property aspeed_pcie_rc_props[] = {
> - DEFINE_PROP_UINT32("bus-nr", AspeedPCIERcState, bus_nr, 0),
> DEFINE_PROP_UINT32("rp-addr", AspeedPCIERcState, rp_addr, 0),
> DEFINE_PROP_UINT32("msi-addr", AspeedPCIERcState, msi_addr, 0),
> DEFINE_PROP_UINT64("dram-base", AspeedPCIERcState, dram_base, 0),
> @@ -490,17 +489,6 @@ static void aspeed_pcie_cfg_readwrite(AspeedPCIECfgState *s,
> offset = cfg_addr & 0xffc;
>
> pci = PCI_HOST_BRIDGE(rc);
> -
> - /*
> - * On the AST2600, the RC_H bus number range from 0x80 to 0xFF, with the
> - * root device and root port assigned to bus 0x80 instead of the standard
> - * 0x00. To allow the PCI subsystem to correctly discover devices on the
> - * root bus, bus 0x80 is remapped to 0x00.
> - */
> - if (bus == rc->bus_nr) {
> - bus = 0;
> - }
> -
> pdev = pci_find_device(pci->bus, bus, devfn);
> if (!pdev) {
> s->regs[desc->rdata_reg] = ~0;
> @@ -650,9 +638,6 @@ static void aspeed_pcie_cfg_realize(DeviceState *dev, Error **errp)
> apc->nr_regs << 2);
> sysbus_init_mmio(sbd, &s->mmio);
>
> - object_property_set_int(OBJECT(&s->rc), "bus-nr",
> - apc->rc_bus_nr,
> - &error_abort);
> object_property_set_int(OBJECT(&s->rc), "rp-addr",
> apc->rc_rp_addr,
> &error_abort);
> @@ -691,7 +676,6 @@ static void aspeed_pcie_cfg_class_init(ObjectClass *klass, const void *data)
> apc->reg_map = &aspeed_regmap;
> apc->nr_regs = 0x100 >> 2;
> apc->rc_msi_addr = 0x1e77005C;
> - apc->rc_bus_nr = 0x80;
> apc->rc_rp_addr = PCI_DEVFN(8, 0);
> }
>
> @@ -811,7 +795,6 @@ static void aspeed_2700_pcie_cfg_class_init(ObjectClass *klass,
> apc->reg_map = &aspeed_2700_regmap;
> apc->nr_regs = 0x100 >> 2;
> apc->rc_msi_addr = 0x000000F0;
> - apc->rc_bus_nr = 0;
> apc->rc_rp_addr = PCI_DEVFN(0, 0);
> }
>
^ permalink raw reply [flat|nested] 20+ messages in thread* RE: [PATCH v1 3/7] hw/pci-host/aspeed_pcie: Drop AST2600 RC_H root-bus remap and bus-nr property
2026-01-28 10:43 ` Cédric Le Goater
@ 2026-01-29 2:10 ` Jamin Lin
2026-01-29 7:06 ` Cédric Le Goater
0 siblings, 1 reply; 20+ messages in thread
From: Jamin Lin @ 2026-01-29 2:10 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Kane Chen
Hi Cédric
> Subject: Re: [PATCH v1 3/7] hw/pci-host/aspeed_pcie: Drop AST2600 RC_H
> root-bus remap and bus-nr property
>
> On 1/27/26 04:23, Jamin Lin via qemu development wrote:
> > The original AST2600 PCIe design supported both RC_L and RC_H, using
> > root bus number 0 for RC_L and 0x80 for RC_H. In that model, the root
> > port appeared as
> > 80:08.0 and QEMU carried a "bus-nr" property plus a config-space bus
> > remap to translate bus 0x80 to bus 0x00 for PCI enumeration.
> >
> > Linux mainline has since dropped RC_L support and updated the RC_H
> > root bus
>
> Was PCI support for the Aspeed SoC merged in mainline ?
>
The ASPEED PCIe RC driver has been applied to the PCIe subtree in the next branch.
Please refer to the following links for details.
The change will be merged into the Linux mainline soon.
https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/log/?h=next
https://lore.kernel.org/linux-pci/20251216-upstream_pcie_rc-v7-0-4aeb0f53c4ce@aspeedtech.com/T/#eb13673b4787528d636afa40791ae43d38bd1152a
https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/commit/?h=next&id=51aa64d4c19f0f00fd50cafd37cc2328675053ab
Thanks,
Jamin
> Thanks,
>
> C.
>
> > number to start at 0. The root port is now enumerated as 00:08.0,
> > matching the default QEMU PCIe subsystem root bus numbering.
> >
> > Remove the bus number setting and the AST2600 bus remap logic, and
> > drop the corresponding "bus-nr"/rc_bus_nr fields and property
> > plumbing. QEMU now relies on the default root bus 0 behavior.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> > include/hw/pci-host/aspeed_pcie.h | 2 --
> > hw/pci-host/aspeed_pcie.c | 19 +------------------
> > 2 files changed, 1 insertion(+), 20 deletions(-)
> >
> > diff --git a/include/hw/pci-host/aspeed_pcie.h
> > b/include/hw/pci-host/aspeed_pcie.h
> > index fde5816ea3..143b356591 100644
> > --- a/include/hw/pci-host/aspeed_pcie.h
> > +++ b/include/hw/pci-host/aspeed_pcie.h
> > @@ -69,7 +69,6 @@ struct AspeedPCIERcState {
> > uint64_t dram_base;
> > uint32_t msi_addr;
> > uint32_t rp_addr;
> > - uint32_t bus_nr;
> > char name[16];
> > qemu_irq irq;
> >
> > @@ -102,7 +101,6 @@ struct AspeedPCIECfgClass {
> >
> > uint32_t rc_msi_addr;
> > uint32_t rc_rp_addr;
> > - uint64_t rc_bus_nr;
> > uint64_t nr_regs;
> > bool rc_has_rd;
> > };
> > diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c
> > index 4fdda95939..4f896f855c 100644
> > --- a/hw/pci-host/aspeed_pcie.c
> > +++ b/hw/pci-host/aspeed_pcie.c
> > @@ -268,7 +268,7 @@ static const char
> *aspeed_pcie_rc_root_bus_path(PCIHostState *host_bridge,
> > AspeedPCIECfgState *cfg =
> > container_of(rc, AspeedPCIECfgState, rc);
> >
> > - snprintf(rc->name, sizeof(rc->name), "%04x:%02x", cfg->id, rc->bus_nr);
> > + snprintf(rc->name, sizeof(rc->name), "%04x:00", cfg->id);
> >
> > return rc->name;
> > }
> > @@ -283,7 +283,6 @@ static void aspeed_pcie_rc_instance_init(Object
> *obj)
> > }
> >
> > static const Property aspeed_pcie_rc_props[] = {
> > - DEFINE_PROP_UINT32("bus-nr", AspeedPCIERcState, bus_nr, 0),
> > DEFINE_PROP_UINT32("rp-addr", AspeedPCIERcState, rp_addr, 0),
> > DEFINE_PROP_UINT32("msi-addr", AspeedPCIERcState, msi_addr, 0),
> > DEFINE_PROP_UINT64("dram-base", AspeedPCIERcState,
> dram_base,
> > 0), @@ -490,17 +489,6 @@ static void
> aspeed_pcie_cfg_readwrite(AspeedPCIECfgState *s,
> > offset = cfg_addr & 0xffc;
> >
> > pci = PCI_HOST_BRIDGE(rc);
> > -
> > - /*
> > - * On the AST2600, the RC_H bus number range from 0x80 to 0xFF,
> with the
> > - * root device and root port assigned to bus 0x80 instead of the
> standard
> > - * 0x00. To allow the PCI subsystem to correctly discover devices on
> the
> > - * root bus, bus 0x80 is remapped to 0x00.
> > - */
> > - if (bus == rc->bus_nr) {
> > - bus = 0;
> > - }
> > -
> > pdev = pci_find_device(pci->bus, bus, devfn);
> > if (!pdev) {
> > s->regs[desc->rdata_reg] = ~0; @@ -650,9 +638,6 @@ static
> > void aspeed_pcie_cfg_realize(DeviceState *dev, Error **errp)
> > apc->nr_regs << 2);
> > sysbus_init_mmio(sbd, &s->mmio);
> >
> > - object_property_set_int(OBJECT(&s->rc), "bus-nr",
> > - apc->rc_bus_nr,
> > - &error_abort);
> > object_property_set_int(OBJECT(&s->rc), "rp-addr",
> > apc->rc_rp_addr,
> > &error_abort); @@ -691,7 +676,6 @@
> > static void aspeed_pcie_cfg_class_init(ObjectClass *klass, const void *data)
> > apc->reg_map = &aspeed_regmap;
> > apc->nr_regs = 0x100 >> 2;
> > apc->rc_msi_addr = 0x1e77005C;
> > - apc->rc_bus_nr = 0x80;
> > apc->rc_rp_addr = PCI_DEVFN(8, 0);
> > }
> >
> > @@ -811,7 +795,6 @@ static void
> aspeed_2700_pcie_cfg_class_init(ObjectClass *klass,
> > apc->reg_map = &aspeed_2700_regmap;
> > apc->nr_regs = 0x100 >> 2;
> > apc->rc_msi_addr = 0x000000F0;
> > - apc->rc_bus_nr = 0;
> > apc->rc_rp_addr = PCI_DEVFN(0, 0);
> > }
> >
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v1 3/7] hw/pci-host/aspeed_pcie: Drop AST2600 RC_H root-bus remap and bus-nr property
2026-01-29 2:10 ` Jamin Lin
@ 2026-01-29 7:06 ` Cédric Le Goater
0 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2026-01-29 7:06 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Kane Chen
On 1/29/26 03:10, Jamin Lin wrote:
> Hi Cédric
>
>> Subject: Re: [PATCH v1 3/7] hw/pci-host/aspeed_pcie: Drop AST2600 RC_H
>> root-bus remap and bus-nr property
>>
>> On 1/27/26 04:23, Jamin Lin via qemu development wrote:
>>> The original AST2600 PCIe design supported both RC_L and RC_H, using
>>> root bus number 0 for RC_L and 0x80 for RC_H. In that model, the root
>>> port appeared as
>>> 80:08.0 and QEMU carried a "bus-nr" property plus a config-space bus
>>> remap to translate bus 0x80 to bus 0x00 for PCI enumeration.
>>>
>>> Linux mainline has since dropped RC_L support and updated the RC_H
>>> root bus
>>
>> Was PCI support for the Aspeed SoC merged in mainline ?
>>
>
> The ASPEED PCIe RC driver has been applied to the PCIe subtree in the next branch.
> Please refer to the following links for details.
> The change will be merged into the Linux mainline soon.
>
> https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/log/?h=next
> https://lore.kernel.org/linux-pci/20251216-upstream_pcie_rc-v7-0-4aeb0f53c4ce@aspeedtech.com/T/#eb13673b4787528d636afa40791ae43d38bd1152a
> https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/commit/?h=next&id=51aa64d4c19f0f00fd50cafd37cc2328675053ab
Great ! nice work.
Thanks,
C.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v1 4/7] hw/arm/aspeed_ast2600: Expand RC_H PCIe MMIO window to 0x60000000 - 0x80000000
2026-01-27 3:23 ` Jamin Lin via qemu development
@ 2026-01-27 3:23 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via @ 2026-01-27 3:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Historically, the ASPEED PCIe driver supported both RC_L and RC_H, with RC_L
using MMIO window 0x60000000 - 0x70000000 and RC_H using 0x70000000 - 0x80000000.
Mainline Linux has dropped RC_L support and now supports RC_H only, updating
RC_H to use a single combined MMIO window 0x60000000 - 0x80000000.
Update the AST2600 QEMU model accordingly by moving PCIE_MMIO1 base to
0x60000000 and increasing the aliased MMIO size to 0x20000000.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast2600.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 4c5a42ea17..efb1d8c063 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -81,7 +81,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
[ASPEED_DEV_FSI1] = 0x1E79B000,
[ASPEED_DEV_FSI2] = 0x1E79B100,
[ASPEED_DEV_I3C] = 0x1E7A0000,
- [ASPEED_DEV_PCIE_MMIO1] = 0x70000000,
+ [ASPEED_DEV_PCIE_MMIO1] = 0x60000000,
[ASPEED_DEV_SDRAM] = 0x80000000,
};
@@ -303,14 +303,14 @@ static uint64_t aspeed_calc_affinity(int cpu)
*
* Model scope / limitations:
* - Firmware supports RC_H only; this QEMU model does not support RC_L.
- * - RC_H uses PHY1 and the MMIO window [0x70000000, 0x80000000]
+ * - RC_H uses PHY1 and the MMIO window [0x60000000, 0x80000000]
* (aka MMIO1).
*
* Indexing convention (this model):
* - Expose a single logical instance at index 0.
* - pcie[0] -> hardware RC_H (PCIe1)
* - phy[0] -> hardware PHY1
- * - mmio.0 -> guest address range MMIO1: 0x70000000-0x80000000
+ * - mmio.0 -> guest address range MMIO1: 0x60000000-0x80000000
* - RC_L / PCIe0 is not created and mapped.
*/
static bool aspeed_soc_ast2600_pcie_realize(DeviceState *dev, Error **errp)
@@ -346,7 +346,7 @@ static bool aspeed_soc_ast2600_pcie_realize(DeviceState *dev, Error **errp)
memory_region_init_alias(&s->pcie_mmio_alias[0], OBJECT(&s->pcie[0].rc),
"aspeed.pcie-mmio", mmio_mr,
sc->memmap[ASPEED_DEV_PCIE_MMIO1],
- 0x10000000);
+ 0x20000000);
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_PCIE_MMIO1],
&s->pcie_mmio_alias[0]);
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v1 4/7] hw/arm/aspeed_ast2600: Expand RC_H PCIe MMIO window to 0x60000000 - 0x80000000
@ 2026-01-27 3:23 ` Jamin Lin via qemu development
0 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-27 3:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Historically, the ASPEED PCIe driver supported both RC_L and RC_H, with RC_L
using MMIO window 0x60000000 - 0x70000000 and RC_H using 0x70000000 - 0x80000000.
Mainline Linux has dropped RC_L support and now supports RC_H only, updating
RC_H to use a single combined MMIO window 0x60000000 - 0x80000000.
Update the AST2600 QEMU model accordingly by moving PCIE_MMIO1 base to
0x60000000 and increasing the aliased MMIO size to 0x20000000.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast2600.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 4c5a42ea17..efb1d8c063 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -81,7 +81,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
[ASPEED_DEV_FSI1] = 0x1E79B000,
[ASPEED_DEV_FSI2] = 0x1E79B100,
[ASPEED_DEV_I3C] = 0x1E7A0000,
- [ASPEED_DEV_PCIE_MMIO1] = 0x70000000,
+ [ASPEED_DEV_PCIE_MMIO1] = 0x60000000,
[ASPEED_DEV_SDRAM] = 0x80000000,
};
@@ -303,14 +303,14 @@ static uint64_t aspeed_calc_affinity(int cpu)
*
* Model scope / limitations:
* - Firmware supports RC_H only; this QEMU model does not support RC_L.
- * - RC_H uses PHY1 and the MMIO window [0x70000000, 0x80000000]
+ * - RC_H uses PHY1 and the MMIO window [0x60000000, 0x80000000]
* (aka MMIO1).
*
* Indexing convention (this model):
* - Expose a single logical instance at index 0.
* - pcie[0] -> hardware RC_H (PCIe1)
* - phy[0] -> hardware PHY1
- * - mmio.0 -> guest address range MMIO1: 0x70000000-0x80000000
+ * - mmio.0 -> guest address range MMIO1: 0x60000000-0x80000000
* - RC_L / PCIe0 is not created and mapped.
*/
static bool aspeed_soc_ast2600_pcie_realize(DeviceState *dev, Error **errp)
@@ -346,7 +346,7 @@ static bool aspeed_soc_ast2600_pcie_realize(DeviceState *dev, Error **errp)
memory_region_init_alias(&s->pcie_mmio_alias[0], OBJECT(&s->pcie[0].rc),
"aspeed.pcie-mmio", mmio_mr,
sc->memmap[ASPEED_DEV_PCIE_MMIO1],
- 0x10000000);
+ 0x20000000);
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_PCIE_MMIO1],
&s->pcie_mmio_alias[0]);
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v1 5/7] tests/functional/arm/test_aspeed_ast2600_sdk: Update test ASPEED SDK v11.00
2026-01-27 3:23 ` Jamin Lin via qemu development
@ 2026-01-27 3:23 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via @ 2026-01-27 3:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Drop root device and set root bus number to 0.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
.../functional/arm/test_aspeed_ast2600_sdk.py | 22 ++++++++-----------
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/tests/functional/arm/test_aspeed_ast2600_sdk.py b/tests/functional/arm/test_aspeed_ast2600_sdk.py
index e3d4ed09e2..6236aeb11c 100755
--- a/tests/functional/arm/test_aspeed_ast2600_sdk.py
+++ b/tests/functional/arm/test_aspeed_ast2600_sdk.py
@@ -14,22 +14,18 @@
class AST2600Machine(AspeedTest):
- ASSET_SDK_V908_AST2600 = Asset(
- 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.08/ast2600-default-obmc.tar.gz',
- 'a0414f14ad696550efe083c2156dbeda855c08cc9ae7f40fe1b41bf292295f82')
+ ASSET_SDK_V1100_AST2600 = Asset(
+ 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2600-default-obmc.tar.gz',
+ '64d8926a7d01b649168be96c986603b5690f06391286c438a3a772c8c7039e93')
def do_ast2600_pcie_test(self):
exec_command_and_wait_for_pattern(self,
- 'lspci -s 80:00.0',
- '80:00.0 Host bridge: '
- 'ASPEED Technology, Inc. Device 2600')
- exec_command_and_wait_for_pattern(self,
- 'lspci -s 80:08.0',
- '80:08.0 PCI bridge: '
+ 'lspci -s 00:08.0',
+ '00:08.0 PCI bridge: '
'ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge')
exec_command_and_wait_for_pattern(self,
- 'lspci -s 81:00.0',
- '81:00.0 Ethernet controller: '
+ 'lspci -s 01:00.0',
+ '01:00.0 Ethernet controller: '
'Intel Corporation 82574L Gigabit Network Connection')
exec_command_and_wait_for_pattern(self,
'ip addr show dev eth4',
@@ -39,7 +35,7 @@ def test_arm_ast2600_evb_sdk(self):
self.set_machine('ast2600-evb')
self.require_netdev('user')
- self.archive_extract(self.ASSET_SDK_V908_AST2600)
+ self.archive_extract(self.ASSET_SDK_V1100_AST2600)
self.vm.add_args('-device',
'tmp105,bus=aspeed.i2c.bus.5,address=0x4d,id=tmp-test')
@@ -77,7 +73,7 @@ def test_arm_ast2600_evb_sdk(self):
def test_arm_ast2600_otp_blockdev_device(self):
self.vm.set_machine("ast2600-evb")
- image_path = self.archive_extract(self.ASSET_SDK_V908_AST2600)
+ image_path = self.archive_extract(self.ASSET_SDK_V1100_AST2600)
otp_img = self.generate_otpmem_image()
self.vm.set_console()
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v1 5/7] tests/functional/arm/test_aspeed_ast2600_sdk: Update test ASPEED SDK v11.00
@ 2026-01-27 3:23 ` Jamin Lin via qemu development
0 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-27 3:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Drop root device and set root bus number to 0.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
.../functional/arm/test_aspeed_ast2600_sdk.py | 22 ++++++++-----------
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/tests/functional/arm/test_aspeed_ast2600_sdk.py b/tests/functional/arm/test_aspeed_ast2600_sdk.py
index e3d4ed09e2..6236aeb11c 100755
--- a/tests/functional/arm/test_aspeed_ast2600_sdk.py
+++ b/tests/functional/arm/test_aspeed_ast2600_sdk.py
@@ -14,22 +14,18 @@
class AST2600Machine(AspeedTest):
- ASSET_SDK_V908_AST2600 = Asset(
- 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.08/ast2600-default-obmc.tar.gz',
- 'a0414f14ad696550efe083c2156dbeda855c08cc9ae7f40fe1b41bf292295f82')
+ ASSET_SDK_V1100_AST2600 = Asset(
+ 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2600-default-obmc.tar.gz',
+ '64d8926a7d01b649168be96c986603b5690f06391286c438a3a772c8c7039e93')
def do_ast2600_pcie_test(self):
exec_command_and_wait_for_pattern(self,
- 'lspci -s 80:00.0',
- '80:00.0 Host bridge: '
- 'ASPEED Technology, Inc. Device 2600')
- exec_command_and_wait_for_pattern(self,
- 'lspci -s 80:08.0',
- '80:08.0 PCI bridge: '
+ 'lspci -s 00:08.0',
+ '00:08.0 PCI bridge: '
'ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge')
exec_command_and_wait_for_pattern(self,
- 'lspci -s 81:00.0',
- '81:00.0 Ethernet controller: '
+ 'lspci -s 01:00.0',
+ '01:00.0 Ethernet controller: '
'Intel Corporation 82574L Gigabit Network Connection')
exec_command_and_wait_for_pattern(self,
'ip addr show dev eth4',
@@ -39,7 +35,7 @@ def test_arm_ast2600_evb_sdk(self):
self.set_machine('ast2600-evb')
self.require_netdev('user')
- self.archive_extract(self.ASSET_SDK_V908_AST2600)
+ self.archive_extract(self.ASSET_SDK_V1100_AST2600)
self.vm.add_args('-device',
'tmp105,bus=aspeed.i2c.bus.5,address=0x4d,id=tmp-test')
@@ -77,7 +73,7 @@ def test_arm_ast2600_evb_sdk(self):
def test_arm_ast2600_otp_blockdev_device(self):
self.vm.set_machine("ast2600-evb")
- image_path = self.archive_extract(self.ASSET_SDK_V908_AST2600)
+ image_path = self.archive_extract(self.ASSET_SDK_V1100_AST2600)
otp_img = self.generate_otpmem_image()
self.vm.set_console()
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v1 6/7] tests/functional/arm/test_aspeed_ast1060: Update test aspeed-zephyr-project v03.04
2026-01-27 3:23 ` Jamin Lin via qemu development
@ 2026-01-27 3:23 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via @ 2026-01-27 3:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
tests/functional/arm/test_aspeed_ast1060.py | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/tests/functional/arm/test_aspeed_ast1060.py b/tests/functional/arm/test_aspeed_ast1060.py
index 034efa5342..eccb4252d8 100644
--- a/tests/functional/arm/test_aspeed_ast1060.py
+++ b/tests/functional/arm/test_aspeed_ast1060.py
@@ -11,18 +11,18 @@
class AST1060Machine(AspeedTest):
- ASSET_ASPEED_AST1060_PROT_3_02 = Asset(
+ ASSET_ASPEED_AST1060_PROT_3_04 = Asset(
('https://github.com/AspeedTech-BMC'
- '/aspeed-zephyr-project/releases/download/v03.02'
- '/ast1060_prot_v03.02.tgz'),
- 'dd5f1adc935316ddd1906506a02e15567bd7290657b52320f1a225564cc175bd')
+ '/aspeed-zephyr-project/releases/download/v03.04'
+ '/ast1060_prot_v03.04.tgz'),
+ 'c0319df55f5b7a547efefc5a6ba374b881223d5fe1a776bfdd36f97fd1f31d50')
- def test_arm_ast1060_prot_3_02(self):
+ def test_arm_ast1060_prot_3_04(self):
self.set_machine('ast1060-evb')
kernel_name = "ast1060_prot/zephyr.bin"
kernel_file = self.archive_extract(
- self.ASSET_ASPEED_AST1060_PROT_3_02, member=kernel_name)
+ self.ASSET_ASPEED_AST1060_PROT_3_04, member=kernel_name)
self.vm.set_console()
self.vm.add_args('-kernel', kernel_file, '-nographic')
@@ -35,7 +35,7 @@ def test_arm_ast1060_otp_blockdev_device(self):
self.vm.set_machine("ast1060-evb")
kernel_name = "ast1060_prot/zephyr.bin"
- kernel_file = self.archive_extract(self.ASSET_ASPEED_AST1060_PROT_3_02,
+ kernel_file = self.archive_extract(self.ASSET_ASPEED_AST1060_PROT_3_04,
member=kernel_name)
otp_img = self.generate_otpmem_image()
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v1 6/7] tests/functional/arm/test_aspeed_ast1060: Update test aspeed-zephyr-project v03.04
@ 2026-01-27 3:23 ` Jamin Lin via qemu development
0 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-27 3:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
tests/functional/arm/test_aspeed_ast1060.py | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/tests/functional/arm/test_aspeed_ast1060.py b/tests/functional/arm/test_aspeed_ast1060.py
index 034efa5342..eccb4252d8 100644
--- a/tests/functional/arm/test_aspeed_ast1060.py
+++ b/tests/functional/arm/test_aspeed_ast1060.py
@@ -11,18 +11,18 @@
class AST1060Machine(AspeedTest):
- ASSET_ASPEED_AST1060_PROT_3_02 = Asset(
+ ASSET_ASPEED_AST1060_PROT_3_04 = Asset(
('https://github.com/AspeedTech-BMC'
- '/aspeed-zephyr-project/releases/download/v03.02'
- '/ast1060_prot_v03.02.tgz'),
- 'dd5f1adc935316ddd1906506a02e15567bd7290657b52320f1a225564cc175bd')
+ '/aspeed-zephyr-project/releases/download/v03.04'
+ '/ast1060_prot_v03.04.tgz'),
+ 'c0319df55f5b7a547efefc5a6ba374b881223d5fe1a776bfdd36f97fd1f31d50')
- def test_arm_ast1060_prot_3_02(self):
+ def test_arm_ast1060_prot_3_04(self):
self.set_machine('ast1060-evb')
kernel_name = "ast1060_prot/zephyr.bin"
kernel_file = self.archive_extract(
- self.ASSET_ASPEED_AST1060_PROT_3_02, member=kernel_name)
+ self.ASSET_ASPEED_AST1060_PROT_3_04, member=kernel_name)
self.vm.set_console()
self.vm.add_args('-kernel', kernel_file, '-nographic')
@@ -35,7 +35,7 @@ def test_arm_ast1060_otp_blockdev_device(self):
self.vm.set_machine("ast1060-evb")
kernel_name = "ast1060_prot/zephyr.bin"
- kernel_file = self.archive_extract(self.ASSET_ASPEED_AST1060_PROT_3_02,
+ kernel_file = self.archive_extract(self.ASSET_ASPEED_AST1060_PROT_3_04,
member=kernel_name)
otp_img = self.generate_otpmem_image()
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v1 7/7] tests/functional/arm/test_aspeed_ast1030: Update test ASPEED Zephyr SDK v03.05
2026-01-27 3:23 ` Jamin Lin via qemu development
@ 2026-01-27 3:23 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via @ 2026-01-27 3:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
tests/functional/arm/test_aspeed_ast1030.py | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/tests/functional/arm/test_aspeed_ast1030.py b/tests/functional/arm/test_aspeed_ast1030.py
index d1822edd8f..0defa7c38e 100755
--- a/tests/functional/arm/test_aspeed_ast1030.py
+++ b/tests/functional/arm/test_aspeed_ast1030.py
@@ -12,17 +12,17 @@
class AST1030Machine(AspeedTest):
- ASSET_ZEPHYR_3_03 = Asset(
+ ASSET_ZEPHYR_3_05 = Asset(
('https://github.com/AspeedTech-BMC'
- '/zephyr/releases/download/v00.03.03/ast1030-evb-demo.zip'),
- '27cd73cdee6374bceb4ee58b3ace87989fa3f0684f4e612510804b588b24d4e0')
+ '/zephyr/releases/download/v00.03.05/ast1030-evb-demo.zip'),
+ '057528d343490b1fbb5a721e91084b4f04fec60dc114bd65e724554f9c217f4b')
- def test_arm_ast1030_zephyros_3_03(self):
+ def test_arm_ast1030_zephyros_3_05(self):
self.set_machine('ast1030-evb')
kernel_name = "ast1030-evb-demo/zephyr.elf"
kernel_file = self.archive_extract(
- self.ASSET_ZEPHYR_3_03, member=kernel_name)
+ self.ASSET_ZEPHYR_3_05, member=kernel_name)
self.vm.set_console()
self.vm.add_args('-kernel', kernel_file, '-nographic')
@@ -72,7 +72,7 @@ def test_arm_ast1030_otp_blockdev_device(self):
self.vm.set_machine("ast1030-evb")
kernel_name = "ast1030-evb-demo/zephyr.elf"
- kernel_file = self.archive_extract(self.ASSET_ZEPHYR_3_03,
+ kernel_file = self.archive_extract(self.ASSET_ZEPHYR_3_05,
member=kernel_name)
otp_img = self.generate_otpmem_image()
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v1 7/7] tests/functional/arm/test_aspeed_ast1030: Update test ASPEED Zephyr SDK v03.05
@ 2026-01-27 3:23 ` Jamin Lin via qemu development
0 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-27 3:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
tests/functional/arm/test_aspeed_ast1030.py | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/tests/functional/arm/test_aspeed_ast1030.py b/tests/functional/arm/test_aspeed_ast1030.py
index d1822edd8f..0defa7c38e 100755
--- a/tests/functional/arm/test_aspeed_ast1030.py
+++ b/tests/functional/arm/test_aspeed_ast1030.py
@@ -12,17 +12,17 @@
class AST1030Machine(AspeedTest):
- ASSET_ZEPHYR_3_03 = Asset(
+ ASSET_ZEPHYR_3_05 = Asset(
('https://github.com/AspeedTech-BMC'
- '/zephyr/releases/download/v00.03.03/ast1030-evb-demo.zip'),
- '27cd73cdee6374bceb4ee58b3ace87989fa3f0684f4e612510804b588b24d4e0')
+ '/zephyr/releases/download/v00.03.05/ast1030-evb-demo.zip'),
+ '057528d343490b1fbb5a721e91084b4f04fec60dc114bd65e724554f9c217f4b')
- def test_arm_ast1030_zephyros_3_03(self):
+ def test_arm_ast1030_zephyros_3_05(self):
self.set_machine('ast1030-evb')
kernel_name = "ast1030-evb-demo/zephyr.elf"
kernel_file = self.archive_extract(
- self.ASSET_ZEPHYR_3_03, member=kernel_name)
+ self.ASSET_ZEPHYR_3_05, member=kernel_name)
self.vm.set_console()
self.vm.add_args('-kernel', kernel_file, '-nographic')
@@ -72,7 +72,7 @@ def test_arm_ast1030_otp_blockdev_device(self):
self.vm.set_machine("ast1030-evb")
kernel_name = "ast1030-evb-demo/zephyr.elf"
- kernel_file = self.archive_extract(self.ASSET_ZEPHYR_3_03,
+ kernel_file = self.archive_extract(self.ASSET_ZEPHYR_3_05,
member=kernel_name)
otp_img = self.generate_otpmem_image()
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v1 0/7] Update functional tests for AST2500/AST2600/AST103/AST1060
2026-01-27 3:23 ` Jamin Lin via qemu development
` (7 preceding siblings ...)
(?)
@ 2026-01-29 7:07 ` Cédric Le Goater
-1 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2026-01-29 7:07 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, kane_chen
On 1/27/26 04:23, Jamin Lin via qemu development wrote:
> v1:
> - Remove AST2600 PCIe root device and RC_L support
> - Drop RC_H root-bus remap and bus number properties
> - Expand AST2600 RC_H PCIe MMIO window to 0x60000000�V0x80000000
> - Update functional tests for AST2500, AST2600, AST1060, and AST1030
> - AST2500 tests are updated to use SDK v10.00, as network support is known
> to be broken in v11.00.
>
> Jamin Lin (7):
> tests/functional/arm/test_aspeed_ast2500: Update test ASPEED SDK
> v10.00
> hw/pci-host/aspeed_pcie: Drop AST2600 PCIe root device
> hw/pci-host/aspeed_pcie: Drop AST2600 RC_H root-bus remap and bus-nr
> property
> hw/arm/aspeed_ast2600: Expand RC_H PCIe MMIO window to 0x60000000 -
> 0x80000000
> tests/functional/arm/test_aspeed_ast2600_sdk: Update test ASPEED SDK
> v11.00
> tests/functional/arm/test_aspeed_ast1060: Update test
> aspeed-zephyr-project v03.04
> tests/functional/arm/test_aspeed_ast1030: Update test ASPEED Zephyr
> SDK v03.05
>
> include/hw/pci-host/aspeed_pcie.h | 11 ---
> hw/arm/aspeed_ast2600.c | 8 +-
> hw/pci-host/aspeed_pcie.c | 76 +------------------
> tests/functional/arm/test_aspeed_ast1030.py | 12 +--
> tests/functional/arm/test_aspeed_ast1060.py | 14 ++--
> tests/functional/arm/test_aspeed_ast2500.py | 8 +-
> .../functional/arm/test_aspeed_ast2600_sdk.py | 22 +++---
> 7 files changed, 31 insertions(+), 120 deletions(-)
>
For the series,
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
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