* [PATCH v2 0/8] Update test ASPEED SDK v11.00 for AST2700 A1 (RESEND)
@ 2026-02-03 2:08 ` Jamin Lin via qemu development
0 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via qemu development @ 2026-02-03 2:08 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
v1
1. Update test ASPEED SDK v11.00 for AST2700 A1
2. Fix DMA moving data into incorrect address for I2C
3. Fix EHCI3/4 IRQ routing to GIC
v2
1. Fix some extra 'From' info in the mail body
Jamin Lin (8):
hw/arm/aspeed_ast27x0: Fix EHCI3/4 IRQ routing to GIC
hw/arm/aspeed_ast27x0: Sort SSP and TSP memmap tables by address
hw/arm/aspeed_ast27x0: Sort SSP and TSP IRQ maps
hw/i2c/aspeed_i2c: Fix DMA moving data into incorrect address
tests/functional/aarch64/test_aspeed_ast2700: Enable PCIe2 DTS status
for AST2700 tests
tests/functional/aarch64/test_aspeed_ast2700: Update test ASPEED SDK
v11.00 for A1
tests/functional/aarch64/test_aspeed_ast2700fc: Update test ASPEED SDK
v11.00 for A1
docs/system/arm/aspeed: Load raw U-Boot image in AST2700 boot example
docs/system/arm/aspeed.rst | 8 +-
hw/arm/aspeed_ast27x0-ssp.c | 14 +--
hw/arm/aspeed_ast27x0-tsp.c | 14 +--
hw/arm/aspeed_ast27x0.c | 2 +
hw/i2c/aspeed_i2c.c | 87 +++++++++++++------
.../functional/aarch64/test_aspeed_ast2700.py | 78 ++++++++++-------
.../aarch64/test_aspeed_ast2700fc.py | 54 ++++++------
7 files changed, 153 insertions(+), 104 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 1/8] hw/arm/aspeed_ast27x0: Fix EHCI3/4 IRQ routing to GIC
2026-02-03 2:08 ` Jamin Lin via qemu development
@ 2026-02-03 2:08 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via @ 2026-02-03 2:08 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen, Cédric Le Goater
EHCI3 and EHCI4 were missing entries in aspeed_soc_ast2700a1_irqmap,
so their source IRQs were never routed through the INTC OR-gates.
As a result, EHCI3/4 interrupts were not propagated to the GIC,
causing incorrect interrupt behavior for these controllers.
Add EHCI3 and EHCI4 to the IRQ map and route them to the same INTC
group as other shared peripherals, ensuring their interrupts are
properly connected to the GIC.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Fixes: ba27ba302a264117c8b8427f944ced1bed17c438 ("hw/arm: ast27x0: Wire up EHCI controllers")
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast27x0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index d17f446661..e16183c3b3 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -149,6 +149,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] = {
[ASPEED_DEV_ETH1] = 196,
[ASPEED_DEV_ETH2] = 196,
[ASPEED_DEV_ETH3] = 196,
+ [ASPEED_DEV_EHCI3] = 196,
+ [ASPEED_DEV_EHCI4] = 196,
[ASPEED_DEV_PECI] = 197,
[ASPEED_DEV_SDHCI] = 197,
};
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 1/8] hw/arm/aspeed_ast27x0: Fix EHCI3/4 IRQ routing to GIC
@ 2026-02-03 2:08 ` Jamin Lin via qemu development
0 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via qemu development @ 2026-02-03 2:08 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen, Cédric Le Goater
EHCI3 and EHCI4 were missing entries in aspeed_soc_ast2700a1_irqmap,
so their source IRQs were never routed through the INTC OR-gates.
As a result, EHCI3/4 interrupts were not propagated to the GIC,
causing incorrect interrupt behavior for these controllers.
Add EHCI3 and EHCI4 to the IRQ map and route them to the same INTC
group as other shared peripherals, ensuring their interrupts are
properly connected to the GIC.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Fixes: ba27ba302a264117c8b8427f944ced1bed17c438 ("hw/arm: ast27x0: Wire up EHCI controllers")
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast27x0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index d17f446661..e16183c3b3 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -149,6 +149,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] = {
[ASPEED_DEV_ETH1] = 196,
[ASPEED_DEV_ETH2] = 196,
[ASPEED_DEV_ETH3] = 196,
+ [ASPEED_DEV_EHCI3] = 196,
+ [ASPEED_DEV_EHCI4] = 196,
[ASPEED_DEV_PECI] = 197,
[ASPEED_DEV_SDHCI] = 197,
};
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v2 1/8] hw/arm/aspeed_ast27x0: Fix EHCI3/4 IRQ routing to GIC
2026-02-03 2:08 ` Jamin Lin via qemu development
(?)
@ 2026-02-05 21:07 ` Michael Tokarev
-1 siblings, 0 replies; 20+ messages in thread
From: Michael Tokarev @ 2026-02-05 21:07 UTC (permalink / raw)
To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: troy_lee, kane_chen, Cédric Le Goater, qemu-stable
On 2/3/26 05:08, Jamin Lin via qemu development wrote:
> EHCI3 and EHCI4 were missing entries in aspeed_soc_ast2700a1_irqmap,
> so their source IRQs were never routed through the INTC OR-gates.
>
> As a result, EHCI3/4 interrupts were not propagated to the GIC,
> causing incorrect interrupt behavior for these controllers.
>
> Add EHCI3 and EHCI4 to the IRQ map and route them to the same INTC
> group as other shared peripherals, ensuring their interrupts are
> properly connected to the GIC.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> Fixes: ba27ba302a264117c8b8427f944ced1bed17c438 ("hw/arm: ast27x0: Wire up EHCI controllers")
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
This looks like a qemu-stable material (10.1.x, 10.2.x).
Please let me know if it isn't.
Thanks,
/mjt
> ---
> hw/arm/aspeed_ast27x0.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index d17f446661..e16183c3b3 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -149,6 +149,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] = {
> [ASPEED_DEV_ETH1] = 196,
> [ASPEED_DEV_ETH2] = 196,
> [ASPEED_DEV_ETH3] = 196,
> + [ASPEED_DEV_EHCI3] = 196,
> + [ASPEED_DEV_EHCI4] = 196,
> [ASPEED_DEV_PECI] = 197,
> [ASPEED_DEV_SDHCI] = 197,
> };
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 2/8] hw/arm/aspeed_ast27x0: Sort SSP and TSP memmap tables by address
2026-02-03 2:08 ` Jamin Lin via qemu development
@ 2026-02-03 2:08 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via @ 2026-02-03 2:08 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen, Cédric Le Goater
Sort the SSP and TSP memmap tables to improve readability and
make the definitions easier to maintain.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast27x0-ssp.c | 10 +++++-----
hw/arm/aspeed_ast27x0-tsp.c | 10 +++++-----
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index cee937b37e..e4bcf0fa2a 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -23,15 +23,15 @@ static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
[ASPEED_DEV_SRAM] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
+ [ASPEED_DEV_TIMER1] = 0x72C10000,
+ [ASPEED_DEV_UART4] = 0x72C1A000,
+ [ASPEED_DEV_IPC0] = 0x72C1C000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
+ [ASPEED_DEV_INTCIO] = 0x74C18000,
[ASPEED_DEV_UART0] = 0x74C33000,
[ASPEED_DEV_UART1] = 0x74C33100,
[ASPEED_DEV_UART2] = 0x74C33200,
[ASPEED_DEV_UART3] = 0x74C33300,
- [ASPEED_DEV_UART4] = 0x72C1A000,
- [ASPEED_DEV_INTCIO] = 0x74C18000,
- [ASPEED_DEV_IPC0] = 0x72C1C000,
- [ASPEED_DEV_IPC1] = 0x74C39000,
[ASPEED_DEV_UART5] = 0x74C33400,
[ASPEED_DEV_UART6] = 0x74C33500,
[ASPEED_DEV_UART7] = 0x74C33600,
@@ -40,7 +40,7 @@ static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
[ASPEED_DEV_UART10] = 0x74C33900,
[ASPEED_DEV_UART11] = 0x74C33A00,
[ASPEED_DEV_UART12] = 0x74C33B00,
- [ASPEED_DEV_TIMER1] = 0x72C10000,
+ [ASPEED_DEV_IPC1] = 0x74C39000,
};
static const int aspeed_soc_ast27x0ssp_irqmap[] = {
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 9c11c016ca..68683a15d8 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -23,15 +23,15 @@ static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
[ASPEED_DEV_SRAM] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
+ [ASPEED_DEV_TIMER1] = 0x72C10000,
+ [ASPEED_DEV_UART4] = 0x72C1A000,
+ [ASPEED_DEV_IPC0] = 0x72C1C000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
+ [ASPEED_DEV_INTCIO] = 0x74C18000,
[ASPEED_DEV_UART0] = 0x74C33000,
[ASPEED_DEV_UART1] = 0x74C33100,
[ASPEED_DEV_UART2] = 0x74C33200,
[ASPEED_DEV_UART3] = 0x74C33300,
- [ASPEED_DEV_UART4] = 0x72C1A000,
- [ASPEED_DEV_INTCIO] = 0x74C18000,
- [ASPEED_DEV_IPC0] = 0x72C1C000,
- [ASPEED_DEV_IPC1] = 0x74C39000,
[ASPEED_DEV_UART5] = 0x74C33400,
[ASPEED_DEV_UART6] = 0x74C33500,
[ASPEED_DEV_UART7] = 0x74C33600,
@@ -40,7 +40,7 @@ static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
[ASPEED_DEV_UART10] = 0x74C33900,
[ASPEED_DEV_UART11] = 0x74C33A00,
[ASPEED_DEV_UART12] = 0x74C33B00,
- [ASPEED_DEV_TIMER1] = 0x72C10000,
+ [ASPEED_DEV_IPC1] = 0x74C39000,
};
static const int aspeed_soc_ast27x0tsp_irqmap[] = {
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 2/8] hw/arm/aspeed_ast27x0: Sort SSP and TSP memmap tables by address
@ 2026-02-03 2:08 ` Jamin Lin via qemu development
0 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via qemu development @ 2026-02-03 2:08 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen, Cédric Le Goater
Sort the SSP and TSP memmap tables to improve readability and
make the definitions easier to maintain.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast27x0-ssp.c | 10 +++++-----
hw/arm/aspeed_ast27x0-tsp.c | 10 +++++-----
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index cee937b37e..e4bcf0fa2a 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -23,15 +23,15 @@ static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
[ASPEED_DEV_SRAM] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
+ [ASPEED_DEV_TIMER1] = 0x72C10000,
+ [ASPEED_DEV_UART4] = 0x72C1A000,
+ [ASPEED_DEV_IPC0] = 0x72C1C000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
+ [ASPEED_DEV_INTCIO] = 0x74C18000,
[ASPEED_DEV_UART0] = 0x74C33000,
[ASPEED_DEV_UART1] = 0x74C33100,
[ASPEED_DEV_UART2] = 0x74C33200,
[ASPEED_DEV_UART3] = 0x74C33300,
- [ASPEED_DEV_UART4] = 0x72C1A000,
- [ASPEED_DEV_INTCIO] = 0x74C18000,
- [ASPEED_DEV_IPC0] = 0x72C1C000,
- [ASPEED_DEV_IPC1] = 0x74C39000,
[ASPEED_DEV_UART5] = 0x74C33400,
[ASPEED_DEV_UART6] = 0x74C33500,
[ASPEED_DEV_UART7] = 0x74C33600,
@@ -40,7 +40,7 @@ static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
[ASPEED_DEV_UART10] = 0x74C33900,
[ASPEED_DEV_UART11] = 0x74C33A00,
[ASPEED_DEV_UART12] = 0x74C33B00,
- [ASPEED_DEV_TIMER1] = 0x72C10000,
+ [ASPEED_DEV_IPC1] = 0x74C39000,
};
static const int aspeed_soc_ast27x0ssp_irqmap[] = {
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 9c11c016ca..68683a15d8 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -23,15 +23,15 @@ static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
[ASPEED_DEV_SRAM] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
+ [ASPEED_DEV_TIMER1] = 0x72C10000,
+ [ASPEED_DEV_UART4] = 0x72C1A000,
+ [ASPEED_DEV_IPC0] = 0x72C1C000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
+ [ASPEED_DEV_INTCIO] = 0x74C18000,
[ASPEED_DEV_UART0] = 0x74C33000,
[ASPEED_DEV_UART1] = 0x74C33100,
[ASPEED_DEV_UART2] = 0x74C33200,
[ASPEED_DEV_UART3] = 0x74C33300,
- [ASPEED_DEV_UART4] = 0x72C1A000,
- [ASPEED_DEV_INTCIO] = 0x74C18000,
- [ASPEED_DEV_IPC0] = 0x72C1C000,
- [ASPEED_DEV_IPC1] = 0x74C39000,
[ASPEED_DEV_UART5] = 0x74C33400,
[ASPEED_DEV_UART6] = 0x74C33500,
[ASPEED_DEV_UART7] = 0x74C33600,
@@ -40,7 +40,7 @@ static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
[ASPEED_DEV_UART10] = 0x74C33900,
[ASPEED_DEV_UART11] = 0x74C33A00,
[ASPEED_DEV_UART12] = 0x74C33B00,
- [ASPEED_DEV_TIMER1] = 0x72C10000,
+ [ASPEED_DEV_IPC1] = 0x74C39000,
};
static const int aspeed_soc_ast27x0tsp_irqmap[] = {
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 3/8] hw/arm/aspeed_ast27x0: Sort SSP and TSP IRQ maps
2026-02-03 2:08 ` Jamin Lin via qemu development
@ 2026-02-03 2:08 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via @ 2026-02-03 2:08 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen, Cédric Le Goater
Sort the SSP and TSP IRQ map tables to improve readability and make the
definitions easier to maintain.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast27x0-ssp.c | 4 ++--
hw/arm/aspeed_ast27x0-tsp.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index e4bcf0fa2a..9b12ba6743 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -44,12 +44,13 @@ static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
};
static const int aspeed_soc_ast27x0ssp_irqmap[] = {
+ [ASPEED_DEV_UART4] = 8,
[ASPEED_DEV_SCU] = 12,
+ [ASPEED_DEV_TIMER1] = 16,
[ASPEED_DEV_UART0] = 164,
[ASPEED_DEV_UART1] = 164,
[ASPEED_DEV_UART2] = 164,
[ASPEED_DEV_UART3] = 164,
- [ASPEED_DEV_UART4] = 8,
[ASPEED_DEV_UART5] = 164,
[ASPEED_DEV_UART6] = 164,
[ASPEED_DEV_UART7] = 164,
@@ -58,7 +59,6 @@ static const int aspeed_soc_ast27x0ssp_irqmap[] = {
[ASPEED_DEV_UART10] = 164,
[ASPEED_DEV_UART11] = 164,
[ASPEED_DEV_UART12] = 164,
- [ASPEED_DEV_TIMER1] = 16,
};
/* SSPINT 164 */
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 68683a15d8..e39d1dc171 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -44,12 +44,13 @@ static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
};
static const int aspeed_soc_ast27x0tsp_irqmap[] = {
+ [ASPEED_DEV_UART4] = 8,
[ASPEED_DEV_SCU] = 12,
+ [ASPEED_DEV_TIMER1] = 16,
[ASPEED_DEV_UART0] = 164,
[ASPEED_DEV_UART1] = 164,
[ASPEED_DEV_UART2] = 164,
[ASPEED_DEV_UART3] = 164,
- [ASPEED_DEV_UART4] = 8,
[ASPEED_DEV_UART5] = 164,
[ASPEED_DEV_UART6] = 164,
[ASPEED_DEV_UART7] = 164,
@@ -58,7 +59,6 @@ static const int aspeed_soc_ast27x0tsp_irqmap[] = {
[ASPEED_DEV_UART10] = 164,
[ASPEED_DEV_UART11] = 164,
[ASPEED_DEV_UART12] = 164,
- [ASPEED_DEV_TIMER1] = 16,
};
/* TSPINT 164 */
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 3/8] hw/arm/aspeed_ast27x0: Sort SSP and TSP IRQ maps
@ 2026-02-03 2:08 ` Jamin Lin via qemu development
0 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via qemu development @ 2026-02-03 2:08 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen, Cédric Le Goater
Sort the SSP and TSP IRQ map tables to improve readability and make the
definitions easier to maintain.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast27x0-ssp.c | 4 ++--
hw/arm/aspeed_ast27x0-tsp.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index e4bcf0fa2a..9b12ba6743 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -44,12 +44,13 @@ static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
};
static const int aspeed_soc_ast27x0ssp_irqmap[] = {
+ [ASPEED_DEV_UART4] = 8,
[ASPEED_DEV_SCU] = 12,
+ [ASPEED_DEV_TIMER1] = 16,
[ASPEED_DEV_UART0] = 164,
[ASPEED_DEV_UART1] = 164,
[ASPEED_DEV_UART2] = 164,
[ASPEED_DEV_UART3] = 164,
- [ASPEED_DEV_UART4] = 8,
[ASPEED_DEV_UART5] = 164,
[ASPEED_DEV_UART6] = 164,
[ASPEED_DEV_UART7] = 164,
@@ -58,7 +59,6 @@ static const int aspeed_soc_ast27x0ssp_irqmap[] = {
[ASPEED_DEV_UART10] = 164,
[ASPEED_DEV_UART11] = 164,
[ASPEED_DEV_UART12] = 164,
- [ASPEED_DEV_TIMER1] = 16,
};
/* SSPINT 164 */
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 68683a15d8..e39d1dc171 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -44,12 +44,13 @@ static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
};
static const int aspeed_soc_ast27x0tsp_irqmap[] = {
+ [ASPEED_DEV_UART4] = 8,
[ASPEED_DEV_SCU] = 12,
+ [ASPEED_DEV_TIMER1] = 16,
[ASPEED_DEV_UART0] = 164,
[ASPEED_DEV_UART1] = 164,
[ASPEED_DEV_UART2] = 164,
[ASPEED_DEV_UART3] = 164,
- [ASPEED_DEV_UART4] = 8,
[ASPEED_DEV_UART5] = 164,
[ASPEED_DEV_UART6] = 164,
[ASPEED_DEV_UART7] = 164,
@@ -58,7 +59,6 @@ static const int aspeed_soc_ast27x0tsp_irqmap[] = {
[ASPEED_DEV_UART10] = 164,
[ASPEED_DEV_UART11] = 164,
[ASPEED_DEV_UART12] = 164,
- [ASPEED_DEV_TIMER1] = 16,
};
/* TSPINT 164 */
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 4/8] hw/i2c/aspeed_i2c: Fix DMA moving data into incorrect address
2026-02-03 2:08 ` Jamin Lin via qemu development
@ 2026-02-03 2:08 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via @ 2026-02-03 2:08 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
In the previous design, the I2C model updated dma_dram_offset only when
firmware programmed the RX/TX DMA buffer address registers. The firmware
used to rewrite these registers before issuing each DMA command.
The firmware driver behavior has changed to program the DMA address
registers only once during I2C initialization. As a result, the I2C model
no longer refreshes dma_dram_offset, causing DMA to move data into an
incorrect DRAM address.
Fix this by introducing helper functions to update dma_dram_offset from
the DMA address registers, and invoke them right before handling TX/RX
DMA operations. This guarantees DMA always uses the correct buffer
address even if the registers are programmed only once.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Fixes: c400c38854017eeccda63115814eba4c3ef2b51f ("hw/i2c/aspeed: Introduce a new dma_dram_offset attribute in AspeedI2Cbus")
---
hw/i2c/aspeed_i2c.c | 87 +++++++++++++++++++++++++++++++--------------
1 file changed, 61 insertions(+), 26 deletions(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 1ee73a8f5e..fb3d6a5600 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -116,8 +116,6 @@ static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus *bus, hwaddr offset,
value = -1;
break;
}
-
- value = extract64(bus->dma_dram_offset, 0, 32);
break;
case A_I2CD_DMA_LEN:
if (!aic->has_dma) {
@@ -221,6 +219,64 @@ static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus)
return SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, TX_STATE);
}
+/*
+ * The AST2700 support the maximum DRAM size is 8 GB.
+ * The DRAM offset range is from 0x0_0000_0000 to
+ * 0x1_FFFF_FFFF and it is enough to use bits [33:0]
+ * saving the dram offset.
+ * Therefore, save the high part physical address bit[1:0]
+ * of Tx/Rx buffer address as dma_dram_offset bit[33:32].
+ */
+static void aspeed_i2c_set_tx_dma_dram_offset(AspeedI2CBus *bus)
+{
+ AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
+ uint32_t value;
+
+ assert(aic->has_dma);
+
+ if (aspeed_i2c_is_new_mode(bus->controller)) {
+ value = bus->regs[R_I2CM_DMA_TX_ADDR];
+ bus->dma_dram_offset =
+ deposit64(bus->dma_dram_offset, 0, 32,
+ FIELD_EX32(value, I2CM_DMA_TX_ADDR, ADDR));
+ if (!aic->has_dma64) {
+ value = bus->regs[R_I2CM_DMA_TX_ADDR_HI];
+ bus->dma_dram_offset =
+ deposit64(bus->dma_dram_offset, 32, 32,
+ extract32(value, 0, 2));
+ }
+ } else {
+ value = bus->regs[R_I2CD_DMA_ADDR];
+ bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 0, 32,
+ value & 0x3ffffffc);
+ }
+}
+
+static void aspeed_i2c_set_rx_dma_dram_offset(AspeedI2CBus *bus)
+{
+ AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
+ uint32_t value;
+
+ assert(aic->has_dma);
+
+ if (aspeed_i2c_is_new_mode(bus->controller)) {
+ value = bus->regs[R_I2CM_DMA_RX_ADDR];
+ bus->dma_dram_offset =
+ deposit64(bus->dma_dram_offset, 0, 32,
+ FIELD_EX32(value, I2CM_DMA_RX_ADDR, ADDR));
+ if (!aic->has_dma64) {
+ value = bus->regs[R_I2CM_DMA_RX_ADDR_HI];
+ bus->dma_dram_offset =
+ deposit64(bus->dma_dram_offset, 32, 32,
+ extract32(value, 0, 2));
+ }
+ } else {
+ value = bus->regs[R_I2CD_DMA_ADDR];
+ bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 0, 32,
+ value & 0x3ffffffc);
+ }
+}
+
static int aspeed_i2c_dma_read(AspeedI2CBus *bus, uint8_t *data)
{
MemTxResult result;
@@ -270,6 +326,7 @@ static int aspeed_i2c_bus_send(AspeedI2CBus *bus)
if (aspeed_i2c_is_new_mode(bus->controller)) {
ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 0);
}
+ aspeed_i2c_set_tx_dma_dram_offset(bus);
while (bus->regs[reg_dma_len]) {
uint8_t data;
ret = aspeed_i2c_dma_read(bus, &data);
@@ -335,6 +392,7 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus)
ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, 0);
}
+ aspeed_i2c_set_rx_dma_dram_offset(bus);
while (bus->regs[reg_dma_len]) {
MemTxResult result;
@@ -401,6 +459,7 @@ static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus)
} else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) {
uint8_t data;
+ aspeed_i2c_set_tx_dma_dram_offset(bus);
aspeed_i2c_dma_read(bus, &data);
return data;
} else {
@@ -657,16 +716,10 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset,
case A_I2CM_DMA_TX_ADDR:
bus->regs[R_I2CM_DMA_TX_ADDR] = FIELD_EX32(value, I2CM_DMA_TX_ADDR,
ADDR);
- bus->dma_dram_offset =
- deposit64(bus->dma_dram_offset, 0, 32,
- FIELD_EX32(value, I2CM_DMA_TX_ADDR, ADDR));
break;
case A_I2CM_DMA_RX_ADDR:
bus->regs[R_I2CM_DMA_RX_ADDR] = FIELD_EX32(value, I2CM_DMA_RX_ADDR,
ADDR);
- bus->dma_dram_offset =
- deposit64(bus->dma_dram_offset, 0, 32,
- FIELD_EX32(value, I2CM_DMA_RX_ADDR, ADDR));
break;
case A_I2CM_DMA_LEN:
w1t = FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T) ||
@@ -748,15 +801,6 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset,
qemu_log_mask(LOG_UNIMP, "%s: Slave mode DMA TX is not implemented\n",
__func__);
break;
-
- /*
- * The AST2700 support the maximum DRAM size is 8 GB.
- * The DRAM offset range is from 0x0_0000_0000 to
- * 0x1_FFFF_FFFF and it is enough to use bits [33:0]
- * saving the dram offset.
- * Therefore, save the high part physical address bit[1:0]
- * of Tx/Rx buffer address as dma_dram_offset bit[33:32].
- */
case A_I2CM_DMA_TX_ADDR_HI:
if (!aic->has_dma64) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n",
@@ -766,8 +810,6 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset,
bus->regs[R_I2CM_DMA_TX_ADDR_HI] = FIELD_EX32(value,
I2CM_DMA_TX_ADDR_HI,
ADDR_HI);
- bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 32, 32,
- extract32(value, 0, 2));
break;
case A_I2CM_DMA_RX_ADDR_HI:
if (!aic->has_dma64) {
@@ -778,8 +820,6 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset,
bus->regs[R_I2CM_DMA_RX_ADDR_HI] = FIELD_EX32(value,
I2CM_DMA_RX_ADDR_HI,
ADDR_HI);
- bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 32, 32,
- extract32(value, 0, 2));
break;
case A_I2CS_DMA_TX_ADDR_HI:
qemu_log_mask(LOG_UNIMP,
@@ -795,8 +835,6 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset,
bus->regs[R_I2CS_DMA_RX_ADDR_HI] = FIELD_EX32(value,
I2CS_DMA_RX_ADDR_HI,
ADDR_HI);
- bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 32, 32,
- extract32(value, 0, 2));
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
@@ -887,9 +925,6 @@ static void aspeed_i2c_bus_old_write(AspeedI2CBus *bus, hwaddr offset,
qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__);
break;
}
-
- bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 0, 32,
- value & 0x3ffffffc);
break;
case A_I2CD_DMA_LEN:
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 4/8] hw/i2c/aspeed_i2c: Fix DMA moving data into incorrect address
@ 2026-02-03 2:08 ` Jamin Lin via qemu development
0 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via qemu development @ 2026-02-03 2:08 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
In the previous design, the I2C model updated dma_dram_offset only when
firmware programmed the RX/TX DMA buffer address registers. The firmware
used to rewrite these registers before issuing each DMA command.
The firmware driver behavior has changed to program the DMA address
registers only once during I2C initialization. As a result, the I2C model
no longer refreshes dma_dram_offset, causing DMA to move data into an
incorrect DRAM address.
Fix this by introducing helper functions to update dma_dram_offset from
the DMA address registers, and invoke them right before handling TX/RX
DMA operations. This guarantees DMA always uses the correct buffer
address even if the registers are programmed only once.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Fixes: c400c38854017eeccda63115814eba4c3ef2b51f ("hw/i2c/aspeed: Introduce a new dma_dram_offset attribute in AspeedI2Cbus")
---
hw/i2c/aspeed_i2c.c | 87 +++++++++++++++++++++++++++++++--------------
1 file changed, 61 insertions(+), 26 deletions(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 1ee73a8f5e..fb3d6a5600 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -116,8 +116,6 @@ static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus *bus, hwaddr offset,
value = -1;
break;
}
-
- value = extract64(bus->dma_dram_offset, 0, 32);
break;
case A_I2CD_DMA_LEN:
if (!aic->has_dma) {
@@ -221,6 +219,64 @@ static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus)
return SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, TX_STATE);
}
+/*
+ * The AST2700 support the maximum DRAM size is 8 GB.
+ * The DRAM offset range is from 0x0_0000_0000 to
+ * 0x1_FFFF_FFFF and it is enough to use bits [33:0]
+ * saving the dram offset.
+ * Therefore, save the high part physical address bit[1:0]
+ * of Tx/Rx buffer address as dma_dram_offset bit[33:32].
+ */
+static void aspeed_i2c_set_tx_dma_dram_offset(AspeedI2CBus *bus)
+{
+ AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
+ uint32_t value;
+
+ assert(aic->has_dma);
+
+ if (aspeed_i2c_is_new_mode(bus->controller)) {
+ value = bus->regs[R_I2CM_DMA_TX_ADDR];
+ bus->dma_dram_offset =
+ deposit64(bus->dma_dram_offset, 0, 32,
+ FIELD_EX32(value, I2CM_DMA_TX_ADDR, ADDR));
+ if (!aic->has_dma64) {
+ value = bus->regs[R_I2CM_DMA_TX_ADDR_HI];
+ bus->dma_dram_offset =
+ deposit64(bus->dma_dram_offset, 32, 32,
+ extract32(value, 0, 2));
+ }
+ } else {
+ value = bus->regs[R_I2CD_DMA_ADDR];
+ bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 0, 32,
+ value & 0x3ffffffc);
+ }
+}
+
+static void aspeed_i2c_set_rx_dma_dram_offset(AspeedI2CBus *bus)
+{
+ AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
+ uint32_t value;
+
+ assert(aic->has_dma);
+
+ if (aspeed_i2c_is_new_mode(bus->controller)) {
+ value = bus->regs[R_I2CM_DMA_RX_ADDR];
+ bus->dma_dram_offset =
+ deposit64(bus->dma_dram_offset, 0, 32,
+ FIELD_EX32(value, I2CM_DMA_RX_ADDR, ADDR));
+ if (!aic->has_dma64) {
+ value = bus->regs[R_I2CM_DMA_RX_ADDR_HI];
+ bus->dma_dram_offset =
+ deposit64(bus->dma_dram_offset, 32, 32,
+ extract32(value, 0, 2));
+ }
+ } else {
+ value = bus->regs[R_I2CD_DMA_ADDR];
+ bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 0, 32,
+ value & 0x3ffffffc);
+ }
+}
+
static int aspeed_i2c_dma_read(AspeedI2CBus *bus, uint8_t *data)
{
MemTxResult result;
@@ -270,6 +326,7 @@ static int aspeed_i2c_bus_send(AspeedI2CBus *bus)
if (aspeed_i2c_is_new_mode(bus->controller)) {
ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 0);
}
+ aspeed_i2c_set_tx_dma_dram_offset(bus);
while (bus->regs[reg_dma_len]) {
uint8_t data;
ret = aspeed_i2c_dma_read(bus, &data);
@@ -335,6 +392,7 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus)
ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, 0);
}
+ aspeed_i2c_set_rx_dma_dram_offset(bus);
while (bus->regs[reg_dma_len]) {
MemTxResult result;
@@ -401,6 +459,7 @@ static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus)
} else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) {
uint8_t data;
+ aspeed_i2c_set_tx_dma_dram_offset(bus);
aspeed_i2c_dma_read(bus, &data);
return data;
} else {
@@ -657,16 +716,10 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset,
case A_I2CM_DMA_TX_ADDR:
bus->regs[R_I2CM_DMA_TX_ADDR] = FIELD_EX32(value, I2CM_DMA_TX_ADDR,
ADDR);
- bus->dma_dram_offset =
- deposit64(bus->dma_dram_offset, 0, 32,
- FIELD_EX32(value, I2CM_DMA_TX_ADDR, ADDR));
break;
case A_I2CM_DMA_RX_ADDR:
bus->regs[R_I2CM_DMA_RX_ADDR] = FIELD_EX32(value, I2CM_DMA_RX_ADDR,
ADDR);
- bus->dma_dram_offset =
- deposit64(bus->dma_dram_offset, 0, 32,
- FIELD_EX32(value, I2CM_DMA_RX_ADDR, ADDR));
break;
case A_I2CM_DMA_LEN:
w1t = FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T) ||
@@ -748,15 +801,6 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset,
qemu_log_mask(LOG_UNIMP, "%s: Slave mode DMA TX is not implemented\n",
__func__);
break;
-
- /*
- * The AST2700 support the maximum DRAM size is 8 GB.
- * The DRAM offset range is from 0x0_0000_0000 to
- * 0x1_FFFF_FFFF and it is enough to use bits [33:0]
- * saving the dram offset.
- * Therefore, save the high part physical address bit[1:0]
- * of Tx/Rx buffer address as dma_dram_offset bit[33:32].
- */
case A_I2CM_DMA_TX_ADDR_HI:
if (!aic->has_dma64) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n",
@@ -766,8 +810,6 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset,
bus->regs[R_I2CM_DMA_TX_ADDR_HI] = FIELD_EX32(value,
I2CM_DMA_TX_ADDR_HI,
ADDR_HI);
- bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 32, 32,
- extract32(value, 0, 2));
break;
case A_I2CM_DMA_RX_ADDR_HI:
if (!aic->has_dma64) {
@@ -778,8 +820,6 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset,
bus->regs[R_I2CM_DMA_RX_ADDR_HI] = FIELD_EX32(value,
I2CM_DMA_RX_ADDR_HI,
ADDR_HI);
- bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 32, 32,
- extract32(value, 0, 2));
break;
case A_I2CS_DMA_TX_ADDR_HI:
qemu_log_mask(LOG_UNIMP,
@@ -795,8 +835,6 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset,
bus->regs[R_I2CS_DMA_RX_ADDR_HI] = FIELD_EX32(value,
I2CS_DMA_RX_ADDR_HI,
ADDR_HI);
- bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 32, 32,
- extract32(value, 0, 2));
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
@@ -887,9 +925,6 @@ static void aspeed_i2c_bus_old_write(AspeedI2CBus *bus, hwaddr offset,
qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__);
break;
}
-
- bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 0, 32,
- value & 0x3ffffffc);
break;
case A_I2CD_DMA_LEN:
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 5/8] tests/functional/aarch64/test_aspeed_ast2700: Enable PCIe2 DTS status for AST2700 tests
2026-02-03 2:08 ` Jamin Lin via qemu development
@ 2026-02-03 2:08 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via @ 2026-02-03 2:08 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
PCIe2 is disabled by default starting from SDK v10.00.
Add a helper function to stop U-Boot autoboot and update the device
tree at runtime, setting the PCIe2 node status to "okay" before
booting Linux. This allows the AST2700 functional test to verify
the PCIe2 root complex behavior correctly.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
.../functional/aarch64/test_aspeed_ast2700.py | 18 ++++++++++++++++--
.../aarch64/test_aspeed_ast2700fc.py | 18 ++++++++++++++++--
2 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/tests/functional/aarch64/test_aspeed_ast2700.py b/tests/functional/aarch64/test_aspeed_ast2700.py
index 0ced1a2502..1f1b5749f4 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700.py
@@ -9,7 +9,7 @@
import os
from qemu_test import QemuSystemTest, Asset
-from qemu_test import wait_for_console_pattern
+from qemu_test import wait_for_console_pattern, exec_command
from qemu_test import exec_command_and_wait_for_pattern
@@ -37,9 +37,23 @@ def verify_vbootrom_firmware_flow(self):
wait_for_console_pattern(self, 'done')
wait_for_console_pattern(self, 'Jumping to BL31 (Trusted Firmware-A)')
+ def enable_ast2700_pcie2(self):
+ wait_for_console_pattern(self, 'Hit any key to stop autoboot')
+ exec_command_and_wait_for_pattern(self, '\012', '=>')
+ exec_command_and_wait_for_pattern(self,
+ 'cp 100420000 403000000 900000', '=>')
+ exec_command_and_wait_for_pattern(self,
+ 'bootm start 403000000', '=>')
+ exec_command_and_wait_for_pattern(self, 'bootm loados', '=>')
+ exec_command_and_wait_for_pattern(self, 'bootm ramdisk', '=>')
+ exec_command_and_wait_for_pattern(self, 'bootm prep', '=>')
+ exec_command_and_wait_for_pattern(self,
+ 'fdt set /soc@14000000/pcie@140d0000 status "okay"', '=>')
+ exec_command(self, 'bootm go')
+
def verify_openbmc_boot_start(self):
wait_for_console_pattern(self, 'U-Boot 2023.10')
- wait_for_console_pattern(self, '## Loading kernel from FIT Image')
+ self.enable_ast2700_pcie2()
wait_for_console_pattern(self, 'Linux version ')
def verify_openbmc_boot_and_login(self, name):
diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/functional/aarch64/test_aspeed_ast2700fc.py
index 8dbc8f234f..a1d8046f58 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700fc.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py
@@ -9,7 +9,7 @@
import os
from qemu_test import QemuSystemTest, Asset
-from qemu_test import wait_for_console_pattern
+from qemu_test import wait_for_console_pattern, exec_command
from qemu_test import exec_command_and_wait_for_pattern
@@ -27,9 +27,23 @@ def do_test_aarch64_aspeed_sdk_start(self, image):
self.vm.launch()
+ def enable_ast2700_pcie2(self):
+ wait_for_console_pattern(self, 'Hit any key to stop autoboot')
+ exec_command_and_wait_for_pattern(self, '\012', '=>')
+ exec_command_and_wait_for_pattern(self,
+ 'cp 100420000 403000000 900000', '=>')
+ exec_command_and_wait_for_pattern(self,
+ 'bootm start 403000000', '=>')
+ exec_command_and_wait_for_pattern(self, 'bootm loados', '=>')
+ exec_command_and_wait_for_pattern(self, 'bootm ramdisk', '=>')
+ exec_command_and_wait_for_pattern(self, 'bootm prep', '=>')
+ exec_command_and_wait_for_pattern(self,
+ 'fdt set /soc@14000000/pcie@140d0000 status "okay"', '=>')
+ exec_command(self, 'bootm go')
+
def verify_openbmc_boot_and_login(self, name):
wait_for_console_pattern(self, 'U-Boot 2023.10')
- wait_for_console_pattern(self, '## Loading kernel from FIT Image')
+ self.enable_ast2700_pcie2()
wait_for_console_pattern(self, 'Starting kernel ...')
wait_for_console_pattern(self, f'{name} login:')
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 5/8] tests/functional/aarch64/test_aspeed_ast2700: Enable PCIe2 DTS status for AST2700 tests
@ 2026-02-03 2:08 ` Jamin Lin via qemu development
0 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via qemu development @ 2026-02-03 2:08 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
PCIe2 is disabled by default starting from SDK v10.00.
Add a helper function to stop U-Boot autoboot and update the device
tree at runtime, setting the PCIe2 node status to "okay" before
booting Linux. This allows the AST2700 functional test to verify
the PCIe2 root complex behavior correctly.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
.../functional/aarch64/test_aspeed_ast2700.py | 18 ++++++++++++++++--
.../aarch64/test_aspeed_ast2700fc.py | 18 ++++++++++++++++--
2 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/tests/functional/aarch64/test_aspeed_ast2700.py b/tests/functional/aarch64/test_aspeed_ast2700.py
index 0ced1a2502..1f1b5749f4 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700.py
@@ -9,7 +9,7 @@
import os
from qemu_test import QemuSystemTest, Asset
-from qemu_test import wait_for_console_pattern
+from qemu_test import wait_for_console_pattern, exec_command
from qemu_test import exec_command_and_wait_for_pattern
@@ -37,9 +37,23 @@ def verify_vbootrom_firmware_flow(self):
wait_for_console_pattern(self, 'done')
wait_for_console_pattern(self, 'Jumping to BL31 (Trusted Firmware-A)')
+ def enable_ast2700_pcie2(self):
+ wait_for_console_pattern(self, 'Hit any key to stop autoboot')
+ exec_command_and_wait_for_pattern(self, '\012', '=>')
+ exec_command_and_wait_for_pattern(self,
+ 'cp 100420000 403000000 900000', '=>')
+ exec_command_and_wait_for_pattern(self,
+ 'bootm start 403000000', '=>')
+ exec_command_and_wait_for_pattern(self, 'bootm loados', '=>')
+ exec_command_and_wait_for_pattern(self, 'bootm ramdisk', '=>')
+ exec_command_and_wait_for_pattern(self, 'bootm prep', '=>')
+ exec_command_and_wait_for_pattern(self,
+ 'fdt set /soc@14000000/pcie@140d0000 status "okay"', '=>')
+ exec_command(self, 'bootm go')
+
def verify_openbmc_boot_start(self):
wait_for_console_pattern(self, 'U-Boot 2023.10')
- wait_for_console_pattern(self, '## Loading kernel from FIT Image')
+ self.enable_ast2700_pcie2()
wait_for_console_pattern(self, 'Linux version ')
def verify_openbmc_boot_and_login(self, name):
diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/functional/aarch64/test_aspeed_ast2700fc.py
index 8dbc8f234f..a1d8046f58 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700fc.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py
@@ -9,7 +9,7 @@
import os
from qemu_test import QemuSystemTest, Asset
-from qemu_test import wait_for_console_pattern
+from qemu_test import wait_for_console_pattern, exec_command
from qemu_test import exec_command_and_wait_for_pattern
@@ -27,9 +27,23 @@ def do_test_aarch64_aspeed_sdk_start(self, image):
self.vm.launch()
+ def enable_ast2700_pcie2(self):
+ wait_for_console_pattern(self, 'Hit any key to stop autoboot')
+ exec_command_and_wait_for_pattern(self, '\012', '=>')
+ exec_command_and_wait_for_pattern(self,
+ 'cp 100420000 403000000 900000', '=>')
+ exec_command_and_wait_for_pattern(self,
+ 'bootm start 403000000', '=>')
+ exec_command_and_wait_for_pattern(self, 'bootm loados', '=>')
+ exec_command_and_wait_for_pattern(self, 'bootm ramdisk', '=>')
+ exec_command_and_wait_for_pattern(self, 'bootm prep', '=>')
+ exec_command_and_wait_for_pattern(self,
+ 'fdt set /soc@14000000/pcie@140d0000 status "okay"', '=>')
+ exec_command(self, 'bootm go')
+
def verify_openbmc_boot_and_login(self, name):
wait_for_console_pattern(self, 'U-Boot 2023.10')
- wait_for_console_pattern(self, '## Loading kernel from FIT Image')
+ self.enable_ast2700_pcie2()
wait_for_console_pattern(self, 'Starting kernel ...')
wait_for_console_pattern(self, f'{name} login:')
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 6/8] tests/functional/aarch64/test_aspeed_ast2700: Update test ASPEED SDK v11.00 for A1
2026-02-03 2:08 ` Jamin Lin via qemu development
@ 2026-02-03 2:08 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via @ 2026-02-03 2:08 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
.../functional/aarch64/test_aspeed_ast2700.py | 60 +++++++++----------
1 file changed, 29 insertions(+), 31 deletions(-)
diff --git a/tests/functional/aarch64/test_aspeed_ast2700.py b/tests/functional/aarch64/test_aspeed_ast2700.py
index 1f1b5749f4..828ea1ca53 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700.py
@@ -26,15 +26,23 @@ def do_test_aarch64_aspeed_sdk_start(self, image):
self.vm.launch()
def verify_vbootrom_firmware_flow(self):
- wait_for_console_pattern(self, 'Found valid FIT image')
- wait_for_console_pattern(self, '[uboot] loading')
- wait_for_console_pattern(self, 'done')
- wait_for_console_pattern(self, '[fdt] loading')
- wait_for_console_pattern(self, 'done')
- wait_for_console_pattern(self, '[tee] loading')
- wait_for_console_pattern(self, 'done')
- wait_for_console_pattern(self, '[atf] loading')
- wait_for_console_pattern(self, 'done')
+ wait_for_console_pattern(self, 'Found valid caliptra flash image')
+ wait_for_console_pattern(self, 'Check flash image checksum')
+ wait_for_console_pattern(self, 'pass')
+ wait_for_console_pattern(self, 'Read abb header')
+ wait_for_console_pattern(self, 'pass')
+ wait_for_console_pattern(self, 'Read soc manifest')
+ wait_for_console_pattern(self, 'pass')
+ wait_for_console_pattern(self, 'Load atf image')
+ wait_for_console_pattern(self, 'pass')
+ wait_for_console_pattern(self, 'Load optee image')
+ wait_for_console_pattern(self, 'pass')
+ wait_for_console_pattern(self, 'Load uboot image')
+ wait_for_console_pattern(self, 'pass')
+ wait_for_console_pattern(self, 'Load ssp image')
+ wait_for_console_pattern(self, 'pass')
+ wait_for_console_pattern(self, 'Load tsp image')
+ wait_for_console_pattern(self, 'pass')
wait_for_console_pattern(self, 'Jumping to BL31 (Trusted Firmware-A)')
def enable_ast2700_pcie2(self):
@@ -63,9 +71,9 @@ def verify_openbmc_boot_and_login(self, name):
exec_command_and_wait_for_pattern(self, 'root', 'Password:')
exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~#')
- ASSET_SDK_V908_AST2700A1 = Asset(
- 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.08/ast2700-default-obmc.tar.gz',
- 'eac3dc409b7ea3cd4b03d4792d3cebd469792ad893cb51e1d15f0fc20bd1e2cd')
+ ASSET_SDK_V1100_AST2700A1 = Asset(
+ 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-a1-obmc.tar.gz',
+ 'd5ceed511cd0dfefbb102fff2d731159e0472948a28066dc0d90bcd54be76525')
def do_ast2700_i2c_test(self):
exec_command_and_wait_for_pattern(self,
@@ -93,19 +101,10 @@ def do_ast2700_pcie_test(self):
def start_ast2700_test(self, name):
num_cpu = 4
- uboot_size = os.path.getsize(self.scratch_file(name,
- 'u-boot-nodtb.bin'))
- uboot_dtb_load_addr = hex(0x400000000 + uboot_size)
-
load_images_list = [
{
'addr': '0x400000000',
- 'file': self.scratch_file(name,
- 'u-boot-nodtb.bin')
- },
- {
- 'addr': str(uboot_dtb_load_addr),
- 'file': self.scratch_file(name, 'u-boot.dtb')
+ 'file': self.scratch_file(name, 'u-boot.bin')
},
{
'addr': '0x430000000',
@@ -113,8 +112,7 @@ def start_ast2700_test(self, name):
},
{
'addr': '0x430080000',
- 'file': self.scratch_file(name, 'optee',
- 'tee-raw.bin')
+ 'file': self.scratch_file(name, 'optee', 'tee-raw.bin')
}
]
@@ -137,26 +135,26 @@ def start_ast2700_test_vbootrom(self, name):
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
- def test_aarch64_ast2700a1_evb_sdk_v09_08(self):
+ def test_aarch64_ast2700a1_evb_sdk_v11_00(self):
self.set_machine('ast2700a1-evb')
self.require_netdev('user')
- self.archive_extract(self.ASSET_SDK_V908_AST2700A1)
+ self.archive_extract(self.ASSET_SDK_V1100_AST2700A1)
self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2')
self.vm.add_args('-netdev', 'user,id=net1')
- self.start_ast2700_test('ast2700-default')
- self.verify_openbmc_boot_and_login('ast2700-default')
+ self.start_ast2700_test('ast2700-a1')
+ self.verify_openbmc_boot_and_login('ast2700-a1')
self.do_ast2700_i2c_test()
self.do_ast2700_pcie_test()
- def test_aarch64_ast2700a1_evb_sdk_vbootrom_v09_08(self):
+ def test_aarch64_ast2700a1_evb_sdk_vbootrom_v11_00(self):
self.set_machine('ast2700a1-evb')
self.require_netdev('user')
- self.archive_extract(self.ASSET_SDK_V908_AST2700A1)
+ self.archive_extract(self.ASSET_SDK_V1100_AST2700A1)
self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2')
self.vm.add_args('-netdev', 'user,id=net1')
- self.start_ast2700_test_vbootrom('ast2700-default')
+ self.start_ast2700_test_vbootrom('ast2700-a1')
self.verify_vbootrom_firmware_flow()
self.verify_openbmc_boot_start()
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 6/8] tests/functional/aarch64/test_aspeed_ast2700: Update test ASPEED SDK v11.00 for A1
@ 2026-02-03 2:08 ` Jamin Lin via qemu development
0 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via qemu development @ 2026-02-03 2:08 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
.../functional/aarch64/test_aspeed_ast2700.py | 60 +++++++++----------
1 file changed, 29 insertions(+), 31 deletions(-)
diff --git a/tests/functional/aarch64/test_aspeed_ast2700.py b/tests/functional/aarch64/test_aspeed_ast2700.py
index 1f1b5749f4..828ea1ca53 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700.py
@@ -26,15 +26,23 @@ def do_test_aarch64_aspeed_sdk_start(self, image):
self.vm.launch()
def verify_vbootrom_firmware_flow(self):
- wait_for_console_pattern(self, 'Found valid FIT image')
- wait_for_console_pattern(self, '[uboot] loading')
- wait_for_console_pattern(self, 'done')
- wait_for_console_pattern(self, '[fdt] loading')
- wait_for_console_pattern(self, 'done')
- wait_for_console_pattern(self, '[tee] loading')
- wait_for_console_pattern(self, 'done')
- wait_for_console_pattern(self, '[atf] loading')
- wait_for_console_pattern(self, 'done')
+ wait_for_console_pattern(self, 'Found valid caliptra flash image')
+ wait_for_console_pattern(self, 'Check flash image checksum')
+ wait_for_console_pattern(self, 'pass')
+ wait_for_console_pattern(self, 'Read abb header')
+ wait_for_console_pattern(self, 'pass')
+ wait_for_console_pattern(self, 'Read soc manifest')
+ wait_for_console_pattern(self, 'pass')
+ wait_for_console_pattern(self, 'Load atf image')
+ wait_for_console_pattern(self, 'pass')
+ wait_for_console_pattern(self, 'Load optee image')
+ wait_for_console_pattern(self, 'pass')
+ wait_for_console_pattern(self, 'Load uboot image')
+ wait_for_console_pattern(self, 'pass')
+ wait_for_console_pattern(self, 'Load ssp image')
+ wait_for_console_pattern(self, 'pass')
+ wait_for_console_pattern(self, 'Load tsp image')
+ wait_for_console_pattern(self, 'pass')
wait_for_console_pattern(self, 'Jumping to BL31 (Trusted Firmware-A)')
def enable_ast2700_pcie2(self):
@@ -63,9 +71,9 @@ def verify_openbmc_boot_and_login(self, name):
exec_command_and_wait_for_pattern(self, 'root', 'Password:')
exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~#')
- ASSET_SDK_V908_AST2700A1 = Asset(
- 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.08/ast2700-default-obmc.tar.gz',
- 'eac3dc409b7ea3cd4b03d4792d3cebd469792ad893cb51e1d15f0fc20bd1e2cd')
+ ASSET_SDK_V1100_AST2700A1 = Asset(
+ 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-a1-obmc.tar.gz',
+ 'd5ceed511cd0dfefbb102fff2d731159e0472948a28066dc0d90bcd54be76525')
def do_ast2700_i2c_test(self):
exec_command_and_wait_for_pattern(self,
@@ -93,19 +101,10 @@ def do_ast2700_pcie_test(self):
def start_ast2700_test(self, name):
num_cpu = 4
- uboot_size = os.path.getsize(self.scratch_file(name,
- 'u-boot-nodtb.bin'))
- uboot_dtb_load_addr = hex(0x400000000 + uboot_size)
-
load_images_list = [
{
'addr': '0x400000000',
- 'file': self.scratch_file(name,
- 'u-boot-nodtb.bin')
- },
- {
- 'addr': str(uboot_dtb_load_addr),
- 'file': self.scratch_file(name, 'u-boot.dtb')
+ 'file': self.scratch_file(name, 'u-boot.bin')
},
{
'addr': '0x430000000',
@@ -113,8 +112,7 @@ def start_ast2700_test(self, name):
},
{
'addr': '0x430080000',
- 'file': self.scratch_file(name, 'optee',
- 'tee-raw.bin')
+ 'file': self.scratch_file(name, 'optee', 'tee-raw.bin')
}
]
@@ -137,26 +135,26 @@ def start_ast2700_test_vbootrom(self, name):
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
- def test_aarch64_ast2700a1_evb_sdk_v09_08(self):
+ def test_aarch64_ast2700a1_evb_sdk_v11_00(self):
self.set_machine('ast2700a1-evb')
self.require_netdev('user')
- self.archive_extract(self.ASSET_SDK_V908_AST2700A1)
+ self.archive_extract(self.ASSET_SDK_V1100_AST2700A1)
self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2')
self.vm.add_args('-netdev', 'user,id=net1')
- self.start_ast2700_test('ast2700-default')
- self.verify_openbmc_boot_and_login('ast2700-default')
+ self.start_ast2700_test('ast2700-a1')
+ self.verify_openbmc_boot_and_login('ast2700-a1')
self.do_ast2700_i2c_test()
self.do_ast2700_pcie_test()
- def test_aarch64_ast2700a1_evb_sdk_vbootrom_v09_08(self):
+ def test_aarch64_ast2700a1_evb_sdk_vbootrom_v11_00(self):
self.set_machine('ast2700a1-evb')
self.require_netdev('user')
- self.archive_extract(self.ASSET_SDK_V908_AST2700A1)
+ self.archive_extract(self.ASSET_SDK_V1100_AST2700A1)
self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2')
self.vm.add_args('-netdev', 'user,id=net1')
- self.start_ast2700_test_vbootrom('ast2700-default')
+ self.start_ast2700_test_vbootrom('ast2700-a1')
self.verify_vbootrom_firmware_flow()
self.verify_openbmc_boot_start()
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 7/8] tests/functional/aarch64/test_aspeed_ast2700fc: Update test ASPEED SDK v11.00 for A1
2026-02-03 2:08 ` Jamin Lin via qemu development
@ 2026-02-03 2:08 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via @ 2026-02-03 2:08 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
.../aarch64/test_aspeed_ast2700fc.py | 36 +++++++------------
1 file changed, 13 insertions(+), 23 deletions(-)
diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/functional/aarch64/test_aspeed_ast2700fc.py
index a1d8046f58..47e56dcfc5 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700fc.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py
@@ -61,9 +61,9 @@ def load_ast2700fc_coprocessor(self, name):
self.vm.add_args('-device',
f'loader,file={file},cpu-num={cpu_num}')
- ASSET_SDK_V908_AST2700 = Asset(
- 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.08/ast2700-default-obmc.tar.gz',
- 'eac3dc409b7ea3cd4b03d4792d3cebd469792ad893cb51e1d15f0fc20bd1e2cd')
+ ASSET_SDK_V1100_AST2700 = Asset(
+ 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-a1-obmc.tar.gz',
+ 'd5ceed511cd0dfefbb102fff2d731159e0472948a28066dc0d90bcd54be76525')
def do_ast2700_i2c_test(self):
exec_command_and_wait_for_pattern(self,
@@ -113,19 +113,10 @@ def do_ast2700fc_tsp_test(self):
def start_ast2700fc_test(self, name):
ca35_core = 4
- uboot_size = os.path.getsize(self.scratch_file(name,
- 'u-boot-nodtb.bin'))
- uboot_dtb_load_addr = hex(0x400000000 + uboot_size)
-
load_images_list = [
{
'addr': '0x400000000',
- 'file': self.scratch_file(name,
- 'u-boot-nodtb.bin')
- },
- {
- 'addr': str(uboot_dtb_load_addr),
- 'file': self.scratch_file(name, 'u-boot.dtb')
+ 'file': self.scratch_file(name, 'u-boot.bin')
},
{
'addr': '0x430000000',
@@ -133,8 +124,7 @@ def start_ast2700fc_test(self, name):
},
{
'addr': '0x430080000',
- 'file': self.scratch_file(name, 'optee',
- 'tee-raw.bin')
+ 'file': self.scratch_file(name, 'optee', 'tee-raw.bin')
}
]
@@ -158,24 +148,24 @@ def start_ast2700fc_test_vbootrom(self, name):
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
- def test_aarch64_ast2700fc_sdk_v09_08(self):
+ def test_aarch64_ast2700fc_sdk_v11_00(self):
self.set_machine('ast2700fc')
self.require_netdev('user')
- self.archive_extract(self.ASSET_SDK_V908_AST2700)
- self.start_ast2700fc_test('ast2700-default')
- self.verify_openbmc_boot_and_login('ast2700-default')
+ self.archive_extract(self.ASSET_SDK_V1100_AST2700)
+ self.start_ast2700fc_test('ast2700-a1')
+ self.verify_openbmc_boot_and_login('ast2700-a1')
self.do_ast2700_i2c_test()
self.do_ast2700_pcie_test()
self.do_ast2700fc_ssp_test()
self.do_ast2700fc_tsp_test()
- def test_aarch64_ast2700fc_sdk_vbootrom_v09_08(self):
+ def test_aarch64_ast2700fc_sdk_vbootrom_v11_00(self):
self.set_machine('ast2700fc')
- self.archive_extract(self.ASSET_SDK_V908_AST2700)
- self.start_ast2700fc_test_vbootrom('ast2700-default')
- self.verify_openbmc_boot_and_login('ast2700-default')
+ self.archive_extract(self.ASSET_SDK_V1100_AST2700)
+ self.start_ast2700fc_test_vbootrom('ast2700-a1')
+ self.verify_openbmc_boot_and_login('ast2700-a1')
self.do_ast2700fc_ssp_test()
self.do_ast2700fc_tsp_test()
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 7/8] tests/functional/aarch64/test_aspeed_ast2700fc: Update test ASPEED SDK v11.00 for A1
@ 2026-02-03 2:08 ` Jamin Lin via qemu development
0 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via qemu development @ 2026-02-03 2:08 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
.../aarch64/test_aspeed_ast2700fc.py | 36 +++++++------------
1 file changed, 13 insertions(+), 23 deletions(-)
diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/functional/aarch64/test_aspeed_ast2700fc.py
index a1d8046f58..47e56dcfc5 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700fc.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py
@@ -61,9 +61,9 @@ def load_ast2700fc_coprocessor(self, name):
self.vm.add_args('-device',
f'loader,file={file},cpu-num={cpu_num}')
- ASSET_SDK_V908_AST2700 = Asset(
- 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.08/ast2700-default-obmc.tar.gz',
- 'eac3dc409b7ea3cd4b03d4792d3cebd469792ad893cb51e1d15f0fc20bd1e2cd')
+ ASSET_SDK_V1100_AST2700 = Asset(
+ 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-a1-obmc.tar.gz',
+ 'd5ceed511cd0dfefbb102fff2d731159e0472948a28066dc0d90bcd54be76525')
def do_ast2700_i2c_test(self):
exec_command_and_wait_for_pattern(self,
@@ -113,19 +113,10 @@ def do_ast2700fc_tsp_test(self):
def start_ast2700fc_test(self, name):
ca35_core = 4
- uboot_size = os.path.getsize(self.scratch_file(name,
- 'u-boot-nodtb.bin'))
- uboot_dtb_load_addr = hex(0x400000000 + uboot_size)
-
load_images_list = [
{
'addr': '0x400000000',
- 'file': self.scratch_file(name,
- 'u-boot-nodtb.bin')
- },
- {
- 'addr': str(uboot_dtb_load_addr),
- 'file': self.scratch_file(name, 'u-boot.dtb')
+ 'file': self.scratch_file(name, 'u-boot.bin')
},
{
'addr': '0x430000000',
@@ -133,8 +124,7 @@ def start_ast2700fc_test(self, name):
},
{
'addr': '0x430080000',
- 'file': self.scratch_file(name, 'optee',
- 'tee-raw.bin')
+ 'file': self.scratch_file(name, 'optee', 'tee-raw.bin')
}
]
@@ -158,24 +148,24 @@ def start_ast2700fc_test_vbootrom(self, name):
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
- def test_aarch64_ast2700fc_sdk_v09_08(self):
+ def test_aarch64_ast2700fc_sdk_v11_00(self):
self.set_machine('ast2700fc')
self.require_netdev('user')
- self.archive_extract(self.ASSET_SDK_V908_AST2700)
- self.start_ast2700fc_test('ast2700-default')
- self.verify_openbmc_boot_and_login('ast2700-default')
+ self.archive_extract(self.ASSET_SDK_V1100_AST2700)
+ self.start_ast2700fc_test('ast2700-a1')
+ self.verify_openbmc_boot_and_login('ast2700-a1')
self.do_ast2700_i2c_test()
self.do_ast2700_pcie_test()
self.do_ast2700fc_ssp_test()
self.do_ast2700fc_tsp_test()
- def test_aarch64_ast2700fc_sdk_vbootrom_v09_08(self):
+ def test_aarch64_ast2700fc_sdk_vbootrom_v11_00(self):
self.set_machine('ast2700fc')
- self.archive_extract(self.ASSET_SDK_V908_AST2700)
- self.start_ast2700fc_test_vbootrom('ast2700-default')
- self.verify_openbmc_boot_and_login('ast2700-default')
+ self.archive_extract(self.ASSET_SDK_V1100_AST2700)
+ self.start_ast2700fc_test_vbootrom('ast2700-a1')
+ self.verify_openbmc_boot_and_login('ast2700-a1')
self.do_ast2700fc_ssp_test()
self.do_ast2700fc_tsp_test()
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 8/8] docs/system/arm/aspeed: Load raw U-Boot image in AST2700 boot example
2026-02-03 2:08 ` Jamin Lin via qemu development
@ 2026-02-03 2:08 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via @ 2026-02-03 2:08 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Recent SDK versions no longer provide a U-Boot FIT image, and U-Boot is
now built as a single raw binary. Update the documentation to load the
raw u-boot.bin image directly.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
docs/system/arm/aspeed.rst | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 97e14b7d33..d0054a7dbb 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -350,11 +350,9 @@ corresponds to the BL31 image load address.
.. code-block:: bash
IMGDIR=ast2700-default
- UBOOT_SIZE=$(stat --format=%s -L ${IMGDIR}/u-boot-nodtb.bin)
$ qemu-system-aarch64 -M ast2700-evb \
- -device loader,force-raw=on,addr=0x400000000,file=${IMGDIR}/u-boot-nodtb.bin \
- -device loader,force-raw=on,addr=$((0x400000000 + ${UBOOT_SIZE})),file=${IMGDIR}/u-boot.dtb \
+ -device loader,force-raw=on,addr=0x400000000,file=${IMGDIR}/u-boot.bin \
-device loader,force-raw=on,addr=0x430000000,file=${IMGDIR}/bl31.bin \
-device loader,force-raw=on,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin \
-device loader,cpu-num=0,addr=0x430000000 \
@@ -409,11 +407,9 @@ Steps to boot the AST2700fc machine:
.. code-block:: bash
IMGDIR=ast2700-default
- UBOOT_SIZE=$(stat --format=%s -L ${IMGDIR}/u-boot-nodtb.bin)
$ qemu-system-aarch64 -M ast2700fc \
- -device loader,force-raw=on,addr=0x400000000,file=${IMGDIR}/u-boot-nodtb.bin \
- -device loader,force-raw=on,addr=$((0x400000000 + ${UBOOT_SIZE})),file=${IMGDIR}/u-boot.dtb \
+ -device loader,force-raw=on,addr=0x400000000,file=${IMGDIR}/u-boot.bin \
-device loader,force-raw=on,addr=0x430000000,file=${IMGDIR}/bl31.bin \
-device loader,force-raw=on,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin \
-device loader,cpu-num=0,addr=0x430000000 \
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 8/8] docs/system/arm/aspeed: Load raw U-Boot image in AST2700 boot example
@ 2026-02-03 2:08 ` Jamin Lin via qemu development
0 siblings, 0 replies; 20+ messages in thread
From: Jamin Lin via qemu development @ 2026-02-03 2:08 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Recent SDK versions no longer provide a U-Boot FIT image, and U-Boot is
now built as a single raw binary. Update the documentation to load the
raw u-boot.bin image directly.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
docs/system/arm/aspeed.rst | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 97e14b7d33..d0054a7dbb 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -350,11 +350,9 @@ corresponds to the BL31 image load address.
.. code-block:: bash
IMGDIR=ast2700-default
- UBOOT_SIZE=$(stat --format=%s -L ${IMGDIR}/u-boot-nodtb.bin)
$ qemu-system-aarch64 -M ast2700-evb \
- -device loader,force-raw=on,addr=0x400000000,file=${IMGDIR}/u-boot-nodtb.bin \
- -device loader,force-raw=on,addr=$((0x400000000 + ${UBOOT_SIZE})),file=${IMGDIR}/u-boot.dtb \
+ -device loader,force-raw=on,addr=0x400000000,file=${IMGDIR}/u-boot.bin \
-device loader,force-raw=on,addr=0x430000000,file=${IMGDIR}/bl31.bin \
-device loader,force-raw=on,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin \
-device loader,cpu-num=0,addr=0x430000000 \
@@ -409,11 +407,9 @@ Steps to boot the AST2700fc machine:
.. code-block:: bash
IMGDIR=ast2700-default
- UBOOT_SIZE=$(stat --format=%s -L ${IMGDIR}/u-boot-nodtb.bin)
$ qemu-system-aarch64 -M ast2700fc \
- -device loader,force-raw=on,addr=0x400000000,file=${IMGDIR}/u-boot-nodtb.bin \
- -device loader,force-raw=on,addr=$((0x400000000 + ${UBOOT_SIZE})),file=${IMGDIR}/u-boot.dtb \
+ -device loader,force-raw=on,addr=0x400000000,file=${IMGDIR}/u-boot.bin \
-device loader,force-raw=on,addr=0x430000000,file=${IMGDIR}/bl31.bin \
-device loader,force-raw=on,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin \
-device loader,cpu-num=0,addr=0x430000000 \
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread