[PATCH net-next v3 0/3] net: stmmac: eic7700: fix EIC7700 eth1 RX sampling timing

[PATCH net-next v3 0/3] net: stmmac: eic7700: fix EIC7700 eth1 RX sampling timing

[lizhi2]

From: Zhi Li <lizhi2@eswincomputing.com>

v2 -> v3:
  - Update eswin,eic7700-eth.yaml:
    - Extend rx-internal-delay-ps and tx-internal-delay-ps range
      from 0-2400 to 0-2540 to match the full 7-bit hardware delay
      field (127 * 20 ps).
    - Add "multipleOf: 20" constraint to reflect the 20 ps hardware
      step size.
    - Make rx-internal-delay-ps and tx-internal-delay-ps optional.
      A well-designed board should not require internal delay tuning.
    - Remove rx-internal-delay-ps and tx-internal-delay-ps from the
      example to avoid encouraging blind copy into board DTs.

  - Update dwmac-eic7700.c:
    - Treat rx-internal-delay-ps and tx-internal-delay-ps as optional
      DT properties.
    - Apply delay configuration only when properties are present.
    - Keep TX/RX delay registers cleared by default to ensure a
      deterministic state when no delay is specified.

  - Describe Ethernet configuration for the HiFive Premier P550 board:
    - Add GMAC controller nodes for the HiFive Premier P550 board
      to describe the on-board Ethernet configuration.

      The Ethernet controller depends on clock, reset, pinctrl
      and HSP subsystem providers which are currently under
      upstream review. These dependent nodes will be submitted
      separately once the corresponding drivers are merged.

      Due to these missing dependencies, dt-binding-check may
      report warnings or failures for this series.

  - No functional changes to RX clock inversion logic.

  - Link to v2:
    https://lore.kernel.org/lkml/20260209094628.886-1-lizhi2@eswincomputing.com/

  - This series is based on the EIC7700 clock support series:
    https://lore.kernel.org/all/20260210095008.726-1-dongxuyang@eswincomputing.com/
    The clock series is currently under review.

v1 -> v2:
  - Update eswin,eic7700-eth.yaml:
    - Drop the vendor-specific properties eswin,rx-clk-invert and
      eswin,tx-clk-invert.
    - Introduce a distinct compatible string
      "eswin,eic7700-qos-eth-clk-inversion" to describe MAC instances that
      require internal RGMII clock inversion.
      This models the SoC-specific hardware difference directly via the
      compatible string and avoids per-board configuration properties.
    - Change rx-internal-delay-ps and tx-internal-delay-ps from enum to
      minimum/maximum to reflect the actual delay range (0-2400 ps)
    - Add reference to High-Speed Subsystem documentation in eswin,hsp-sp-csr
      description. The HSP CSR block is described in Chapter 10
      ("High-Speed Interface") of the EIC7700X SoC Technical Reference Manual,
      Part 4 (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf):
      https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases

  - Update dwmac-eic7700.c:
    - Remove handling of eswin,rx-clk-invert and eswin,tx-clk-invert
      properties.
    - Select RX clock inversion based on the new
      "eswin,eic7700-qos-eth-clk-inversion" compatible string, using
      match data to apply the required configuration for affected MAC
      instances (eth1).

  - Link to v1:
    https://lore.kernel.org/lkml/20260109080601.1262-1-lizhi2@eswincomputing.com/

Zhi Li (3):
  dt-bindings: ethernet: eswin: add clock sampling control
  net: stmmac: eic7700: enable clocks before syscon access and correct
    RX sampling timing
  riscv: dts: eswin: eic7700-hifive-premier-p550: enable Ethernet
    controller

 .../bindings/net/eswin,eic7700-eth.yaml       |  75 ++++++--
 .../dts/eswin/eic7700-hifive-premier-p550.dts |  50 +++++
 arch/riscv/boot/dts/eswin/eic7700.dtsi        |  54 ++++++
 .../ethernet/stmicro/stmmac/dwmac-eic7700.c   | 180 +++++++++++++-----
 4 files changed, 300 insertions(+), 59 deletions(-)

-- 
2.25.1

[PATCH net-next v3 0/3] net: stmmac: eic7700: fix EIC7700 eth1 RX sampling timing

[lizhi2]

From: Zhi Li <lizhi2@eswincomputing.com>

v2 -> v3:
  - Update eswin,eic7700-eth.yaml:
    - Extend rx-internal-delay-ps and tx-internal-delay-ps range
      from 0-2400 to 0-2540 to match the full 7-bit hardware delay
      field (127 * 20 ps).
    - Add "multipleOf: 20" constraint to reflect the 20 ps hardware
      step size.
    - Make rx-internal-delay-ps and tx-internal-delay-ps optional.
      A well-designed board should not require internal delay tuning.
    - Remove rx-internal-delay-ps and tx-internal-delay-ps from the
      example to avoid encouraging blind copy into board DTs.

  - Update dwmac-eic7700.c:
    - Treat rx-internal-delay-ps and tx-internal-delay-ps as optional
      DT properties.
    - Apply delay configuration only when properties are present.
    - Keep TX/RX delay registers cleared by default to ensure a
      deterministic state when no delay is specified.

  - Describe Ethernet configuration for the HiFive Premier P550 board:
    - Add GMAC controller nodes for the HiFive Premier P550 board
      to describe the on-board Ethernet configuration.

      The Ethernet controller depends on clock, reset, pinctrl
      and HSP subsystem providers which are currently under
      upstream review. These dependent nodes will be submitted
      separately once the corresponding drivers are merged.

      Due to these missing dependencies, dt-binding-check may
      report warnings or failures for this series.

  - No functional changes to RX clock inversion logic.

  - Link to v2:
    https://lore.kernel.org/lkml/20260209094628.886-1-lizhi2@eswincomputing.com/

  - This series is based on the EIC7700 clock support series:
    https://lore.kernel.org/all/20260210095008.726-1-dongxuyang@eswincomputing.com/
    The clock series is currently under review.

v1 -> v2:
  - Update eswin,eic7700-eth.yaml:
    - Drop the vendor-specific properties eswin,rx-clk-invert and
      eswin,tx-clk-invert.
    - Introduce a distinct compatible string
      "eswin,eic7700-qos-eth-clk-inversion" to describe MAC instances that
      require internal RGMII clock inversion.
      This models the SoC-specific hardware difference directly via the
      compatible string and avoids per-board configuration properties.
    - Change rx-internal-delay-ps and tx-internal-delay-ps from enum to
      minimum/maximum to reflect the actual delay range (0-2400 ps)
    - Add reference to High-Speed Subsystem documentation in eswin,hsp-sp-csr
      description. The HSP CSR block is described in Chapter 10
      ("High-Speed Interface") of the EIC7700X SoC Technical Reference Manual,
      Part 4 (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf):
      https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases

  - Update dwmac-eic7700.c:
    - Remove handling of eswin,rx-clk-invert and eswin,tx-clk-invert
      properties.
    - Select RX clock inversion based on the new
      "eswin,eic7700-qos-eth-clk-inversion" compatible string, using
      match data to apply the required configuration for affected MAC
      instances (eth1).

  - Link to v1:
    https://lore.kernel.org/lkml/20260109080601.1262-1-lizhi2@eswincomputing.com/

Zhi Li (3):
  dt-bindings: ethernet: eswin: add clock sampling control
  net: stmmac: eic7700: enable clocks before syscon access and correct
    RX sampling timing
  riscv: dts: eswin: eic7700-hifive-premier-p550: enable Ethernet
    controller

 .../bindings/net/eswin,eic7700-eth.yaml       |  75 ++++++--
 .../dts/eswin/eic7700-hifive-premier-p550.dts |  50 +++++
 arch/riscv/boot/dts/eswin/eic7700.dtsi        |  54 ++++++
 .../ethernet/stmicro/stmmac/dwmac-eic7700.c   | 180 +++++++++++++-----
 4 files changed, 300 insertions(+), 59 deletions(-)

-- 
2.25.1


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[PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[lizhi2]

From: Zhi Li <lizhi2@eswincomputing.com>

The second Ethernet controller (eth1) on the EIC7700 SoC may experience
RX data sampling issues at high speed due to EIC7700-specific receive
clock to data skew at the MAC input.

On the EIC7700 SoC, the second Ethernet controller (eth1) requires
inversion of the internal RGMII receive clock in order to meet RX data
sampling timing at high speed.

Describe this SoC-specific difference by introducing a distinct compatible
string for MAC instances that require internal clock inversion, allowing the
driver to select the appropriate configuration without relying on per-board
vendor-specific properties.

The rx-internal-delay-ps and tx-internal-delay-ps properties now use
minimum and maximum constraints to reflect the actual hardware delay
range (0-2540 ps) applied in 20 ps steps. This relaxes the binding
validation compared to the previous enum-based definition and avoids
regressions for existing DTBs while keeping the same hardware limits.

Treat the RX/TX internal delay properties as optional, board-specific
tuning knobs and remove them from the example to avoid encouraging
their use.

In addition, the binding now includes additional background information
about the HSP CSR registers accessed by the MAC. The TXD and RXD delay
control registers are included so the driver can explicitly clear any
residual configuration left by the bootloader. Background reference for
the High-Speed Subsystem and HSP CSR block is available in Chapter 10
("High-Speed Interface") of the EIC7700X SoC Technical Reference Manual,
Part 4 (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf):
https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases

There are currently no in-tree users of the EIC7700 Ethernet driver, so
these changes are safe.

Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC")
Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
---
 .../bindings/net/eswin,eic7700-eth.yaml       | 75 +++++++++++++++----
 1 file changed, 59 insertions(+), 16 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
index 91e8cd1db67b..22d1cecea07e 100644
--- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
+++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
@@ -20,6 +20,7 @@ select:
       contains:
         enum:
           - eswin,eic7700-qos-eth
+          - eswin,eic7700-qos-eth-clk-inversion
   required:
     - compatible
 
@@ -28,9 +29,13 @@ allOf:
 
 properties:
   compatible:
-    items:
-      - const: eswin,eic7700-qos-eth
-      - const: snps,dwmac-5.20
+    oneOf:
+      - items:
+          - const: eswin,eic7700-qos-eth
+          - const: snps,dwmac-5.20
+      - items:
+          - const: eswin,eic7700-qos-eth-clk-inversion
+          - const: snps,dwmac-5.20
 
   reg:
     maxItems: 1
@@ -63,16 +68,29 @@ properties:
       - const: stmmaceth
 
   rx-internal-delay-ps:
-    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
+    minimum: 0
+    maximum: 2540
+    multipleOf: 20
 
   tx-internal-delay-ps:
-    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
+    minimum: 0
+    maximum: 2540
+    multipleOf: 20
 
   eswin,hsp-sp-csr:
     description:
       HSP CSR is to control and get status of different high-speed peripherals
       (such as Ethernet, USB, SATA, etc.) via register, which can tune
       board-level's parameters of PHY, etc.
+
+      Additional background information about the High-Speed Subsystem
+      and the HSP CSR block is available in Chapter 10 ("High-Speed Interface")
+      of the EIC7700X SoC Technical Reference Manual, Part 4
+      (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf). The manual is
+      publicly available at
+      https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
+
+      This reference is provided for background information only.
     $ref: /schemas/types.yaml#/definitions/phandle-array
     items:
       - items:
@@ -81,7 +99,9 @@ properties:
                          or external clock selection
           - description: Offset of AXI clock controller Low-Power request
                          register
+          - description: Offset of register controlling TXD delay
           - description: Offset of register controlling TX/RX clock delay
+          - description: Offset of register controlling RXD delay
 
 required:
   - compatible
@@ -93,8 +113,6 @@ required:
   - phy-mode
   - resets
   - reset-names
-  - rx-internal-delay-ps
-  - tx-internal-delay-ps
   - eswin,hsp-sp-csr
 
 unevaluatedProperties: false
@@ -104,24 +122,49 @@ examples:
     ethernet@50400000 {
         compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20";
         reg = <0x50400000 0x10000>;
+        interrupt-parent = <&plic>;
+        interrupts = <61>;
+        interrupt-names = "macirq";
         clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>,
                 <&d0_clock 193>;
         clock-names = "axi", "cfg", "stmmaceth", "tx";
+        resets = <&reset 95>;
+        reset-names = "stmmaceth";
+        eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x114 0x118 0x11c>;
+        phy-handle = <&gmac0_phy0>;
+        phy-mode = "rgmii-id";
+        snps,aal;
+        snps,fixed-burst;
+        snps,tso;
+        snps,axi-config = <&stmmac_axi_setup_gmac0>;
+
+        stmmac_axi_setup_gmac0: stmmac-axi-config {
+            snps,blen = <0 0 0 0 16 8 4>;
+            snps,rd_osr_lmt = <2>;
+            snps,wr_osr_lmt = <2>;
+        };
+    };
+
+    ethernet@50410000 {
+        compatible = "eswin,eic7700-qos-eth-clk-inversion", "snps,dwmac-5.20";
+        reg = <0x50410000 0x10000>;
         interrupt-parent = <&plic>;
-        interrupts = <61>;
+        interrupts = <70>;
         interrupt-names = "macirq";
-        phy-mode = "rgmii-id";
-        phy-handle = <&phy0>;
-        resets = <&reset 95>;
+        clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>,
+                <&d0_clock 194>;
+        clock-names = "axi", "cfg", "stmmaceth", "tx";
+        resets = <&reset 94>;
         reset-names = "stmmaceth";
-        rx-internal-delay-ps = <200>;
-        tx-internal-delay-ps = <200>;
-        eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118>;
-        snps,axi-config = <&stmmac_axi_setup>;
+        eswin,hsp-sp-csr = <&hsp_sp_csr 0x200 0x208 0x214 0x218 0x21c>;
+        phy-handle = <&gmac1_phy0>;
+        phy-mode = "rgmii-id";
         snps,aal;
         snps,fixed-burst;
         snps,tso;
-        stmmac_axi_setup: stmmac-axi-config {
+        snps,axi-config = <&stmmac_axi_setup_gmac1>;
+
+        stmmac_axi_setup_gmac1: stmmac-axi-config {
             snps,blen = <0 0 0 0 16 8 4>;
             snps,rd_osr_lmt = <2>;
             snps,wr_osr_lmt = <2>;
-- 
2.25.1

[PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[lizhi2]

From: Zhi Li <lizhi2@eswincomputing.com>

The second Ethernet controller (eth1) on the EIC7700 SoC may experience
RX data sampling issues at high speed due to EIC7700-specific receive
clock to data skew at the MAC input.

On the EIC7700 SoC, the second Ethernet controller (eth1) requires
inversion of the internal RGMII receive clock in order to meet RX data
sampling timing at high speed.

Describe this SoC-specific difference by introducing a distinct compatible
string for MAC instances that require internal clock inversion, allowing the
driver to select the appropriate configuration without relying on per-board
vendor-specific properties.

The rx-internal-delay-ps and tx-internal-delay-ps properties now use
minimum and maximum constraints to reflect the actual hardware delay
range (0-2540 ps) applied in 20 ps steps. This relaxes the binding
validation compared to the previous enum-based definition and avoids
regressions for existing DTBs while keeping the same hardware limits.

Treat the RX/TX internal delay properties as optional, board-specific
tuning knobs and remove them from the example to avoid encouraging
their use.

In addition, the binding now includes additional background information
about the HSP CSR registers accessed by the MAC. The TXD and RXD delay
control registers are included so the driver can explicitly clear any
residual configuration left by the bootloader. Background reference for
the High-Speed Subsystem and HSP CSR block is available in Chapter 10
("High-Speed Interface") of the EIC7700X SoC Technical Reference Manual,
Part 4 (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf):
https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases

There are currently no in-tree users of the EIC7700 Ethernet driver, so
these changes are safe.

Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC")
Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
---
 .../bindings/net/eswin,eic7700-eth.yaml       | 75 +++++++++++++++----
 1 file changed, 59 insertions(+), 16 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
index 91e8cd1db67b..22d1cecea07e 100644
--- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
+++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
@@ -20,6 +20,7 @@ select:
       contains:
         enum:
           - eswin,eic7700-qos-eth
+          - eswin,eic7700-qos-eth-clk-inversion
   required:
     - compatible
 
@@ -28,9 +29,13 @@ allOf:
 
 properties:
   compatible:
-    items:
-      - const: eswin,eic7700-qos-eth
-      - const: snps,dwmac-5.20
+    oneOf:
+      - items:
+          - const: eswin,eic7700-qos-eth
+          - const: snps,dwmac-5.20
+      - items:
+          - const: eswin,eic7700-qos-eth-clk-inversion
+          - const: snps,dwmac-5.20
 
   reg:
     maxItems: 1
@@ -63,16 +68,29 @@ properties:
       - const: stmmaceth
 
   rx-internal-delay-ps:
-    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
+    minimum: 0
+    maximum: 2540
+    multipleOf: 20
 
   tx-internal-delay-ps:
-    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
+    minimum: 0
+    maximum: 2540
+    multipleOf: 20
 
   eswin,hsp-sp-csr:
     description:
       HSP CSR is to control and get status of different high-speed peripherals
       (such as Ethernet, USB, SATA, etc.) via register, which can tune
       board-level's parameters of PHY, etc.
+
+      Additional background information about the High-Speed Subsystem
+      and the HSP CSR block is available in Chapter 10 ("High-Speed Interface")
+      of the EIC7700X SoC Technical Reference Manual, Part 4
+      (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf). The manual is
+      publicly available at
+      https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
+
+      This reference is provided for background information only.
     $ref: /schemas/types.yaml#/definitions/phandle-array
     items:
       - items:
@@ -81,7 +99,9 @@ properties:
                          or external clock selection
           - description: Offset of AXI clock controller Low-Power request
                          register
+          - description: Offset of register controlling TXD delay
           - description: Offset of register controlling TX/RX clock delay
+          - description: Offset of register controlling RXD delay
 
 required:
   - compatible
@@ -93,8 +113,6 @@ required:
   - phy-mode
   - resets
   - reset-names
-  - rx-internal-delay-ps
-  - tx-internal-delay-ps
   - eswin,hsp-sp-csr
 
 unevaluatedProperties: false
@@ -104,24 +122,49 @@ examples:
     ethernet@50400000 {
         compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20";
         reg = <0x50400000 0x10000>;
+        interrupt-parent = <&plic>;
+        interrupts = <61>;
+        interrupt-names = "macirq";
         clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>,
                 <&d0_clock 193>;
         clock-names = "axi", "cfg", "stmmaceth", "tx";
+        resets = <&reset 95>;
+        reset-names = "stmmaceth";
+        eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x114 0x118 0x11c>;
+        phy-handle = <&gmac0_phy0>;
+        phy-mode = "rgmii-id";
+        snps,aal;
+        snps,fixed-burst;
+        snps,tso;
+        snps,axi-config = <&stmmac_axi_setup_gmac0>;
+
+        stmmac_axi_setup_gmac0: stmmac-axi-config {
+            snps,blen = <0 0 0 0 16 8 4>;
+            snps,rd_osr_lmt = <2>;
+            snps,wr_osr_lmt = <2>;
+        };
+    };
+
+    ethernet@50410000 {
+        compatible = "eswin,eic7700-qos-eth-clk-inversion", "snps,dwmac-5.20";
+        reg = <0x50410000 0x10000>;
         interrupt-parent = <&plic>;
-        interrupts = <61>;
+        interrupts = <70>;
         interrupt-names = "macirq";
-        phy-mode = "rgmii-id";
-        phy-handle = <&phy0>;
-        resets = <&reset 95>;
+        clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>,
+                <&d0_clock 194>;
+        clock-names = "axi", "cfg", "stmmaceth", "tx";
+        resets = <&reset 94>;
         reset-names = "stmmaceth";
-        rx-internal-delay-ps = <200>;
-        tx-internal-delay-ps = <200>;
-        eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118>;
-        snps,axi-config = <&stmmac_axi_setup>;
+        eswin,hsp-sp-csr = <&hsp_sp_csr 0x200 0x208 0x214 0x218 0x21c>;
+        phy-handle = <&gmac1_phy0>;
+        phy-mode = "rgmii-id";
         snps,aal;
         snps,fixed-burst;
         snps,tso;
-        stmmac_axi_setup: stmmac-axi-config {
+        snps,axi-config = <&stmmac_axi_setup_gmac1>;
+
+        stmmac_axi_setup_gmac1: stmmac-axi-config {
             snps,blen = <0 0 0 0 16 8 4>;
             snps,rd_osr_lmt = <2>;
             snps,wr_osr_lmt = <2>;
-- 
2.25.1


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Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[Jakub Kicinski]

On Tue,  3 Mar 2026 14:16:37 +0800 lizhi2@eswincomputing.com wrote:
> There are currently no in-tree users of the EIC7700 Ethernet driver, so
> these changes are safe.

What do you mean by this sentence? The commit under Fixes was part of
Linux v6.19 already.

> Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC")

Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[Jakub Kicinski]

On Tue,  3 Mar 2026 14:16:37 +0800 lizhi2@eswincomputing.com wrote:
> There are currently no in-tree users of the EIC7700 Ethernet driver, so
> these changes are safe.

What do you mean by this sentence? The commit under Fixes was part of
Linux v6.19 already.

> Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC")

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Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[Conor Dooley]

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On Tue, Mar 03, 2026 at 04:38:46PM -0800, Jakub Kicinski wrote:
> On Tue,  3 Mar 2026 14:16:37 +0800 lizhi2@eswincomputing.com wrote:
> > There are currently no in-tree users of the EIC7700 Ethernet driver, so
> > these changes are safe.
> 
> What do you mean by this sentence? The commit under Fixes was part of
> Linux v6.19 already.

The "funny" thing is that caring about users doesn't even really matter
on the devicetree patch, except for this hunk:
|@@ -81,7 +99,9 @@ properties:
|                          or external clock selection
|           - description: Offset of AXI clock controller Low-Power request
|                          register
|+          - description: Offset of register controlling TXD delay
|           - description: Offset of register controlling TX/RX clock delay
|+          - description: Offset of register controlling RXD delay
| 
| required:
|   - compatible
And it only matters here because an item is injected mid-list. If this
was moved to the end with the RXD delay, the **dt-binding** changes
don't have issues with safety. I've not looked at whether there are
knock-on concerns about users in the driver or whatever yet, but from a
binding POV only that hunk can break something that currently works.

> > Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC")

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Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[Conor Dooley]

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On Tue, Mar 03, 2026 at 04:38:46PM -0800, Jakub Kicinski wrote:
> On Tue,  3 Mar 2026 14:16:37 +0800 lizhi2@eswincomputing.com wrote:
> > There are currently no in-tree users of the EIC7700 Ethernet driver, so
> > these changes are safe.
> 
> What do you mean by this sentence? The commit under Fixes was part of
> Linux v6.19 already.

The "funny" thing is that caring about users doesn't even really matter
on the devicetree patch, except for this hunk:
|@@ -81,7 +99,9 @@ properties:
|                          or external clock selection
|           - description: Offset of AXI clock controller Low-Power request
|                          register
|+          - description: Offset of register controlling TXD delay
|           - description: Offset of register controlling TX/RX clock delay
|+          - description: Offset of register controlling RXD delay
| 
| required:
|   - compatible
And it only matters here because an item is injected mid-list. If this
was moved to the end with the RXD delay, the **dt-binding** changes
don't have issues with safety. I've not looked at whether there are
knock-on concerns about users in the driver or whatever yet, but from a
binding POV only that hunk can break something that currently works.

> > Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC")

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Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[Bo Gan]

Hi All,

On 3/3/26 16:47, Conor Dooley wrote:
> On Tue, Mar 03, 2026 at 04:38:46PM -0800, Jakub Kicinski wrote:
>> On Tue,  3 Mar 2026 14:16:37 +0800 lizhi2@eswincomputing.com wrote:
>>> There are currently no in-tree users of the EIC7700 Ethernet driver, so
>>> these changes are safe.
>>
>> What do you mean by this sentence? The commit under Fixes was part of
>> Linux v6.19 already.
> 
> The "funny" thing is that caring about users doesn't even really matter
> on the devicetree patch, except for this hunk:
> |@@ -81,7 +99,9 @@ properties:
> |                          or external clock selection
> |           - description: Offset of AXI clock controller Low-Power request
> |                          register
> |+          - description: Offset of register controlling TXD delay
> |           - description: Offset of register controlling TX/RX clock delay
> |+          - description: Offset of register controlling RXD delay
> |
> | required:
> |   - compatible
> And it only matters here because an item is injected mid-list. If this
> was moved to the end with the RXD delay, the **dt-binding** changes
> don't have issues with safety. I've not looked at whether there are
> knock-on concerns about users in the driver or whatever yet, but from a
> binding POV only that hunk can break something that currently works.

This was already discussed here in v1:
https://lore.kernel.org/lkml/e7183ae1-8b8b-4e77-9f4e-3bc1b4b63556@lunn.ch/

The device-tree is not checked in yet by ESWIN folks, so there's currently
no user of the dt-binding. No need to worry about backward compat.

> 
>>> Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC")

Bo

Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[Bo Gan]

Hi All,

On 3/3/26 16:47, Conor Dooley wrote:
> On Tue, Mar 03, 2026 at 04:38:46PM -0800, Jakub Kicinski wrote:
>> On Tue,  3 Mar 2026 14:16:37 +0800 lizhi2@eswincomputing.com wrote:
>>> There are currently no in-tree users of the EIC7700 Ethernet driver, so
>>> these changes are safe.
>>
>> What do you mean by this sentence? The commit under Fixes was part of
>> Linux v6.19 already.
> 
> The "funny" thing is that caring about users doesn't even really matter
> on the devicetree patch, except for this hunk:
> |@@ -81,7 +99,9 @@ properties:
> |                          or external clock selection
> |           - description: Offset of AXI clock controller Low-Power request
> |                          register
> |+          - description: Offset of register controlling TXD delay
> |           - description: Offset of register controlling TX/RX clock delay
> |+          - description: Offset of register controlling RXD delay
> |
> | required:
> |   - compatible
> And it only matters here because an item is injected mid-list. If this
> was moved to the end with the RXD delay, the **dt-binding** changes
> don't have issues with safety. I've not looked at whether there are
> knock-on concerns about users in the driver or whatever yet, but from a
> binding POV only that hunk can break something that currently works.

This was already discussed here in v1:
https://lore.kernel.org/lkml/e7183ae1-8b8b-4e77-9f4e-3bc1b4b63556@lunn.ch/

The device-tree is not checked in yet by ESWIN folks, so there's currently
no user of the dt-binding. No need to worry about backward compat.

> 
>>> Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC")

Bo


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Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[Krzysztof Kozlowski]

On Tue, Mar 03, 2026 at 05:23:18PM -0800, Bo Gan wrote:
> Hi All,
> 
> On 3/3/26 16:47, Conor Dooley wrote:
> > On Tue, Mar 03, 2026 at 04:38:46PM -0800, Jakub Kicinski wrote:
> > > On Tue,  3 Mar 2026 14:16:37 +0800 lizhi2@eswincomputing.com wrote:
> > > > There are currently no in-tree users of the EIC7700 Ethernet driver, so
> > > > these changes are safe.
> > > 
> > > What do you mean by this sentence? The commit under Fixes was part of
> > > Linux v6.19 already.
> > 
> > The "funny" thing is that caring about users doesn't even really matter
> > on the devicetree patch, except for this hunk:
> > |@@ -81,7 +99,9 @@ properties:
> > |                          or external clock selection
> > |           - description: Offset of AXI clock controller Low-Power request
> > |                          register
> > |+          - description: Offset of register controlling TXD delay
> > |           - description: Offset of register controlling TX/RX clock delay
> > |+          - description: Offset of register controlling RXD delay
> > |
> > | required:
> > |   - compatible
> > And it only matters here because an item is injected mid-list. If this
> > was moved to the end with the RXD delay, the **dt-binding** changes
> > don't have issues with safety. I've not looked at whether there are
> > knock-on concerns about users in the driver or whatever yet, but from a
> > binding POV only that hunk can break something that currently works.
> 
> This was already discussed here in v1:
> https://lore.kernel.org/lkml/e7183ae1-8b8b-4e77-9f4e-3bc1b4b63556@lunn.ch/
> 
> The device-tree is not checked in yet by ESWIN folks, so there's currently
> no user of the dt-binding. No need to worry about backward compat.

Of course there is user of this binding, for example ESWIN. Or many
other vendors using it out of tree. You documented ABI.

Best regards,
Krzysztof

Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[Krzysztof Kozlowski]

On Tue, Mar 03, 2026 at 05:23:18PM -0800, Bo Gan wrote:
> Hi All,
> 
> On 3/3/26 16:47, Conor Dooley wrote:
> > On Tue, Mar 03, 2026 at 04:38:46PM -0800, Jakub Kicinski wrote:
> > > On Tue,  3 Mar 2026 14:16:37 +0800 lizhi2@eswincomputing.com wrote:
> > > > There are currently no in-tree users of the EIC7700 Ethernet driver, so
> > > > these changes are safe.
> > > 
> > > What do you mean by this sentence? The commit under Fixes was part of
> > > Linux v6.19 already.
> > 
> > The "funny" thing is that caring about users doesn't even really matter
> > on the devicetree patch, except for this hunk:
> > |@@ -81,7 +99,9 @@ properties:
> > |                          or external clock selection
> > |           - description: Offset of AXI clock controller Low-Power request
> > |                          register
> > |+          - description: Offset of register controlling TXD delay
> > |           - description: Offset of register controlling TX/RX clock delay
> > |+          - description: Offset of register controlling RXD delay
> > |
> > | required:
> > |   - compatible
> > And it only matters here because an item is injected mid-list. If this
> > was moved to the end with the RXD delay, the **dt-binding** changes
> > don't have issues with safety. I've not looked at whether there are
> > knock-on concerns about users in the driver or whatever yet, but from a
> > binding POV only that hunk can break something that currently works.
> 
> This was already discussed here in v1:
> https://lore.kernel.org/lkml/e7183ae1-8b8b-4e77-9f4e-3bc1b4b63556@lunn.ch/
> 
> The device-tree is not checked in yet by ESWIN folks, so there's currently
> no user of the dt-binding. No need to worry about backward compat.

Of course there is user of this binding, for example ESWIN. Or many
other vendors using it out of tree. You documented ABI.

Best regards,
Krzysztof


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Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[Conor Dooley]

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On Tue, Mar 03, 2026 at 05:23:18PM -0800, Bo Gan wrote:
> Hi All,
> 
> On 3/3/26 16:47, Conor Dooley wrote:
> > On Tue, Mar 03, 2026 at 04:38:46PM -0800, Jakub Kicinski wrote:
> > > On Tue,  3 Mar 2026 14:16:37 +0800 lizhi2@eswincomputing.com wrote:
> > > > There are currently no in-tree users of the EIC7700 Ethernet driver, so
> > > > these changes are safe.
> > > 
> > > What do you mean by this sentence? The commit under Fixes was part of
> > > Linux v6.19 already.
> > 
> > The "funny" thing is that caring about users doesn't even really matter
> > on the devicetree patch, except for this hunk:
> > |@@ -81,7 +99,9 @@ properties:
> > |                          or external clock selection
> > |           - description: Offset of AXI clock controller Low-Power request
> > |                          register
> > |+          - description: Offset of register controlling TXD delay
> > |           - description: Offset of register controlling TX/RX clock delay
> > |+          - description: Offset of register controlling RXD delay
> > |
> > | required:
> > |   - compatible
> > And it only matters here because an item is injected mid-list. If this
> > was moved to the end with the RXD delay, the **dt-binding** changes
> > don't have issues with safety. I've not looked at whether there are
> > knock-on concerns about users in the driver or whatever yet, but from a
> > binding POV only that hunk can break something that currently works.
> 
> This was already discussed here in v1:
> https://lore.kernel.org/lkml/e7183ae1-8b8b-4e77-9f4e-3bc1b4b63556@lunn.ch/
> 
> The device-tree is not checked in yet by ESWIN folks, so there's currently
> no user of the dt-binding. No need to worry about backward compat.

The binding and driver exist, there doesn't need to be a dts in tree for
there to be potential users. If the break was important I might not
care, but this seems to be a gratuitous break, since the new items could
be added to the end of the list and compatibility maintained without
incurring any more difficulty for you.

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Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[Conor Dooley]

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On Tue, Mar 03, 2026 at 05:23:18PM -0800, Bo Gan wrote:
> Hi All,
> 
> On 3/3/26 16:47, Conor Dooley wrote:
> > On Tue, Mar 03, 2026 at 04:38:46PM -0800, Jakub Kicinski wrote:
> > > On Tue,  3 Mar 2026 14:16:37 +0800 lizhi2@eswincomputing.com wrote:
> > > > There are currently no in-tree users of the EIC7700 Ethernet driver, so
> > > > these changes are safe.
> > > 
> > > What do you mean by this sentence? The commit under Fixes was part of
> > > Linux v6.19 already.
> > 
> > The "funny" thing is that caring about users doesn't even really matter
> > on the devicetree patch, except for this hunk:
> > |@@ -81,7 +99,9 @@ properties:
> > |                          or external clock selection
> > |           - description: Offset of AXI clock controller Low-Power request
> > |                          register
> > |+          - description: Offset of register controlling TXD delay
> > |           - description: Offset of register controlling TX/RX clock delay
> > |+          - description: Offset of register controlling RXD delay
> > |
> > | required:
> > |   - compatible
> > And it only matters here because an item is injected mid-list. If this
> > was moved to the end with the RXD delay, the **dt-binding** changes
> > don't have issues with safety. I've not looked at whether there are
> > knock-on concerns about users in the driver or whatever yet, but from a
> > binding POV only that hunk can break something that currently works.
> 
> This was already discussed here in v1:
> https://lore.kernel.org/lkml/e7183ae1-8b8b-4e77-9f4e-3bc1b4b63556@lunn.ch/
> 
> The device-tree is not checked in yet by ESWIN folks, so there's currently
> no user of the dt-binding. No need to worry about backward compat.

The binding and driver exist, there doesn't need to be a dts in tree for
there to be potential users. If the break was important I might not
care, but this seems to be a gratuitous break, since the new items could
be added to the end of the list and compatibility maintained without
incurring any more difficulty for you.

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Re: Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[李志]

> -----原始邮件-----
> 发件人: "Conor Dooley" <conor@kernel.org>
> 发送时间:2026-03-04 17:30:57 (星期三)
> 收件人: "Bo Gan" <ganboing@gmail.com>
> 抄送: "Jakub Kicinski" <kuba@kernel.org>, lizhi2@eswincomputing.com, devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, wens@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com
> 主题: Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control
> 
> On Tue, Mar 03, 2026 at 05:23:18PM -0800, Bo Gan wrote:
> > Hi All,
> > 
> > On 3/3/26 16:47, Conor Dooley wrote:
> > > On Tue, Mar 03, 2026 at 04:38:46PM -0800, Jakub Kicinski wrote:
> > > > On Tue,  3 Mar 2026 14:16:37 +0800 lizhi2@eswincomputing.com wrote:
> > > > > There are currently no in-tree users of the EIC7700 Ethernet driver, so
> > > > > these changes are safe.
> > > > 
> > > > What do you mean by this sentence? The commit under Fixes was part of
> > > > Linux v6.19 already.
> > > 
> > > The "funny" thing is that caring about users doesn't even really matter
> > > on the devicetree patch, except for this hunk:
> > > |@@ -81,7 +99,9 @@ properties:
> > > |                          or external clock selection
> > > |           - description: Offset of AXI clock controller Low-Power request
> > > |                          register
> > > |+          - description: Offset of register controlling TXD delay
> > > |           - description: Offset of register controlling TX/RX clock delay
> > > |+          - description: Offset of register controlling RXD delay
> > > |
> > > | required:
> > > |   - compatible
> > > And it only matters here because an item is injected mid-list. If this
> > > was moved to the end with the RXD delay, the **dt-binding** changes
> > > don't have issues with safety. I've not looked at whether there are
> > > knock-on concerns about users in the driver or whatever yet, but from a
> > > binding POV only that hunk can break something that currently works.
> > 
> > This was already discussed here in v1:
> > https://lore.kernel.org/lkml/e7183ae1-8b8b-4e77-9f4e-3bc1b4b63556@lunn.ch/
> > 
> > The device-tree is not checked in yet by ESWIN folks, so there's currently
> > no user of the dt-binding. No need to worry about backward compat.
> 
> The binding and driver exist, there doesn't need to be a dts in tree for
> there to be potential users. If the break was important I might not
> care, but this seems to be a gratuitous break, since the new items could
> be added to the end of the list and compatibility maintained without
> incurring any more difficulty for you.

Hi Conor and Krzysztof,

Thanks for the reviews.

- The next patch will fix the property order to avoid any breakage
  with existing DT bindings.

- Eth1 does have a timing issue in silicon, as discussed here:
  https://lore.kernel.org/lkml/32a1f814.2c79.19bfe173225.Coremail.linmin@eswincomputing.com/

  Based on this, and according to the advice from Andrew
  https://lore.kernel.org/lkml/59cec617-0189-4dc3-bc3f-6346155a62ae@lunn.ch/
  https://lore.kernel.org/lkml/bd202cfa-d6eb-4d0e-982d-b49795dd25f7@lunn.ch/
  adding a DT property is not a reasonable approach.
  
  In the next patch, I will improve the description/paragraph and properly
  document the timing issues.
  
  Do you think this is okay?

Best regards,
Zhi Li

Re: Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[李志]

> -----原始邮件-----
> 发件人: "Conor Dooley" <conor@kernel.org>
> 发送时间:2026-03-04 17:30:57 (星期三)
> 收件人: "Bo Gan" <ganboing@gmail.com>
> 抄送: "Jakub Kicinski" <kuba@kernel.org>, lizhi2@eswincomputing.com, devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, wens@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com
> 主题: Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control
> 
> On Tue, Mar 03, 2026 at 05:23:18PM -0800, Bo Gan wrote:
> > Hi All,
> > 
> > On 3/3/26 16:47, Conor Dooley wrote:
> > > On Tue, Mar 03, 2026 at 04:38:46PM -0800, Jakub Kicinski wrote:
> > > > On Tue,  3 Mar 2026 14:16:37 +0800 lizhi2@eswincomputing.com wrote:
> > > > > There are currently no in-tree users of the EIC7700 Ethernet driver, so
> > > > > these changes are safe.
> > > > 
> > > > What do you mean by this sentence? The commit under Fixes was part of
> > > > Linux v6.19 already.
> > > 
> > > The "funny" thing is that caring about users doesn't even really matter
> > > on the devicetree patch, except for this hunk:
> > > |@@ -81,7 +99,9 @@ properties:
> > > |                          or external clock selection
> > > |           - description: Offset of AXI clock controller Low-Power request
> > > |                          register
> > > |+          - description: Offset of register controlling TXD delay
> > > |           - description: Offset of register controlling TX/RX clock delay
> > > |+          - description: Offset of register controlling RXD delay
> > > |
> > > | required:
> > > |   - compatible
> > > And it only matters here because an item is injected mid-list. If this
> > > was moved to the end with the RXD delay, the **dt-binding** changes
> > > don't have issues with safety. I've not looked at whether there are
> > > knock-on concerns about users in the driver or whatever yet, but from a
> > > binding POV only that hunk can break something that currently works.
> > 
> > This was already discussed here in v1:
> > https://lore.kernel.org/lkml/e7183ae1-8b8b-4e77-9f4e-3bc1b4b63556@lunn.ch/
> > 
> > The device-tree is not checked in yet by ESWIN folks, so there's currently
> > no user of the dt-binding. No need to worry about backward compat.
> 
> The binding and driver exist, there doesn't need to be a dts in tree for
> there to be potential users. If the break was important I might not
> care, but this seems to be a gratuitous break, since the new items could
> be added to the end of the list and compatibility maintained without
> incurring any more difficulty for you.

Hi Conor and Krzysztof,

Thanks for the reviews.

- The next patch will fix the property order to avoid any breakage
  with existing DT bindings.

- Eth1 does have a timing issue in silicon, as discussed here:
  https://lore.kernel.org/lkml/32a1f814.2c79.19bfe173225.Coremail.linmin@eswincomputing.com/

  Based on this, and according to the advice from Andrew
  https://lore.kernel.org/lkml/59cec617-0189-4dc3-bc3f-6346155a62ae@lunn.ch/
  https://lore.kernel.org/lkml/bd202cfa-d6eb-4d0e-982d-b49795dd25f7@lunn.ch/
  adding a DT property is not a reasonable approach.
  
  In the next patch, I will improve the description/paragraph and properly
  document the timing issues.
  
  Do you think this is okay?

Best regards,
Zhi Li
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Re: Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[Conor Dooley]

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On Thu, Mar 05, 2026 at 10:52:38AM +0800, 李志 wrote:
> 
> 
> 
> > -----原始邮件-----
> > 发件人: "Conor Dooley" <conor@kernel.org>
> > 发送时间:2026-03-04 17:30:57 (星期三)
> > 收件人: "Bo Gan" <ganboing@gmail.com>
> > 抄送: "Jakub Kicinski" <kuba@kernel.org>, lizhi2@eswincomputing.com, devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, wens@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com
> > 主题: Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control
> > 
> > On Tue, Mar 03, 2026 at 05:23:18PM -0800, Bo Gan wrote:
> > > Hi All,
> > > 
> > > On 3/3/26 16:47, Conor Dooley wrote:
> > > > On Tue, Mar 03, 2026 at 04:38:46PM -0800, Jakub Kicinski wrote:
> > > > > On Tue,  3 Mar 2026 14:16:37 +0800 lizhi2@eswincomputing.com wrote:
> > > > > > There are currently no in-tree users of the EIC7700 Ethernet driver, so
> > > > > > these changes are safe.
> > > > > 
> > > > > What do you mean by this sentence? The commit under Fixes was part of
> > > > > Linux v6.19 already.
> > > > 
> > > > The "funny" thing is that caring about users doesn't even really matter
> > > > on the devicetree patch, except for this hunk:
> > > > |@@ -81,7 +99,9 @@ properties:
> > > > |                          or external clock selection
> > > > |           - description: Offset of AXI clock controller Low-Power request
> > > > |                          register
> > > > |+          - description: Offset of register controlling TXD delay
> > > > |           - description: Offset of register controlling TX/RX clock delay
> > > > |+          - description: Offset of register controlling RXD delay
> > > > |
> > > > | required:
> > > > |   - compatible
> > > > And it only matters here because an item is injected mid-list. If this
> > > > was moved to the end with the RXD delay, the **dt-binding** changes
> > > > don't have issues with safety. I've not looked at whether there are
> > > > knock-on concerns about users in the driver or whatever yet, but from a
> > > > binding POV only that hunk can break something that currently works.
> > > 
> > > This was already discussed here in v1:
> > > https://lore.kernel.org/lkml/e7183ae1-8b8b-4e77-9f4e-3bc1b4b63556@lunn.ch/
> > > 
> > > The device-tree is not checked in yet by ESWIN folks, so there's currently
> > > no user of the dt-binding. No need to worry about backward compat.
> > 
> > The binding and driver exist, there doesn't need to be a dts in tree for
> > there to be potential users. If the break was important I might not
> > care, but this seems to be a gratuitous break, since the new items could
> > be added to the end of the list and compatibility maintained without
> > incurring any more difficulty for you.
> 
> Hi Conor and Krzysztof,
> 
> Thanks for the reviews.
> 
> - The next patch will fix the property order to avoid any breakage
>   with existing DT bindings.

Good, thanks.

> - Eth1 does have a timing issue in silicon, as discussed here:
>   https://lore.kernel.org/lkml/32a1f814.2c79.19bfe173225.Coremail.linmin@eswincomputing.com/
> 
>   Based on this, and according to the advice from Andrew
>   https://lore.kernel.org/lkml/59cec617-0189-4dc3-bc3f-6346155a62ae@lunn.ch/
>   https://lore.kernel.org/lkml/bd202cfa-d6eb-4d0e-982d-b49795dd25f7@lunn.ch/
>   adding a DT property is not a reasonable approach.
>   
>   In the next patch, I will improve the description/paragraph and properly
>   document the timing issues.

I personally don't mind having two compatibles, but I might be more
clear about what device the new one refers to (so something like
s/clk-inversion/eth1/g). But Krzysztof was the one who objected to
having multiple compatibles, so it's worth waiting to see what he has to
say.

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Re: Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[Conor Dooley]

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On Thu, Mar 05, 2026 at 10:52:38AM +0800, 李志 wrote:
> 
> 
> 
> > -----原始邮件-----
> > 发件人: "Conor Dooley" <conor@kernel.org>
> > 发送时间:2026-03-04 17:30:57 (星期三)
> > 收件人: "Bo Gan" <ganboing@gmail.com>
> > 抄送: "Jakub Kicinski" <kuba@kernel.org>, lizhi2@eswincomputing.com, devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, wens@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com
> > 主题: Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control
> > 
> > On Tue, Mar 03, 2026 at 05:23:18PM -0800, Bo Gan wrote:
> > > Hi All,
> > > 
> > > On 3/3/26 16:47, Conor Dooley wrote:
> > > > On Tue, Mar 03, 2026 at 04:38:46PM -0800, Jakub Kicinski wrote:
> > > > > On Tue,  3 Mar 2026 14:16:37 +0800 lizhi2@eswincomputing.com wrote:
> > > > > > There are currently no in-tree users of the EIC7700 Ethernet driver, so
> > > > > > these changes are safe.
> > > > > 
> > > > > What do you mean by this sentence? The commit under Fixes was part of
> > > > > Linux v6.19 already.
> > > > 
> > > > The "funny" thing is that caring about users doesn't even really matter
> > > > on the devicetree patch, except for this hunk:
> > > > |@@ -81,7 +99,9 @@ properties:
> > > > |                          or external clock selection
> > > > |           - description: Offset of AXI clock controller Low-Power request
> > > > |                          register
> > > > |+          - description: Offset of register controlling TXD delay
> > > > |           - description: Offset of register controlling TX/RX clock delay
> > > > |+          - description: Offset of register controlling RXD delay
> > > > |
> > > > | required:
> > > > |   - compatible
> > > > And it only matters here because an item is injected mid-list. If this
> > > > was moved to the end with the RXD delay, the **dt-binding** changes
> > > > don't have issues with safety. I've not looked at whether there are
> > > > knock-on concerns about users in the driver or whatever yet, but from a
> > > > binding POV only that hunk can break something that currently works.
> > > 
> > > This was already discussed here in v1:
> > > https://lore.kernel.org/lkml/e7183ae1-8b8b-4e77-9f4e-3bc1b4b63556@lunn.ch/
> > > 
> > > The device-tree is not checked in yet by ESWIN folks, so there's currently
> > > no user of the dt-binding. No need to worry about backward compat.
> > 
> > The binding and driver exist, there doesn't need to be a dts in tree for
> > there to be potential users. If the break was important I might not
> > care, but this seems to be a gratuitous break, since the new items could
> > be added to the end of the list and compatibility maintained without
> > incurring any more difficulty for you.
> 
> Hi Conor and Krzysztof,
> 
> Thanks for the reviews.
> 
> - The next patch will fix the property order to avoid any breakage
>   with existing DT bindings.

Good, thanks.

> - Eth1 does have a timing issue in silicon, as discussed here:
>   https://lore.kernel.org/lkml/32a1f814.2c79.19bfe173225.Coremail.linmin@eswincomputing.com/
> 
>   Based on this, and according to the advice from Andrew
>   https://lore.kernel.org/lkml/59cec617-0189-4dc3-bc3f-6346155a62ae@lunn.ch/
>   https://lore.kernel.org/lkml/bd202cfa-d6eb-4d0e-982d-b49795dd25f7@lunn.ch/
>   adding a DT property is not a reasonable approach.
>   
>   In the next patch, I will improve the description/paragraph and properly
>   document the timing issues.

I personally don't mind having two compatibles, but I might be more
clear about what device the new one refers to (so something like
s/clk-inversion/eth1/g). But Krzysztof was the one who objected to
having multiple compatibles, so it's worth waiting to see what he has to
say.

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Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[Krzysztof Kozlowski]

On Tue, Mar 03, 2026 at 02:16:37PM +0800, lizhi2@eswincomputing.com wrote:
> From: Zhi Li <lizhi2@eswincomputing.com>
> 
> The second Ethernet controller (eth1) on the EIC7700 SoC may experience
> RX data sampling issues at high speed due to EIC7700-specific receive
> clock to data skew at the MAC input.
> 
> On the EIC7700 SoC, the second Ethernet controller (eth1) requires
> inversion of the internal RGMII receive clock in order to meet RX data
> sampling timing at high speed.
> 
> Describe this SoC-specific difference by introducing a distinct compatible
> string for MAC instances that require internal clock inversion, allowing the
> driver to select the appropriate configuration without relying on per-board
> vendor-specific properties.

Pointless description/paragrapgh. Your explanation why adding a
compatible is "because I need compatible". That's completely redundant.

Explain what is special about this MAC instance, what's different in its
programming model or other characteristics that you claim it is a
different device.

> 
> The rx-internal-delay-ps and tx-internal-delay-ps properties now use
> minimum and maximum constraints to reflect the actual hardware delay
> range (0-2540 ps) applied in 20 ps steps. This relaxes the binding
> validation compared to the previous enum-based definition and avoids
> regressions for existing DTBs while keeping the same hardware limits.
> 
> Treat the RX/TX internal delay properties as optional, board-specific
> tuning knobs and remove them from the example to avoid encouraging
> their use.
> 
> In addition, the binding now includes additional background information
> about the HSP CSR registers accessed by the MAC. The TXD and RXD delay
> control registers are included so the driver can explicitly clear any
> residual configuration left by the bootloader. Background reference for
> the High-Speed Subsystem and HSP CSR block is available in Chapter 10
> ("High-Speed Interface") of the EIC7700X SoC Technical Reference Manual,
> Part 4 (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf):
> https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
> 
> There are currently no in-tree users of the EIC7700 Ethernet driver, so
> these changes are safe.
> 
> Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC")
> Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
> ---
>  .../bindings/net/eswin,eic7700-eth.yaml       | 75 +++++++++++++++----
>  1 file changed, 59 insertions(+), 16 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
> index 91e8cd1db67b..22d1cecea07e 100644
> --- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
> +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
> @@ -20,6 +20,7 @@ select:
>        contains:
>          enum:
>            - eswin,eic7700-qos-eth
> +          - eswin,eic7700-qos-eth-clk-inversion
>    required:
>      - compatible
>  
> @@ -28,9 +29,13 @@ allOf:
>  
>  properties:
>    compatible:
> -    items:
> -      - const: eswin,eic7700-qos-eth
> -      - const: snps,dwmac-5.20
> +    oneOf:
> +      - items:
> +          - const: eswin,eic7700-qos-eth
> +          - const: snps,dwmac-5.20
> +      - items:
> +          - const: eswin,eic7700-qos-eth-clk-inversion

So just enum for both entries?

Anyway, that's the same device, so you do not get two compatibles. This
should be a property. Which property not sure, maybe all this was
discussed already.


> +          - const: snps,dwmac-5.20
>  
>    reg:
>      maxItems: 1
> @@ -63,16 +68,29 @@ properties:
>        - const: stmmaceth
>  
>    rx-internal-delay-ps:
> -    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
> +    minimum: 0
> +    maximum: 2540
> +    multipleOf: 20
>  
>    tx-internal-delay-ps:
> -    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
> +    minimum: 0
> +    maximum: 2540
> +    multipleOf: 20
>  
>    eswin,hsp-sp-csr:
>      description:
>        HSP CSR is to control and get status of different high-speed peripherals
>        (such as Ethernet, USB, SATA, etc.) via register, which can tune
>        board-level's parameters of PHY, etc.
> +
> +      Additional background information about the High-Speed Subsystem
> +      and the HSP CSR block is available in Chapter 10 ("High-Speed Interface")
> +      of the EIC7700X SoC Technical Reference Manual, Part 4
> +      (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf). The manual is
> +      publicly available at
> +      https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
> +
> +      This reference is provided for background information only.
>      $ref: /schemas/types.yaml#/definitions/phandle-array
>      items:
>        - items:
> @@ -81,7 +99,9 @@ properties:
>                           or external clock selection
>            - description: Offset of AXI clock controller Low-Power request
>                           register
> +          - description: Offset of register controlling TXD delay
>            - description: Offset of register controlling TX/RX clock delay
> +          - description: Offset of register controlling RXD delay

As pointed out, you cannot change the order and there is no reason for
doing this explained in commit msg.

Best regards,
Krzysztof

Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[Krzysztof Kozlowski]

On Tue, Mar 03, 2026 at 02:16:37PM +0800, lizhi2@eswincomputing.com wrote:
> From: Zhi Li <lizhi2@eswincomputing.com>
> 
> The second Ethernet controller (eth1) on the EIC7700 SoC may experience
> RX data sampling issues at high speed due to EIC7700-specific receive
> clock to data skew at the MAC input.
> 
> On the EIC7700 SoC, the second Ethernet controller (eth1) requires
> inversion of the internal RGMII receive clock in order to meet RX data
> sampling timing at high speed.
> 
> Describe this SoC-specific difference by introducing a distinct compatible
> string for MAC instances that require internal clock inversion, allowing the
> driver to select the appropriate configuration without relying on per-board
> vendor-specific properties.

Pointless description/paragrapgh. Your explanation why adding a
compatible is "because I need compatible". That's completely redundant.

Explain what is special about this MAC instance, what's different in its
programming model or other characteristics that you claim it is a
different device.

> 
> The rx-internal-delay-ps and tx-internal-delay-ps properties now use
> minimum and maximum constraints to reflect the actual hardware delay
> range (0-2540 ps) applied in 20 ps steps. This relaxes the binding
> validation compared to the previous enum-based definition and avoids
> regressions for existing DTBs while keeping the same hardware limits.
> 
> Treat the RX/TX internal delay properties as optional, board-specific
> tuning knobs and remove them from the example to avoid encouraging
> their use.
> 
> In addition, the binding now includes additional background information
> about the HSP CSR registers accessed by the MAC. The TXD and RXD delay
> control registers are included so the driver can explicitly clear any
> residual configuration left by the bootloader. Background reference for
> the High-Speed Subsystem and HSP CSR block is available in Chapter 10
> ("High-Speed Interface") of the EIC7700X SoC Technical Reference Manual,
> Part 4 (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf):
> https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
> 
> There are currently no in-tree users of the EIC7700 Ethernet driver, so
> these changes are safe.
> 
> Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC")
> Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
> ---
>  .../bindings/net/eswin,eic7700-eth.yaml       | 75 +++++++++++++++----
>  1 file changed, 59 insertions(+), 16 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
> index 91e8cd1db67b..22d1cecea07e 100644
> --- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
> +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
> @@ -20,6 +20,7 @@ select:
>        contains:
>          enum:
>            - eswin,eic7700-qos-eth
> +          - eswin,eic7700-qos-eth-clk-inversion
>    required:
>      - compatible
>  
> @@ -28,9 +29,13 @@ allOf:
>  
>  properties:
>    compatible:
> -    items:
> -      - const: eswin,eic7700-qos-eth
> -      - const: snps,dwmac-5.20
> +    oneOf:
> +      - items:
> +          - const: eswin,eic7700-qos-eth
> +          - const: snps,dwmac-5.20
> +      - items:
> +          - const: eswin,eic7700-qos-eth-clk-inversion

So just enum for both entries?

Anyway, that's the same device, so you do not get two compatibles. This
should be a property. Which property not sure, maybe all this was
discussed already.


> +          - const: snps,dwmac-5.20
>  
>    reg:
>      maxItems: 1
> @@ -63,16 +68,29 @@ properties:
>        - const: stmmaceth
>  
>    rx-internal-delay-ps:
> -    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
> +    minimum: 0
> +    maximum: 2540
> +    multipleOf: 20
>  
>    tx-internal-delay-ps:
> -    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
> +    minimum: 0
> +    maximum: 2540
> +    multipleOf: 20
>  
>    eswin,hsp-sp-csr:
>      description:
>        HSP CSR is to control and get status of different high-speed peripherals
>        (such as Ethernet, USB, SATA, etc.) via register, which can tune
>        board-level's parameters of PHY, etc.
> +
> +      Additional background information about the High-Speed Subsystem
> +      and the HSP CSR block is available in Chapter 10 ("High-Speed Interface")
> +      of the EIC7700X SoC Technical Reference Manual, Part 4
> +      (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf). The manual is
> +      publicly available at
> +      https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
> +
> +      This reference is provided for background information only.
>      $ref: /schemas/types.yaml#/definitions/phandle-array
>      items:
>        - items:
> @@ -81,7 +99,9 @@ properties:
>                           or external clock selection
>            - description: Offset of AXI clock controller Low-Power request
>                           register
> +          - description: Offset of register controlling TXD delay
>            - description: Offset of register controlling TX/RX clock delay
> +          - description: Offset of register controlling RXD delay

As pointed out, you cannot change the order and there is no reason for
doing this explained in commit msg.

Best regards,
Krzysztof


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Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[Bo Gan]

Hi Krzysztof,

On 3/3/26 23:44, Krzysztof Kozlowski wrote:
> On Tue, Mar 03, 2026 at 02:16:37PM +0800, lizhi2@eswincomputing.com wrote:
>> From: Zhi Li <lizhi2@eswincomputing.com>
>>
>> The second Ethernet controller (eth1) on the EIC7700 SoC may experience
>> RX data sampling issues at high speed due to EIC7700-specific receive
>> clock to data skew at the MAC input.
>>
>> On the EIC7700 SoC, the second Ethernet controller (eth1) requires
>> inversion of the internal RGMII receive clock in order to meet RX data
>> sampling timing at high speed.
>>
>> Describe this SoC-specific difference by introducing a distinct compatible
>> string for MAC instances that require internal clock inversion, allowing the
>> driver to select the appropriate configuration without relying on per-board
>> vendor-specific properties.
> 
> Pointless description/paragrapgh. Your explanation why adding a
> compatible is "because I need compatible". That's completely redundant.
> 
> Explain what is special about this MAC instance, what's different in its
> programming model or other characteristics that you claim it is a
> different device.
> 

I think ESWIN should improve the description/paragraph and properly doc
the timing issues discussed here:
https://lore.kernel.org/lkml/32a1f814.2c79.19bfe173225.Coremail.linmin@eswincomputing.com/

I do feel the need of using a different compatible, though. I think we
discussed in depth in that thread (link above), and advice from Andrew

https://lore.kernel.org/lkml/59cec617-0189-4dc3-bc3f-6346155a62ae@lunn.ch/

https://lore.kernel.org/lkml/bd202cfa-d6eb-4d0e-982d-b49795dd25f7@lunn.ch/

is to basically apply different parameters to MAC based on eth0/eth1. The
compatible string approach is a clean solution to achieve that. The reason
being that for eth1, there's no way to meet the standard without clock
inversion, given the vast internal clock skew. I don't think claiming it
as a different device than eth0 is that far-fetched. Hence, no need for an
additional property and the driver code to check for that.

>>
>> The rx-internal-delay-ps and tx-internal-delay-ps properties now use
>> minimum and maximum constraints to reflect the actual hardware delay
>> range (0-2540 ps) applied in 20 ps steps. This relaxes the binding
>> validation compared to the previous enum-based definition and avoids
>> regressions for existing DTBs while keeping the same hardware limits.
>>
>> Treat the RX/TX internal delay properties as optional, board-specific
>> tuning knobs and remove them from the example to avoid encouraging
>> their use.
>>
>> In addition, the binding now includes additional background information
>> about the HSP CSR registers accessed by the MAC. The TXD and RXD delay
>> control registers are included so the driver can explicitly clear any
>> residual configuration left by the bootloader. Background reference for
>> the High-Speed Subsystem and HSP CSR block is available in Chapter 10
>> ("High-Speed Interface") of the EIC7700X SoC Technical Reference Manual,
>> Part 4 (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf):
>> https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
>>
>> There are currently no in-tree users of the EIC7700 Ethernet driver, so
>> these changes are safe.
>>
>> Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC")
>> Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
>> ---
>>   .../bindings/net/eswin,eic7700-eth.yaml       | 75 +++++++++++++++----
>>   1 file changed, 59 insertions(+), 16 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
>> index 91e8cd1db67b..22d1cecea07e 100644
>> --- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
>> +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
>> @@ -20,6 +20,7 @@ select:
>>         contains:
>>           enum:
>>             - eswin,eic7700-qos-eth
>> +          - eswin,eic7700-qos-eth-clk-inversion
>>     required:
>>       - compatible
>>   
>> @@ -28,9 +29,13 @@ allOf:
>>   
>>   properties:
>>     compatible:
>> -    items:
>> -      - const: eswin,eic7700-qos-eth
>> -      - const: snps,dwmac-5.20
>> +    oneOf:
>> +      - items:
>> +          - const: eswin,eic7700-qos-eth
>> +          - const: snps,dwmac-5.20
>> +      - items:
>> +          - const: eswin,eic7700-qos-eth-clk-inversion
> 
> So just enum for both entries?
> 
> Anyway, that's the same device, so you do not get two compatibles. This
> should be a property. Which property not sure, maybe all this was
> discussed already.
> 
> 
>> +          - const: snps,dwmac-5.20
>>   
>>     reg:
>>       maxItems: 1
>> @@ -63,16 +68,29 @@ properties:
>>         - const: stmmaceth
>>   
>>     rx-internal-delay-ps:
>> -    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
>> +    minimum: 0
>> +    maximum: 2540
>> +    multipleOf: 20
>>   
>>     tx-internal-delay-ps:
>> -    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
>> +    minimum: 0
>> +    maximum: 2540
>> +    multipleOf: 20
>>   
>>     eswin,hsp-sp-csr:
>>       description:
>>         HSP CSR is to control and get status of different high-speed peripherals
>>         (such as Ethernet, USB, SATA, etc.) via register, which can tune
>>         board-level's parameters of PHY, etc.
>> +
>> +      Additional background information about the High-Speed Subsystem
>> +      and the HSP CSR block is available in Chapter 10 ("High-Speed Interface")
>> +      of the EIC7700X SoC Technical Reference Manual, Part 4
>> +      (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf). The manual is
>> +      publicly available at
>> +      https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
>> +
>> +      This reference is provided for background information only.
>>       $ref: /schemas/types.yaml#/definitions/phandle-array
>>       items:
>>         - items:
>> @@ -81,7 +99,9 @@ properties:
>>                            or external clock selection
>>             - description: Offset of AXI clock controller Low-Power request
>>                            register
>> +          - description: Offset of register controlling TXD delay
>>             - description: Offset of register controlling TX/RX clock delay
>> +          - description: Offset of register controlling RXD delay
> 
> As pointed out, you cannot change the order and there is no reason for
> doing this explained in commit msg.
> 
> Best regards,
> Krzysztof
> 

Bo

Re: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[Bo Gan]

Hi Krzysztof,

On 3/3/26 23:44, Krzysztof Kozlowski wrote:
> On Tue, Mar 03, 2026 at 02:16:37PM +0800, lizhi2@eswincomputing.com wrote:
>> From: Zhi Li <lizhi2@eswincomputing.com>
>>
>> The second Ethernet controller (eth1) on the EIC7700 SoC may experience
>> RX data sampling issues at high speed due to EIC7700-specific receive
>> clock to data skew at the MAC input.
>>
>> On the EIC7700 SoC, the second Ethernet controller (eth1) requires
>> inversion of the internal RGMII receive clock in order to meet RX data
>> sampling timing at high speed.
>>
>> Describe this SoC-specific difference by introducing a distinct compatible
>> string for MAC instances that require internal clock inversion, allowing the
>> driver to select the appropriate configuration without relying on per-board
>> vendor-specific properties.
> 
> Pointless description/paragrapgh. Your explanation why adding a
> compatible is "because I need compatible". That's completely redundant.
> 
> Explain what is special about this MAC instance, what's different in its
> programming model or other characteristics that you claim it is a
> different device.
> 

I think ESWIN should improve the description/paragraph and properly doc
the timing issues discussed here:
https://lore.kernel.org/lkml/32a1f814.2c79.19bfe173225.Coremail.linmin@eswincomputing.com/

I do feel the need of using a different compatible, though. I think we
discussed in depth in that thread (link above), and advice from Andrew

https://lore.kernel.org/lkml/59cec617-0189-4dc3-bc3f-6346155a62ae@lunn.ch/

https://lore.kernel.org/lkml/bd202cfa-d6eb-4d0e-982d-b49795dd25f7@lunn.ch/

is to basically apply different parameters to MAC based on eth0/eth1. The
compatible string approach is a clean solution to achieve that. The reason
being that for eth1, there's no way to meet the standard without clock
inversion, given the vast internal clock skew. I don't think claiming it
as a different device than eth0 is that far-fetched. Hence, no need for an
additional property and the driver code to check for that.

>>
>> The rx-internal-delay-ps and tx-internal-delay-ps properties now use
>> minimum and maximum constraints to reflect the actual hardware delay
>> range (0-2540 ps) applied in 20 ps steps. This relaxes the binding
>> validation compared to the previous enum-based definition and avoids
>> regressions for existing DTBs while keeping the same hardware limits.
>>
>> Treat the RX/TX internal delay properties as optional, board-specific
>> tuning knobs and remove them from the example to avoid encouraging
>> their use.
>>
>> In addition, the binding now includes additional background information
>> about the HSP CSR registers accessed by the MAC. The TXD and RXD delay
>> control registers are included so the driver can explicitly clear any
>> residual configuration left by the bootloader. Background reference for
>> the High-Speed Subsystem and HSP CSR block is available in Chapter 10
>> ("High-Speed Interface") of the EIC7700X SoC Technical Reference Manual,
>> Part 4 (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf):
>> https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
>>
>> There are currently no in-tree users of the EIC7700 Ethernet driver, so
>> these changes are safe.
>>
>> Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC")
>> Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
>> ---
>>   .../bindings/net/eswin,eic7700-eth.yaml       | 75 +++++++++++++++----
>>   1 file changed, 59 insertions(+), 16 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
>> index 91e8cd1db67b..22d1cecea07e 100644
>> --- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
>> +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
>> @@ -20,6 +20,7 @@ select:
>>         contains:
>>           enum:
>>             - eswin,eic7700-qos-eth
>> +          - eswin,eic7700-qos-eth-clk-inversion
>>     required:
>>       - compatible
>>   
>> @@ -28,9 +29,13 @@ allOf:
>>   
>>   properties:
>>     compatible:
>> -    items:
>> -      - const: eswin,eic7700-qos-eth
>> -      - const: snps,dwmac-5.20
>> +    oneOf:
>> +      - items:
>> +          - const: eswin,eic7700-qos-eth
>> +          - const: snps,dwmac-5.20
>> +      - items:
>> +          - const: eswin,eic7700-qos-eth-clk-inversion
> 
> So just enum for both entries?
> 
> Anyway, that's the same device, so you do not get two compatibles. This
> should be a property. Which property not sure, maybe all this was
> discussed already.
> 
> 
>> +          - const: snps,dwmac-5.20
>>   
>>     reg:
>>       maxItems: 1
>> @@ -63,16 +68,29 @@ properties:
>>         - const: stmmaceth
>>   
>>     rx-internal-delay-ps:
>> -    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
>> +    minimum: 0
>> +    maximum: 2540
>> +    multipleOf: 20
>>   
>>     tx-internal-delay-ps:
>> -    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
>> +    minimum: 0
>> +    maximum: 2540
>> +    multipleOf: 20
>>   
>>     eswin,hsp-sp-csr:
>>       description:
>>         HSP CSR is to control and get status of different high-speed peripherals
>>         (such as Ethernet, USB, SATA, etc.) via register, which can tune
>>         board-level's parameters of PHY, etc.
>> +
>> +      Additional background information about the High-Speed Subsystem
>> +      and the HSP CSR block is available in Chapter 10 ("High-Speed Interface")
>> +      of the EIC7700X SoC Technical Reference Manual, Part 4
>> +      (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf). The manual is
>> +      publicly available at
>> +      https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
>> +
>> +      This reference is provided for background information only.
>>       $ref: /schemas/types.yaml#/definitions/phandle-array
>>       items:
>>         - items:
>> @@ -81,7 +99,9 @@ properties:
>>                            or external clock selection
>>             - description: Offset of AXI clock controller Low-Power request
>>                            register
>> +          - description: Offset of register controlling TXD delay
>>             - description: Offset of register controlling TX/RX clock delay
>> +          - description: Offset of register controlling RXD delay
> 
> As pointed out, you cannot change the order and there is no reason for
> doing this explained in commit msg.
> 
> Best regards,
> Krzysztof
> 

Bo


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[PATCH net-next v3 2/3] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing

[lizhi2]

From: Zhi Li <lizhi2@eswincomputing.com>

The second Ethernet controller (eth1) on the Eswin EIC7700 SoC may fail
to sample RX data correctly at Gigabit speed due to EIC7700-specific
receive clock to data skew at the MAC input in the silicon.

The existing internal delay configuration does not provide sufficient
adjustment range to compensate for this condition at 1000Mbps.
Update the EIC7700 DWMAC glue driver to apply EIC7700-specific clock
sampling inversion only during Gigabit operation on MAC instances
that require it.

TXD and RXD delay registers are explicitly cleared during initialization
to override any residual configuration left by the bootloader. All HSP
CSR register accesses are performed only after the required clocks are
enabled.

Fixes: ea77dbbdbc4e ("net: stmmac: add Eswin EIC7700 glue driver")
Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
---
 .../ethernet/stmicro/stmmac/dwmac-eic7700.c   | 180 +++++++++++++-----
 1 file changed, 137 insertions(+), 43 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c
index bcb8e000e720..acddea58cc6b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c
@@ -28,20 +28,40 @@
 
 /*
  * TX/RX Clock Delay Bit Masks:
- * - TX Delay: bits [14:8] — TX_CLK delay (unit: 0.1ns per bit)
- * - RX Delay: bits [30:24] — RX_CLK delay (unit: 0.1ns per bit)
+ * - TX Delay: bits [14:8] — TX_CLK delay (unit: 0.02ns per bit)
+ * - TX Invert : bit  [15]
+ * - RX Delay: bits [30:24] — RX_CLK delay (unit: 0.02ns per bit)
+ * - RX Invert : bit  [31]
  */
 #define EIC7700_ETH_TX_ADJ_DELAY	GENMASK(14, 8)
 #define EIC7700_ETH_RX_ADJ_DELAY	GENMASK(30, 24)
+#define EIC7700_ETH_TX_INV_DELAY	BIT(15)
+#define EIC7700_ETH_RX_INV_DELAY	BIT(31)
 
-#define EIC7700_MAX_DELAY_UNIT 0x7F
+#define EIC7700_MAX_DELAY_STEPS		0x7F
+#define EIC7700_DELAY_STEP_PS		20
+#define EIC7700_MAX_DELAY_PS	\
+	(EIC7700_MAX_DELAY_STEPS * EIC7700_DELAY_STEP_PS)
 
 static const char * const eic7700_clk_names[] = {
 	"tx", "axi", "cfg",
 };
 
+struct eic7700_dwmac_data {
+	bool rgmii_rx_clk_invert;
+};
+
 struct eic7700_qos_priv {
+	struct device *dev;
 	struct plat_stmmacenet_data *plat_dat;
+	struct regmap *eic7700_hsp_regmap;
+	u32 eth_axi_lp_ctrl_offset;
+	u32 eth_phy_ctrl_offset;
+	u32 eth_txd_offset;
+	u32 eth_clk_offset;
+	u32 eth_rxd_offset;
+	u32 eth_clk_dly_param;
+	bool eth_rx_clk_inv;
 };
 
 static int eic7700_clks_config(void *priv, bool enabled)
@@ -61,8 +81,26 @@ static int eic7700_clks_config(void *priv, bool enabled)
 static int eic7700_dwmac_init(struct device *dev, void *priv)
 {
 	struct eic7700_qos_priv *dwc = priv;
+	int ret;
+
+	ret = eic7700_clks_config(dwc, true);
+	if (ret)
+		return ret;
+
+	ret = regmap_set_bits(dwc->eic7700_hsp_regmap,
+			      dwc->eth_phy_ctrl_offset,
+			      EIC7700_ETH_TX_CLK_SEL |
+			      EIC7700_ETH_PHY_INTF_SELI);
+	if (ret)
+		return ret;
+
+	regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_axi_lp_ctrl_offset,
+		     EIC7700_ETH_CSYSREQ_VAL);
 
-	return eic7700_clks_config(dwc, true);
+	regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_txd_offset, 0);
+	regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_rxd_offset, 0);
+
+	return 0;
 }
 
 static void eic7700_dwmac_exit(struct device *dev, void *priv)
@@ -88,18 +126,34 @@ static int eic7700_dwmac_resume(struct device *dev, void *priv)
 	return ret;
 }
 
+static void eic7700_dwmac_fix_speed(void *priv, int speed, unsigned int mode)
+{
+	struct eic7700_qos_priv *dwc = (struct eic7700_qos_priv *)priv;
+	u32 dly_param = dwc->eth_clk_dly_param;
+
+	switch (speed) {
+	case SPEED_1000:
+		if (dwc->eth_rx_clk_inv)
+			dly_param |= EIC7700_ETH_RX_INV_DELAY;
+		break;
+	case SPEED_100:
+	case SPEED_10:
+		break;
+	default:
+		dev_err(dwc->dev, "invalid speed %u\n", speed);
+		break;
+	}
+
+	regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_clk_offset, dly_param);
+}
+
 static int eic7700_dwmac_probe(struct platform_device *pdev)
 {
+	const struct eic7700_dwmac_data *data;
 	struct plat_stmmacenet_data *plat_dat;
 	struct stmmac_resources stmmac_res;
 	struct eic7700_qos_priv *dwc_priv;
-	struct regmap *eic7700_hsp_regmap;
-	u32 eth_axi_lp_ctrl_offset;
-	u32 eth_phy_ctrl_offset;
-	u32 eth_phy_ctrl_regset;
-	u32 eth_rxd_dly_offset;
-	u32 eth_dly_param = 0;
-	u32 delay_ps;
+	u32 delay_ps, val;
 	int i, ret;
 
 	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
@@ -116,70 +170,95 @@ static int eic7700_dwmac_probe(struct platform_device *pdev)
 	if (!dwc_priv)
 		return -ENOMEM;
 
+	dwc_priv->dev = &pdev->dev;
+
+	data = device_get_match_data(&pdev->dev);
+	if (!data)
+		return dev_err_probe(&pdev->dev,
+				     -EINVAL, "no match data found\n");
+
+	dwc_priv->eth_rx_clk_inv = data->rgmii_rx_clk_invert;
+
 	/* Read rx-internal-delay-ps and update rx_clk delay */
 	if (!of_property_read_u32(pdev->dev.of_node,
 				  "rx-internal-delay-ps", &delay_ps)) {
-		u32 val = min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT);
+		if (delay_ps % EIC7700_DELAY_STEP_PS)
+			return dev_err_probe(&pdev->dev, -EINVAL,
+				"rx delay must be multiple of %dps\n",
+				EIC7700_DELAY_STEP_PS);
 
-		eth_dly_param &= ~EIC7700_ETH_RX_ADJ_DELAY;
-		eth_dly_param |= FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val);
-	} else {
-		return dev_err_probe(&pdev->dev, -EINVAL,
-			"missing required property rx-internal-delay-ps\n");
+		if (delay_ps > EIC7700_MAX_DELAY_PS)
+			return dev_err_probe(&pdev->dev, -EINVAL,
+				"rx delay out of range\n");
+
+		val = delay_ps / EIC7700_DELAY_STEP_PS;
+
+		dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_RX_ADJ_DELAY;
+		dwc_priv->eth_clk_dly_param |=
+				 FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val);
 	}
 
 	/* Read tx-internal-delay-ps and update tx_clk delay */
 	if (!of_property_read_u32(pdev->dev.of_node,
 				  "tx-internal-delay-ps", &delay_ps)) {
-		u32 val = min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT);
+		if (delay_ps % EIC7700_DELAY_STEP_PS)
+			return dev_err_probe(&pdev->dev, -EINVAL,
+				"tx delay must be multiple of %dps\n",
+				EIC7700_DELAY_STEP_PS);
+
+		if (delay_ps > EIC7700_MAX_DELAY_PS)
+			return dev_err_probe(&pdev->dev, -EINVAL,
+				"tx delay out of range\n");
 
-		eth_dly_param &= ~EIC7700_ETH_TX_ADJ_DELAY;
-		eth_dly_param |= FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val);
-	} else {
-		return dev_err_probe(&pdev->dev, -EINVAL,
-			"missing required property tx-internal-delay-ps\n");
+		val = delay_ps / EIC7700_DELAY_STEP_PS;
+
+		dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_TX_ADJ_DELAY;
+		dwc_priv->eth_clk_dly_param |=
+				 FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val);
 	}
 
-	eic7700_hsp_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
-							     "eswin,hsp-sp-csr");
-	if (IS_ERR(eic7700_hsp_regmap))
+	dwc_priv->eic7700_hsp_regmap =
+			syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+							"eswin,hsp-sp-csr");
+	if (IS_ERR(dwc_priv->eic7700_hsp_regmap))
 		return dev_err_probe(&pdev->dev,
-				PTR_ERR(eic7700_hsp_regmap),
+				PTR_ERR(dwc_priv->eic7700_hsp_regmap),
 				"Failed to get hsp-sp-csr regmap\n");
 
 	ret = of_property_read_u32_index(pdev->dev.of_node,
 					 "eswin,hsp-sp-csr",
-					 1, &eth_phy_ctrl_offset);
+					 1, &dwc_priv->eth_phy_ctrl_offset);
 	if (ret)
 		return dev_err_probe(&pdev->dev, ret,
 				     "can't get eth_phy_ctrl_offset\n");
 
-	regmap_read(eic7700_hsp_regmap, eth_phy_ctrl_offset,
-		    &eth_phy_ctrl_regset);
-	eth_phy_ctrl_regset |=
-		(EIC7700_ETH_TX_CLK_SEL | EIC7700_ETH_PHY_INTF_SELI);
-	regmap_write(eic7700_hsp_regmap, eth_phy_ctrl_offset,
-		     eth_phy_ctrl_regset);
-
 	ret = of_property_read_u32_index(pdev->dev.of_node,
 					 "eswin,hsp-sp-csr",
-					 2, &eth_axi_lp_ctrl_offset);
+					 2, &dwc_priv->eth_axi_lp_ctrl_offset);
 	if (ret)
 		return dev_err_probe(&pdev->dev, ret,
 				     "can't get eth_axi_lp_ctrl_offset\n");
 
-	regmap_write(eic7700_hsp_regmap, eth_axi_lp_ctrl_offset,
-		     EIC7700_ETH_CSYSREQ_VAL);
+	ret = of_property_read_u32_index(pdev->dev.of_node,
+					 "eswin,hsp-sp-csr",
+					 3, &dwc_priv->eth_txd_offset);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret,
+				     "can't get eth_txd_offset\n");
 
 	ret = of_property_read_u32_index(pdev->dev.of_node,
 					 "eswin,hsp-sp-csr",
-					 3, &eth_rxd_dly_offset);
+					 4, &dwc_priv->eth_clk_offset);
 	if (ret)
 		return dev_err_probe(&pdev->dev, ret,
-				     "can't get eth_rxd_dly_offset\n");
+				     "can't get eth_clk_offset\n");
 
-	regmap_write(eic7700_hsp_regmap, eth_rxd_dly_offset,
-		     eth_dly_param);
+	ret = of_property_read_u32_index(pdev->dev.of_node,
+					 "eswin,hsp-sp-csr",
+					 5, &dwc_priv->eth_rxd_offset);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret,
+				     "can't get eth_rxd_offset\n");
 
 	plat_dat->num_clks = ARRAY_SIZE(eic7700_clk_names);
 	plat_dat->clks = devm_kcalloc(&pdev->dev,
@@ -208,12 +287,27 @@ static int eic7700_dwmac_probe(struct platform_device *pdev)
 	plat_dat->exit = eic7700_dwmac_exit;
 	plat_dat->suspend = eic7700_dwmac_suspend;
 	plat_dat->resume = eic7700_dwmac_resume;
+	plat_dat->fix_mac_speed = eic7700_dwmac_fix_speed;
 
 	return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
 }
 
+static const struct eic7700_dwmac_data eic7700_dwmac_data = {
+	.rgmii_rx_clk_invert = false,
+};
+
+static const struct eic7700_dwmac_data eic7700_dwmac_data_clk_inversion = {
+	.rgmii_rx_clk_invert = true,
+};
+
 static const struct of_device_id eic7700_dwmac_match[] = {
-	{ .compatible = "eswin,eic7700-qos-eth" },
+	{	.compatible = "eswin,eic7700-qos-eth",
+		.data = &eic7700_dwmac_data,
+	},
+	{
+		.compatible = "eswin,eic7700-qos-eth-clk-inversion",
+		.data = &eic7700_dwmac_data_clk_inversion,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, eic7700_dwmac_match);
-- 
2.25.1

[PATCH net-next v3 2/3] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing

[lizhi2]

From: Zhi Li <lizhi2@eswincomputing.com>

The second Ethernet controller (eth1) on the Eswin EIC7700 SoC may fail
to sample RX data correctly at Gigabit speed due to EIC7700-specific
receive clock to data skew at the MAC input in the silicon.

The existing internal delay configuration does not provide sufficient
adjustment range to compensate for this condition at 1000Mbps.
Update the EIC7700 DWMAC glue driver to apply EIC7700-specific clock
sampling inversion only during Gigabit operation on MAC instances
that require it.

TXD and RXD delay registers are explicitly cleared during initialization
to override any residual configuration left by the bootloader. All HSP
CSR register accesses are performed only after the required clocks are
enabled.

Fixes: ea77dbbdbc4e ("net: stmmac: add Eswin EIC7700 glue driver")
Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
---
 .../ethernet/stmicro/stmmac/dwmac-eic7700.c   | 180 +++++++++++++-----
 1 file changed, 137 insertions(+), 43 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c
index bcb8e000e720..acddea58cc6b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c
@@ -28,20 +28,40 @@
 
 /*
  * TX/RX Clock Delay Bit Masks:
- * - TX Delay: bits [14:8] — TX_CLK delay (unit: 0.1ns per bit)
- * - RX Delay: bits [30:24] — RX_CLK delay (unit: 0.1ns per bit)
+ * - TX Delay: bits [14:8] — TX_CLK delay (unit: 0.02ns per bit)
+ * - TX Invert : bit  [15]
+ * - RX Delay: bits [30:24] — RX_CLK delay (unit: 0.02ns per bit)
+ * - RX Invert : bit  [31]
  */
 #define EIC7700_ETH_TX_ADJ_DELAY	GENMASK(14, 8)
 #define EIC7700_ETH_RX_ADJ_DELAY	GENMASK(30, 24)
+#define EIC7700_ETH_TX_INV_DELAY	BIT(15)
+#define EIC7700_ETH_RX_INV_DELAY	BIT(31)
 
-#define EIC7700_MAX_DELAY_UNIT 0x7F
+#define EIC7700_MAX_DELAY_STEPS		0x7F
+#define EIC7700_DELAY_STEP_PS		20
+#define EIC7700_MAX_DELAY_PS	\
+	(EIC7700_MAX_DELAY_STEPS * EIC7700_DELAY_STEP_PS)
 
 static const char * const eic7700_clk_names[] = {
 	"tx", "axi", "cfg",
 };
 
+struct eic7700_dwmac_data {
+	bool rgmii_rx_clk_invert;
+};
+
 struct eic7700_qos_priv {
+	struct device *dev;
 	struct plat_stmmacenet_data *plat_dat;
+	struct regmap *eic7700_hsp_regmap;
+	u32 eth_axi_lp_ctrl_offset;
+	u32 eth_phy_ctrl_offset;
+	u32 eth_txd_offset;
+	u32 eth_clk_offset;
+	u32 eth_rxd_offset;
+	u32 eth_clk_dly_param;
+	bool eth_rx_clk_inv;
 };
 
 static int eic7700_clks_config(void *priv, bool enabled)
@@ -61,8 +81,26 @@ static int eic7700_clks_config(void *priv, bool enabled)
 static int eic7700_dwmac_init(struct device *dev, void *priv)
 {
 	struct eic7700_qos_priv *dwc = priv;
+	int ret;
+
+	ret = eic7700_clks_config(dwc, true);
+	if (ret)
+		return ret;
+
+	ret = regmap_set_bits(dwc->eic7700_hsp_regmap,
+			      dwc->eth_phy_ctrl_offset,
+			      EIC7700_ETH_TX_CLK_SEL |
+			      EIC7700_ETH_PHY_INTF_SELI);
+	if (ret)
+		return ret;
+
+	regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_axi_lp_ctrl_offset,
+		     EIC7700_ETH_CSYSREQ_VAL);
 
-	return eic7700_clks_config(dwc, true);
+	regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_txd_offset, 0);
+	regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_rxd_offset, 0);
+
+	return 0;
 }
 
 static void eic7700_dwmac_exit(struct device *dev, void *priv)
@@ -88,18 +126,34 @@ static int eic7700_dwmac_resume(struct device *dev, void *priv)
 	return ret;
 }
 
+static void eic7700_dwmac_fix_speed(void *priv, int speed, unsigned int mode)
+{
+	struct eic7700_qos_priv *dwc = (struct eic7700_qos_priv *)priv;
+	u32 dly_param = dwc->eth_clk_dly_param;
+
+	switch (speed) {
+	case SPEED_1000:
+		if (dwc->eth_rx_clk_inv)
+			dly_param |= EIC7700_ETH_RX_INV_DELAY;
+		break;
+	case SPEED_100:
+	case SPEED_10:
+		break;
+	default:
+		dev_err(dwc->dev, "invalid speed %u\n", speed);
+		break;
+	}
+
+	regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_clk_offset, dly_param);
+}
+
 static int eic7700_dwmac_probe(struct platform_device *pdev)
 {
+	const struct eic7700_dwmac_data *data;
 	struct plat_stmmacenet_data *plat_dat;
 	struct stmmac_resources stmmac_res;
 	struct eic7700_qos_priv *dwc_priv;
-	struct regmap *eic7700_hsp_regmap;
-	u32 eth_axi_lp_ctrl_offset;
-	u32 eth_phy_ctrl_offset;
-	u32 eth_phy_ctrl_regset;
-	u32 eth_rxd_dly_offset;
-	u32 eth_dly_param = 0;
-	u32 delay_ps;
+	u32 delay_ps, val;
 	int i, ret;
 
 	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
@@ -116,70 +170,95 @@ static int eic7700_dwmac_probe(struct platform_device *pdev)
 	if (!dwc_priv)
 		return -ENOMEM;
 
+	dwc_priv->dev = &pdev->dev;
+
+	data = device_get_match_data(&pdev->dev);
+	if (!data)
+		return dev_err_probe(&pdev->dev,
+				     -EINVAL, "no match data found\n");
+
+	dwc_priv->eth_rx_clk_inv = data->rgmii_rx_clk_invert;
+
 	/* Read rx-internal-delay-ps and update rx_clk delay */
 	if (!of_property_read_u32(pdev->dev.of_node,
 				  "rx-internal-delay-ps", &delay_ps)) {
-		u32 val = min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT);
+		if (delay_ps % EIC7700_DELAY_STEP_PS)
+			return dev_err_probe(&pdev->dev, -EINVAL,
+				"rx delay must be multiple of %dps\n",
+				EIC7700_DELAY_STEP_PS);
 
-		eth_dly_param &= ~EIC7700_ETH_RX_ADJ_DELAY;
-		eth_dly_param |= FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val);
-	} else {
-		return dev_err_probe(&pdev->dev, -EINVAL,
-			"missing required property rx-internal-delay-ps\n");
+		if (delay_ps > EIC7700_MAX_DELAY_PS)
+			return dev_err_probe(&pdev->dev, -EINVAL,
+				"rx delay out of range\n");
+
+		val = delay_ps / EIC7700_DELAY_STEP_PS;
+
+		dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_RX_ADJ_DELAY;
+		dwc_priv->eth_clk_dly_param |=
+				 FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val);
 	}
 
 	/* Read tx-internal-delay-ps and update tx_clk delay */
 	if (!of_property_read_u32(pdev->dev.of_node,
 				  "tx-internal-delay-ps", &delay_ps)) {
-		u32 val = min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT);
+		if (delay_ps % EIC7700_DELAY_STEP_PS)
+			return dev_err_probe(&pdev->dev, -EINVAL,
+				"tx delay must be multiple of %dps\n",
+				EIC7700_DELAY_STEP_PS);
+
+		if (delay_ps > EIC7700_MAX_DELAY_PS)
+			return dev_err_probe(&pdev->dev, -EINVAL,
+				"tx delay out of range\n");
 
-		eth_dly_param &= ~EIC7700_ETH_TX_ADJ_DELAY;
-		eth_dly_param |= FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val);
-	} else {
-		return dev_err_probe(&pdev->dev, -EINVAL,
-			"missing required property tx-internal-delay-ps\n");
+		val = delay_ps / EIC7700_DELAY_STEP_PS;
+
+		dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_TX_ADJ_DELAY;
+		dwc_priv->eth_clk_dly_param |=
+				 FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val);
 	}
 
-	eic7700_hsp_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
-							     "eswin,hsp-sp-csr");
-	if (IS_ERR(eic7700_hsp_regmap))
+	dwc_priv->eic7700_hsp_regmap =
+			syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+							"eswin,hsp-sp-csr");
+	if (IS_ERR(dwc_priv->eic7700_hsp_regmap))
 		return dev_err_probe(&pdev->dev,
-				PTR_ERR(eic7700_hsp_regmap),
+				PTR_ERR(dwc_priv->eic7700_hsp_regmap),
 				"Failed to get hsp-sp-csr regmap\n");
 
 	ret = of_property_read_u32_index(pdev->dev.of_node,
 					 "eswin,hsp-sp-csr",
-					 1, &eth_phy_ctrl_offset);
+					 1, &dwc_priv->eth_phy_ctrl_offset);
 	if (ret)
 		return dev_err_probe(&pdev->dev, ret,
 				     "can't get eth_phy_ctrl_offset\n");
 
-	regmap_read(eic7700_hsp_regmap, eth_phy_ctrl_offset,
-		    &eth_phy_ctrl_regset);
-	eth_phy_ctrl_regset |=
-		(EIC7700_ETH_TX_CLK_SEL | EIC7700_ETH_PHY_INTF_SELI);
-	regmap_write(eic7700_hsp_regmap, eth_phy_ctrl_offset,
-		     eth_phy_ctrl_regset);
-
 	ret = of_property_read_u32_index(pdev->dev.of_node,
 					 "eswin,hsp-sp-csr",
-					 2, &eth_axi_lp_ctrl_offset);
+					 2, &dwc_priv->eth_axi_lp_ctrl_offset);
 	if (ret)
 		return dev_err_probe(&pdev->dev, ret,
 				     "can't get eth_axi_lp_ctrl_offset\n");
 
-	regmap_write(eic7700_hsp_regmap, eth_axi_lp_ctrl_offset,
-		     EIC7700_ETH_CSYSREQ_VAL);
+	ret = of_property_read_u32_index(pdev->dev.of_node,
+					 "eswin,hsp-sp-csr",
+					 3, &dwc_priv->eth_txd_offset);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret,
+				     "can't get eth_txd_offset\n");
 
 	ret = of_property_read_u32_index(pdev->dev.of_node,
 					 "eswin,hsp-sp-csr",
-					 3, &eth_rxd_dly_offset);
+					 4, &dwc_priv->eth_clk_offset);
 	if (ret)
 		return dev_err_probe(&pdev->dev, ret,
-				     "can't get eth_rxd_dly_offset\n");
+				     "can't get eth_clk_offset\n");
 
-	regmap_write(eic7700_hsp_regmap, eth_rxd_dly_offset,
-		     eth_dly_param);
+	ret = of_property_read_u32_index(pdev->dev.of_node,
+					 "eswin,hsp-sp-csr",
+					 5, &dwc_priv->eth_rxd_offset);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret,
+				     "can't get eth_rxd_offset\n");
 
 	plat_dat->num_clks = ARRAY_SIZE(eic7700_clk_names);
 	plat_dat->clks = devm_kcalloc(&pdev->dev,
@@ -208,12 +287,27 @@ static int eic7700_dwmac_probe(struct platform_device *pdev)
 	plat_dat->exit = eic7700_dwmac_exit;
 	plat_dat->suspend = eic7700_dwmac_suspend;
 	plat_dat->resume = eic7700_dwmac_resume;
+	plat_dat->fix_mac_speed = eic7700_dwmac_fix_speed;
 
 	return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
 }
 
+static const struct eic7700_dwmac_data eic7700_dwmac_data = {
+	.rgmii_rx_clk_invert = false,
+};
+
+static const struct eic7700_dwmac_data eic7700_dwmac_data_clk_inversion = {
+	.rgmii_rx_clk_invert = true,
+};
+
 static const struct of_device_id eic7700_dwmac_match[] = {
-	{ .compatible = "eswin,eic7700-qos-eth" },
+	{	.compatible = "eswin,eic7700-qos-eth",
+		.data = &eic7700_dwmac_data,
+	},
+	{
+		.compatible = "eswin,eic7700-qos-eth-clk-inversion",
+		.data = &eic7700_dwmac_data_clk_inversion,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, eic7700_dwmac_match);
-- 
2.25.1


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Re: [PATCH net-next v3 2/3] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing

[Jakub Kicinski]

On Tue,  3 Mar 2026 14:17:08 +0800 lizhi2@eswincomputing.com wrote:
>  .../ethernet/stmicro/stmmac/dwmac-eic7700.c   | 180 +++++++++++++-----
>  1 file changed, 137 insertions(+), 43 deletions(-)

../drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c:290:33: error: assignment to ‘void (*)(void *, phy_interface_t,  int,  unsigned int)’ from incompatible pointer type ‘void (*)(void *, int,  unsigned int)’ [-Wincompatible-pointer-types]
  290 |         plat_dat->fix_mac_speed = eic7700_dwmac_fix_speed;
      |                                 ^
../drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c:129:13: note: ‘eic7700_dwmac_fix_speed’ declared here
  129 | static void eic7700_dwmac_fix_speed(void *priv, int speed, unsigned int mode)
      |             ^~~~~~~~~~~~~~~~~~~~~~~
-- 
pw-bot: cr

Re: [PATCH net-next v3 2/3] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing

[Jakub Kicinski]

On Tue,  3 Mar 2026 14:17:08 +0800 lizhi2@eswincomputing.com wrote:
>  .../ethernet/stmicro/stmmac/dwmac-eic7700.c   | 180 +++++++++++++-----
>  1 file changed, 137 insertions(+), 43 deletions(-)

../drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c:290:33: error: assignment to ‘void (*)(void *, phy_interface_t,  int,  unsigned int)’ from incompatible pointer type ‘void (*)(void *, int,  unsigned int)’ [-Wincompatible-pointer-types]
  290 |         plat_dat->fix_mac_speed = eic7700_dwmac_fix_speed;
      |                                 ^
../drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c:129:13: note: ‘eic7700_dwmac_fix_speed’ declared here
  129 | static void eic7700_dwmac_fix_speed(void *priv, int speed, unsigned int mode)
      |             ^~~~~~~~~~~~~~~~~~~~~~~
-- 
pw-bot: cr

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Re: [PATCH net-next v3 2/3] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing

[kernel test robot]

Hi,

kernel test robot noticed the following build errors:

[auto build test ERROR on net-next/main]

url:    https://github.com/intel-lab-lkp/linux/commits/lizhi2-eswincomputing-com/dt-bindings-ethernet-eswin-add-clock-sampling-control/20260303-142311
base:   net-next/main
patch link:    https://lore.kernel.org/r/20260303061711.895-1-lizhi2%40eswincomputing.com
patch subject: [PATCH net-next v3 2/3] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing
config: m68k-allmodconfig (https://download.01.org/0day-ci/archive/20260305/202603051555.5m64TOiy-lkp@intel.com/config)
compiler: m68k-linux-gcc (GCC) 15.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260305/202603051555.5m64TOiy-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603051555.5m64TOiy-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c: In function 'eic7700_dwmac_probe':
>> drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c:290:33: error: assignment to 'void (*)(void *, phy_interface_t,  int,  unsigned int)' from incompatible pointer type 'void (*)(void *, int,  unsigned int)' [-Wincompatible-pointer-types]
     290 |         plat_dat->fix_mac_speed = eic7700_dwmac_fix_speed;
         |                                 ^
   drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c:129:13: note: 'eic7700_dwmac_fix_speed' declared here
     129 | static void eic7700_dwmac_fix_speed(void *priv, int speed, unsigned int mode)
         |             ^~~~~~~~~~~~~~~~~~~~~~~


vim +290 drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c

   149	
   150	static int eic7700_dwmac_probe(struct platform_device *pdev)
   151	{
   152		const struct eic7700_dwmac_data *data;
   153		struct plat_stmmacenet_data *plat_dat;
   154		struct stmmac_resources stmmac_res;
   155		struct eic7700_qos_priv *dwc_priv;
   156		u32 delay_ps, val;
   157		int i, ret;
   158	
   159		ret = stmmac_get_platform_resources(pdev, &stmmac_res);
   160		if (ret)
   161			return dev_err_probe(&pdev->dev, ret,
   162					"failed to get resources\n");
   163	
   164		plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
   165		if (IS_ERR(plat_dat))
   166			return dev_err_probe(&pdev->dev, PTR_ERR(plat_dat),
   167					"dt configuration failed\n");
   168	
   169		dwc_priv = devm_kzalloc(&pdev->dev, sizeof(*dwc_priv), GFP_KERNEL);
   170		if (!dwc_priv)
   171			return -ENOMEM;
   172	
   173		dwc_priv->dev = &pdev->dev;
   174	
   175		data = device_get_match_data(&pdev->dev);
   176		if (!data)
   177			return dev_err_probe(&pdev->dev,
   178					     -EINVAL, "no match data found\n");
   179	
   180		dwc_priv->eth_rx_clk_inv = data->rgmii_rx_clk_invert;
   181	
   182		/* Read rx-internal-delay-ps and update rx_clk delay */
   183		if (!of_property_read_u32(pdev->dev.of_node,
   184					  "rx-internal-delay-ps", &delay_ps)) {
   185			if (delay_ps % EIC7700_DELAY_STEP_PS)
   186				return dev_err_probe(&pdev->dev, -EINVAL,
   187					"rx delay must be multiple of %dps\n",
   188					EIC7700_DELAY_STEP_PS);
   189	
   190			if (delay_ps > EIC7700_MAX_DELAY_PS)
   191				return dev_err_probe(&pdev->dev, -EINVAL,
   192					"rx delay out of range\n");
   193	
   194			val = delay_ps / EIC7700_DELAY_STEP_PS;
   195	
   196			dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_RX_ADJ_DELAY;
   197			dwc_priv->eth_clk_dly_param |=
   198					 FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val);
   199		}
   200	
   201		/* Read tx-internal-delay-ps and update tx_clk delay */
   202		if (!of_property_read_u32(pdev->dev.of_node,
   203					  "tx-internal-delay-ps", &delay_ps)) {
   204			if (delay_ps % EIC7700_DELAY_STEP_PS)
   205				return dev_err_probe(&pdev->dev, -EINVAL,
   206					"tx delay must be multiple of %dps\n",
   207					EIC7700_DELAY_STEP_PS);
   208	
   209			if (delay_ps > EIC7700_MAX_DELAY_PS)
   210				return dev_err_probe(&pdev->dev, -EINVAL,
   211					"tx delay out of range\n");
   212	
   213			val = delay_ps / EIC7700_DELAY_STEP_PS;
   214	
   215			dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_TX_ADJ_DELAY;
   216			dwc_priv->eth_clk_dly_param |=
   217					 FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val);
   218		}
   219	
   220		dwc_priv->eic7700_hsp_regmap =
   221				syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
   222								"eswin,hsp-sp-csr");
   223		if (IS_ERR(dwc_priv->eic7700_hsp_regmap))
   224			return dev_err_probe(&pdev->dev,
   225					PTR_ERR(dwc_priv->eic7700_hsp_regmap),
   226					"Failed to get hsp-sp-csr regmap\n");
   227	
   228		ret = of_property_read_u32_index(pdev->dev.of_node,
   229						 "eswin,hsp-sp-csr",
   230						 1, &dwc_priv->eth_phy_ctrl_offset);
   231		if (ret)
   232			return dev_err_probe(&pdev->dev, ret,
   233					     "can't get eth_phy_ctrl_offset\n");
   234	
   235		ret = of_property_read_u32_index(pdev->dev.of_node,
   236						 "eswin,hsp-sp-csr",
   237						 2, &dwc_priv->eth_axi_lp_ctrl_offset);
   238		if (ret)
   239			return dev_err_probe(&pdev->dev, ret,
   240					     "can't get eth_axi_lp_ctrl_offset\n");
   241	
   242		ret = of_property_read_u32_index(pdev->dev.of_node,
   243						 "eswin,hsp-sp-csr",
   244						 3, &dwc_priv->eth_txd_offset);
   245		if (ret)
   246			return dev_err_probe(&pdev->dev, ret,
   247					     "can't get eth_txd_offset\n");
   248	
   249		ret = of_property_read_u32_index(pdev->dev.of_node,
   250						 "eswin,hsp-sp-csr",
   251						 4, &dwc_priv->eth_clk_offset);
   252		if (ret)
   253			return dev_err_probe(&pdev->dev, ret,
   254					     "can't get eth_clk_offset\n");
   255	
   256		ret = of_property_read_u32_index(pdev->dev.of_node,
   257						 "eswin,hsp-sp-csr",
   258						 5, &dwc_priv->eth_rxd_offset);
   259		if (ret)
   260			return dev_err_probe(&pdev->dev, ret,
   261					     "can't get eth_rxd_offset\n");
   262	
   263		plat_dat->num_clks = ARRAY_SIZE(eic7700_clk_names);
   264		plat_dat->clks = devm_kcalloc(&pdev->dev,
   265					      plat_dat->num_clks,
   266					      sizeof(*plat_dat->clks),
   267					      GFP_KERNEL);
   268		if (!plat_dat->clks)
   269			return -ENOMEM;
   270	
   271		for (i = 0; i < ARRAY_SIZE(eic7700_clk_names); i++)
   272			plat_dat->clks[i].id = eic7700_clk_names[i];
   273	
   274		ret = devm_clk_bulk_get_optional(&pdev->dev,
   275						 plat_dat->num_clks,
   276						 plat_dat->clks);
   277		if (ret)
   278			return dev_err_probe(&pdev->dev, ret,
   279					     "Failed to get clocks\n");
   280	
   281		plat_dat->clk_tx_i = stmmac_pltfr_find_clk(plat_dat, "tx");
   282		plat_dat->set_clk_tx_rate = stmmac_set_clk_tx_rate;
   283		plat_dat->clks_config = eic7700_clks_config;
   284		plat_dat->bsp_priv = dwc_priv;
   285		dwc_priv->plat_dat = plat_dat;
   286		plat_dat->init = eic7700_dwmac_init;
   287		plat_dat->exit = eic7700_dwmac_exit;
   288		plat_dat->suspend = eic7700_dwmac_suspend;
   289		plat_dat->resume = eic7700_dwmac_resume;
 > 290		plat_dat->fix_mac_speed = eic7700_dwmac_fix_speed;
   291	
   292		return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
   293	}
   294	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH net-next v3 2/3] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing

[kernel test robot]

Hi,

kernel test robot noticed the following build errors:

[auto build test ERROR on net-next/main]

url:    https://github.com/intel-lab-lkp/linux/commits/lizhi2-eswincomputing-com/dt-bindings-ethernet-eswin-add-clock-sampling-control/20260303-142311
base:   net-next/main
patch link:    https://lore.kernel.org/r/20260303061711.895-1-lizhi2%40eswincomputing.com
patch subject: [PATCH net-next v3 2/3] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing
config: m68k-allmodconfig (https://download.01.org/0day-ci/archive/20260305/202603051555.5m64TOiy-lkp@intel.com/config)
compiler: m68k-linux-gcc (GCC) 15.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260305/202603051555.5m64TOiy-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603051555.5m64TOiy-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c: In function 'eic7700_dwmac_probe':
>> drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c:290:33: error: assignment to 'void (*)(void *, phy_interface_t,  int,  unsigned int)' from incompatible pointer type 'void (*)(void *, int,  unsigned int)' [-Wincompatible-pointer-types]
     290 |         plat_dat->fix_mac_speed = eic7700_dwmac_fix_speed;
         |                                 ^
   drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c:129:13: note: 'eic7700_dwmac_fix_speed' declared here
     129 | static void eic7700_dwmac_fix_speed(void *priv, int speed, unsigned int mode)
         |             ^~~~~~~~~~~~~~~~~~~~~~~


vim +290 drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c

   149	
   150	static int eic7700_dwmac_probe(struct platform_device *pdev)
   151	{
   152		const struct eic7700_dwmac_data *data;
   153		struct plat_stmmacenet_data *plat_dat;
   154		struct stmmac_resources stmmac_res;
   155		struct eic7700_qos_priv *dwc_priv;
   156		u32 delay_ps, val;
   157		int i, ret;
   158	
   159		ret = stmmac_get_platform_resources(pdev, &stmmac_res);
   160		if (ret)
   161			return dev_err_probe(&pdev->dev, ret,
   162					"failed to get resources\n");
   163	
   164		plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
   165		if (IS_ERR(plat_dat))
   166			return dev_err_probe(&pdev->dev, PTR_ERR(plat_dat),
   167					"dt configuration failed\n");
   168	
   169		dwc_priv = devm_kzalloc(&pdev->dev, sizeof(*dwc_priv), GFP_KERNEL);
   170		if (!dwc_priv)
   171			return -ENOMEM;
   172	
   173		dwc_priv->dev = &pdev->dev;
   174	
   175		data = device_get_match_data(&pdev->dev);
   176		if (!data)
   177			return dev_err_probe(&pdev->dev,
   178					     -EINVAL, "no match data found\n");
   179	
   180		dwc_priv->eth_rx_clk_inv = data->rgmii_rx_clk_invert;
   181	
   182		/* Read rx-internal-delay-ps and update rx_clk delay */
   183		if (!of_property_read_u32(pdev->dev.of_node,
   184					  "rx-internal-delay-ps", &delay_ps)) {
   185			if (delay_ps % EIC7700_DELAY_STEP_PS)
   186				return dev_err_probe(&pdev->dev, -EINVAL,
   187					"rx delay must be multiple of %dps\n",
   188					EIC7700_DELAY_STEP_PS);
   189	
   190			if (delay_ps > EIC7700_MAX_DELAY_PS)
   191				return dev_err_probe(&pdev->dev, -EINVAL,
   192					"rx delay out of range\n");
   193	
   194			val = delay_ps / EIC7700_DELAY_STEP_PS;
   195	
   196			dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_RX_ADJ_DELAY;
   197			dwc_priv->eth_clk_dly_param |=
   198					 FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val);
   199		}
   200	
   201		/* Read tx-internal-delay-ps and update tx_clk delay */
   202		if (!of_property_read_u32(pdev->dev.of_node,
   203					  "tx-internal-delay-ps", &delay_ps)) {
   204			if (delay_ps % EIC7700_DELAY_STEP_PS)
   205				return dev_err_probe(&pdev->dev, -EINVAL,
   206					"tx delay must be multiple of %dps\n",
   207					EIC7700_DELAY_STEP_PS);
   208	
   209			if (delay_ps > EIC7700_MAX_DELAY_PS)
   210				return dev_err_probe(&pdev->dev, -EINVAL,
   211					"tx delay out of range\n");
   212	
   213			val = delay_ps / EIC7700_DELAY_STEP_PS;
   214	
   215			dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_TX_ADJ_DELAY;
   216			dwc_priv->eth_clk_dly_param |=
   217					 FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val);
   218		}
   219	
   220		dwc_priv->eic7700_hsp_regmap =
   221				syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
   222								"eswin,hsp-sp-csr");
   223		if (IS_ERR(dwc_priv->eic7700_hsp_regmap))
   224			return dev_err_probe(&pdev->dev,
   225					PTR_ERR(dwc_priv->eic7700_hsp_regmap),
   226					"Failed to get hsp-sp-csr regmap\n");
   227	
   228		ret = of_property_read_u32_index(pdev->dev.of_node,
   229						 "eswin,hsp-sp-csr",
   230						 1, &dwc_priv->eth_phy_ctrl_offset);
   231		if (ret)
   232			return dev_err_probe(&pdev->dev, ret,
   233					     "can't get eth_phy_ctrl_offset\n");
   234	
   235		ret = of_property_read_u32_index(pdev->dev.of_node,
   236						 "eswin,hsp-sp-csr",
   237						 2, &dwc_priv->eth_axi_lp_ctrl_offset);
   238		if (ret)
   239			return dev_err_probe(&pdev->dev, ret,
   240					     "can't get eth_axi_lp_ctrl_offset\n");
   241	
   242		ret = of_property_read_u32_index(pdev->dev.of_node,
   243						 "eswin,hsp-sp-csr",
   244						 3, &dwc_priv->eth_txd_offset);
   245		if (ret)
   246			return dev_err_probe(&pdev->dev, ret,
   247					     "can't get eth_txd_offset\n");
   248	
   249		ret = of_property_read_u32_index(pdev->dev.of_node,
   250						 "eswin,hsp-sp-csr",
   251						 4, &dwc_priv->eth_clk_offset);
   252		if (ret)
   253			return dev_err_probe(&pdev->dev, ret,
   254					     "can't get eth_clk_offset\n");
   255	
   256		ret = of_property_read_u32_index(pdev->dev.of_node,
   257						 "eswin,hsp-sp-csr",
   258						 5, &dwc_priv->eth_rxd_offset);
   259		if (ret)
   260			return dev_err_probe(&pdev->dev, ret,
   261					     "can't get eth_rxd_offset\n");
   262	
   263		plat_dat->num_clks = ARRAY_SIZE(eic7700_clk_names);
   264		plat_dat->clks = devm_kcalloc(&pdev->dev,
   265					      plat_dat->num_clks,
   266					      sizeof(*plat_dat->clks),
   267					      GFP_KERNEL);
   268		if (!plat_dat->clks)
   269			return -ENOMEM;
   270	
   271		for (i = 0; i < ARRAY_SIZE(eic7700_clk_names); i++)
   272			plat_dat->clks[i].id = eic7700_clk_names[i];
   273	
   274		ret = devm_clk_bulk_get_optional(&pdev->dev,
   275						 plat_dat->num_clks,
   276						 plat_dat->clks);
   277		if (ret)
   278			return dev_err_probe(&pdev->dev, ret,
   279					     "Failed to get clocks\n");
   280	
   281		plat_dat->clk_tx_i = stmmac_pltfr_find_clk(plat_dat, "tx");
   282		plat_dat->set_clk_tx_rate = stmmac_set_clk_tx_rate;
   283		plat_dat->clks_config = eic7700_clks_config;
   284		plat_dat->bsp_priv = dwc_priv;
   285		dwc_priv->plat_dat = plat_dat;
   286		plat_dat->init = eic7700_dwmac_init;
   287		plat_dat->exit = eic7700_dwmac_exit;
   288		plat_dat->suspend = eic7700_dwmac_suspend;
   289		plat_dat->resume = eic7700_dwmac_resume;
 > 290		plat_dat->fix_mac_speed = eic7700_dwmac_fix_speed;
   291	
   292		return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
   293	}
   294	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
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Re: [PATCH net-next v3 2/3] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing

[kernel test robot]

Hi,

kernel test robot noticed the following build errors:

[auto build test ERROR on net-next/main]

url:    https://github.com/intel-lab-lkp/linux/commits/lizhi2-eswincomputing-com/dt-bindings-ethernet-eswin-add-clock-sampling-control/20260303-142311
base:   net-next/main
patch link:    https://lore.kernel.org/r/20260303061711.895-1-lizhi2%40eswincomputing.com
patch subject: [PATCH net-next v3 2/3] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing
config: hexagon-allmodconfig (https://download.01.org/0day-ci/archive/20260305/202603051549.4Mb0ZZjM-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260305/202603051549.4Mb0ZZjM-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603051549.4Mb0ZZjM-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c:290:26: error: incompatible function pointer types assigning to 'void (*)(void *, phy_interface_t, int, unsigned int)' from 'void (void *, int, unsigned int)' [-Wincompatible-function-pointer-types]
     290 |         plat_dat->fix_mac_speed = eic7700_dwmac_fix_speed;
         |                                 ^ ~~~~~~~~~~~~~~~~~~~~~~~
   1 error generated.


vim +290 drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c

   149	
   150	static int eic7700_dwmac_probe(struct platform_device *pdev)
   151	{
   152		const struct eic7700_dwmac_data *data;
   153		struct plat_stmmacenet_data *plat_dat;
   154		struct stmmac_resources stmmac_res;
   155		struct eic7700_qos_priv *dwc_priv;
   156		u32 delay_ps, val;
   157		int i, ret;
   158	
   159		ret = stmmac_get_platform_resources(pdev, &stmmac_res);
   160		if (ret)
   161			return dev_err_probe(&pdev->dev, ret,
   162					"failed to get resources\n");
   163	
   164		plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
   165		if (IS_ERR(plat_dat))
   166			return dev_err_probe(&pdev->dev, PTR_ERR(plat_dat),
   167					"dt configuration failed\n");
   168	
   169		dwc_priv = devm_kzalloc(&pdev->dev, sizeof(*dwc_priv), GFP_KERNEL);
   170		if (!dwc_priv)
   171			return -ENOMEM;
   172	
   173		dwc_priv->dev = &pdev->dev;
   174	
   175		data = device_get_match_data(&pdev->dev);
   176		if (!data)
   177			return dev_err_probe(&pdev->dev,
   178					     -EINVAL, "no match data found\n");
   179	
   180		dwc_priv->eth_rx_clk_inv = data->rgmii_rx_clk_invert;
   181	
   182		/* Read rx-internal-delay-ps and update rx_clk delay */
   183		if (!of_property_read_u32(pdev->dev.of_node,
   184					  "rx-internal-delay-ps", &delay_ps)) {
   185			if (delay_ps % EIC7700_DELAY_STEP_PS)
   186				return dev_err_probe(&pdev->dev, -EINVAL,
   187					"rx delay must be multiple of %dps\n",
   188					EIC7700_DELAY_STEP_PS);
   189	
   190			if (delay_ps > EIC7700_MAX_DELAY_PS)
   191				return dev_err_probe(&pdev->dev, -EINVAL,
   192					"rx delay out of range\n");
   193	
   194			val = delay_ps / EIC7700_DELAY_STEP_PS;
   195	
   196			dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_RX_ADJ_DELAY;
   197			dwc_priv->eth_clk_dly_param |=
   198					 FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val);
   199		}
   200	
   201		/* Read tx-internal-delay-ps and update tx_clk delay */
   202		if (!of_property_read_u32(pdev->dev.of_node,
   203					  "tx-internal-delay-ps", &delay_ps)) {
   204			if (delay_ps % EIC7700_DELAY_STEP_PS)
   205				return dev_err_probe(&pdev->dev, -EINVAL,
   206					"tx delay must be multiple of %dps\n",
   207					EIC7700_DELAY_STEP_PS);
   208	
   209			if (delay_ps > EIC7700_MAX_DELAY_PS)
   210				return dev_err_probe(&pdev->dev, -EINVAL,
   211					"tx delay out of range\n");
   212	
   213			val = delay_ps / EIC7700_DELAY_STEP_PS;
   214	
   215			dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_TX_ADJ_DELAY;
   216			dwc_priv->eth_clk_dly_param |=
   217					 FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val);
   218		}
   219	
   220		dwc_priv->eic7700_hsp_regmap =
   221				syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
   222								"eswin,hsp-sp-csr");
   223		if (IS_ERR(dwc_priv->eic7700_hsp_regmap))
   224			return dev_err_probe(&pdev->dev,
   225					PTR_ERR(dwc_priv->eic7700_hsp_regmap),
   226					"Failed to get hsp-sp-csr regmap\n");
   227	
   228		ret = of_property_read_u32_index(pdev->dev.of_node,
   229						 "eswin,hsp-sp-csr",
   230						 1, &dwc_priv->eth_phy_ctrl_offset);
   231		if (ret)
   232			return dev_err_probe(&pdev->dev, ret,
   233					     "can't get eth_phy_ctrl_offset\n");
   234	
   235		ret = of_property_read_u32_index(pdev->dev.of_node,
   236						 "eswin,hsp-sp-csr",
   237						 2, &dwc_priv->eth_axi_lp_ctrl_offset);
   238		if (ret)
   239			return dev_err_probe(&pdev->dev, ret,
   240					     "can't get eth_axi_lp_ctrl_offset\n");
   241	
   242		ret = of_property_read_u32_index(pdev->dev.of_node,
   243						 "eswin,hsp-sp-csr",
   244						 3, &dwc_priv->eth_txd_offset);
   245		if (ret)
   246			return dev_err_probe(&pdev->dev, ret,
   247					     "can't get eth_txd_offset\n");
   248	
   249		ret = of_property_read_u32_index(pdev->dev.of_node,
   250						 "eswin,hsp-sp-csr",
   251						 4, &dwc_priv->eth_clk_offset);
   252		if (ret)
   253			return dev_err_probe(&pdev->dev, ret,
   254					     "can't get eth_clk_offset\n");
   255	
   256		ret = of_property_read_u32_index(pdev->dev.of_node,
   257						 "eswin,hsp-sp-csr",
   258						 5, &dwc_priv->eth_rxd_offset);
   259		if (ret)
   260			return dev_err_probe(&pdev->dev, ret,
   261					     "can't get eth_rxd_offset\n");
   262	
   263		plat_dat->num_clks = ARRAY_SIZE(eic7700_clk_names);
   264		plat_dat->clks = devm_kcalloc(&pdev->dev,
   265					      plat_dat->num_clks,
   266					      sizeof(*plat_dat->clks),
   267					      GFP_KERNEL);
   268		if (!plat_dat->clks)
   269			return -ENOMEM;
   270	
   271		for (i = 0; i < ARRAY_SIZE(eic7700_clk_names); i++)
   272			plat_dat->clks[i].id = eic7700_clk_names[i];
   273	
   274		ret = devm_clk_bulk_get_optional(&pdev->dev,
   275						 plat_dat->num_clks,
   276						 plat_dat->clks);
   277		if (ret)
   278			return dev_err_probe(&pdev->dev, ret,
   279					     "Failed to get clocks\n");
   280	
   281		plat_dat->clk_tx_i = stmmac_pltfr_find_clk(plat_dat, "tx");
   282		plat_dat->set_clk_tx_rate = stmmac_set_clk_tx_rate;
   283		plat_dat->clks_config = eic7700_clks_config;
   284		plat_dat->bsp_priv = dwc_priv;
   285		dwc_priv->plat_dat = plat_dat;
   286		plat_dat->init = eic7700_dwmac_init;
   287		plat_dat->exit = eic7700_dwmac_exit;
   288		plat_dat->suspend = eic7700_dwmac_suspend;
   289		plat_dat->resume = eic7700_dwmac_resume;
 > 290		plat_dat->fix_mac_speed = eic7700_dwmac_fix_speed;
   291	
   292		return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
   293	}
   294	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH net-next v3 2/3] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing

[kernel test robot]

Hi,

kernel test robot noticed the following build errors:

[auto build test ERROR on net-next/main]

url:    https://github.com/intel-lab-lkp/linux/commits/lizhi2-eswincomputing-com/dt-bindings-ethernet-eswin-add-clock-sampling-control/20260303-142311
base:   net-next/main
patch link:    https://lore.kernel.org/r/20260303061711.895-1-lizhi2%40eswincomputing.com
patch subject: [PATCH net-next v3 2/3] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing
config: hexagon-allmodconfig (https://download.01.org/0day-ci/archive/20260305/202603051549.4Mb0ZZjM-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260305/202603051549.4Mb0ZZjM-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603051549.4Mb0ZZjM-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c:290:26: error: incompatible function pointer types assigning to 'void (*)(void *, phy_interface_t, int, unsigned int)' from 'void (void *, int, unsigned int)' [-Wincompatible-function-pointer-types]
     290 |         plat_dat->fix_mac_speed = eic7700_dwmac_fix_speed;
         |                                 ^ ~~~~~~~~~~~~~~~~~~~~~~~
   1 error generated.


vim +290 drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c

   149	
   150	static int eic7700_dwmac_probe(struct platform_device *pdev)
   151	{
   152		const struct eic7700_dwmac_data *data;
   153		struct plat_stmmacenet_data *plat_dat;
   154		struct stmmac_resources stmmac_res;
   155		struct eic7700_qos_priv *dwc_priv;
   156		u32 delay_ps, val;
   157		int i, ret;
   158	
   159		ret = stmmac_get_platform_resources(pdev, &stmmac_res);
   160		if (ret)
   161			return dev_err_probe(&pdev->dev, ret,
   162					"failed to get resources\n");
   163	
   164		plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
   165		if (IS_ERR(plat_dat))
   166			return dev_err_probe(&pdev->dev, PTR_ERR(plat_dat),
   167					"dt configuration failed\n");
   168	
   169		dwc_priv = devm_kzalloc(&pdev->dev, sizeof(*dwc_priv), GFP_KERNEL);
   170		if (!dwc_priv)
   171			return -ENOMEM;
   172	
   173		dwc_priv->dev = &pdev->dev;
   174	
   175		data = device_get_match_data(&pdev->dev);
   176		if (!data)
   177			return dev_err_probe(&pdev->dev,
   178					     -EINVAL, "no match data found\n");
   179	
   180		dwc_priv->eth_rx_clk_inv = data->rgmii_rx_clk_invert;
   181	
   182		/* Read rx-internal-delay-ps and update rx_clk delay */
   183		if (!of_property_read_u32(pdev->dev.of_node,
   184					  "rx-internal-delay-ps", &delay_ps)) {
   185			if (delay_ps % EIC7700_DELAY_STEP_PS)
   186				return dev_err_probe(&pdev->dev, -EINVAL,
   187					"rx delay must be multiple of %dps\n",
   188					EIC7700_DELAY_STEP_PS);
   189	
   190			if (delay_ps > EIC7700_MAX_DELAY_PS)
   191				return dev_err_probe(&pdev->dev, -EINVAL,
   192					"rx delay out of range\n");
   193	
   194			val = delay_ps / EIC7700_DELAY_STEP_PS;
   195	
   196			dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_RX_ADJ_DELAY;
   197			dwc_priv->eth_clk_dly_param |=
   198					 FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val);
   199		}
   200	
   201		/* Read tx-internal-delay-ps and update tx_clk delay */
   202		if (!of_property_read_u32(pdev->dev.of_node,
   203					  "tx-internal-delay-ps", &delay_ps)) {
   204			if (delay_ps % EIC7700_DELAY_STEP_PS)
   205				return dev_err_probe(&pdev->dev, -EINVAL,
   206					"tx delay must be multiple of %dps\n",
   207					EIC7700_DELAY_STEP_PS);
   208	
   209			if (delay_ps > EIC7700_MAX_DELAY_PS)
   210				return dev_err_probe(&pdev->dev, -EINVAL,
   211					"tx delay out of range\n");
   212	
   213			val = delay_ps / EIC7700_DELAY_STEP_PS;
   214	
   215			dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_TX_ADJ_DELAY;
   216			dwc_priv->eth_clk_dly_param |=
   217					 FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val);
   218		}
   219	
   220		dwc_priv->eic7700_hsp_regmap =
   221				syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
   222								"eswin,hsp-sp-csr");
   223		if (IS_ERR(dwc_priv->eic7700_hsp_regmap))
   224			return dev_err_probe(&pdev->dev,
   225					PTR_ERR(dwc_priv->eic7700_hsp_regmap),
   226					"Failed to get hsp-sp-csr regmap\n");
   227	
   228		ret = of_property_read_u32_index(pdev->dev.of_node,
   229						 "eswin,hsp-sp-csr",
   230						 1, &dwc_priv->eth_phy_ctrl_offset);
   231		if (ret)
   232			return dev_err_probe(&pdev->dev, ret,
   233					     "can't get eth_phy_ctrl_offset\n");
   234	
   235		ret = of_property_read_u32_index(pdev->dev.of_node,
   236						 "eswin,hsp-sp-csr",
   237						 2, &dwc_priv->eth_axi_lp_ctrl_offset);
   238		if (ret)
   239			return dev_err_probe(&pdev->dev, ret,
   240					     "can't get eth_axi_lp_ctrl_offset\n");
   241	
   242		ret = of_property_read_u32_index(pdev->dev.of_node,
   243						 "eswin,hsp-sp-csr",
   244						 3, &dwc_priv->eth_txd_offset);
   245		if (ret)
   246			return dev_err_probe(&pdev->dev, ret,
   247					     "can't get eth_txd_offset\n");
   248	
   249		ret = of_property_read_u32_index(pdev->dev.of_node,
   250						 "eswin,hsp-sp-csr",
   251						 4, &dwc_priv->eth_clk_offset);
   252		if (ret)
   253			return dev_err_probe(&pdev->dev, ret,
   254					     "can't get eth_clk_offset\n");
   255	
   256		ret = of_property_read_u32_index(pdev->dev.of_node,
   257						 "eswin,hsp-sp-csr",
   258						 5, &dwc_priv->eth_rxd_offset);
   259		if (ret)
   260			return dev_err_probe(&pdev->dev, ret,
   261					     "can't get eth_rxd_offset\n");
   262	
   263		plat_dat->num_clks = ARRAY_SIZE(eic7700_clk_names);
   264		plat_dat->clks = devm_kcalloc(&pdev->dev,
   265					      plat_dat->num_clks,
   266					      sizeof(*plat_dat->clks),
   267					      GFP_KERNEL);
   268		if (!plat_dat->clks)
   269			return -ENOMEM;
   270	
   271		for (i = 0; i < ARRAY_SIZE(eic7700_clk_names); i++)
   272			plat_dat->clks[i].id = eic7700_clk_names[i];
   273	
   274		ret = devm_clk_bulk_get_optional(&pdev->dev,
   275						 plat_dat->num_clks,
   276						 plat_dat->clks);
   277		if (ret)
   278			return dev_err_probe(&pdev->dev, ret,
   279					     "Failed to get clocks\n");
   280	
   281		plat_dat->clk_tx_i = stmmac_pltfr_find_clk(plat_dat, "tx");
   282		plat_dat->set_clk_tx_rate = stmmac_set_clk_tx_rate;
   283		plat_dat->clks_config = eic7700_clks_config;
   284		plat_dat->bsp_priv = dwc_priv;
   285		dwc_priv->plat_dat = plat_dat;
   286		plat_dat->init = eic7700_dwmac_init;
   287		plat_dat->exit = eic7700_dwmac_exit;
   288		plat_dat->suspend = eic7700_dwmac_suspend;
   289		plat_dat->resume = eic7700_dwmac_resume;
 > 290		plat_dat->fix_mac_speed = eic7700_dwmac_fix_speed;
   291	
   292		return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
   293	}
   294	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

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[PATCH net-next v3 3/3] riscv: dts: eswin: eic7700-hifive-premier-p550: enable Ethernet controller

[lizhi2]

From: Zhi Li <lizhi2@eswincomputing.com>

Enable the on-board Gigabit Ethernet controller on the
HiFive Premier P550 development board.

Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
---
 .../dts/eswin/eic7700-hifive-premier-p550.dts | 50 +++++++++++++++++
 arch/riscv/boot/dts/eswin/eic7700.dtsi        | 54 +++++++++++++++++++
 2 files changed, 104 insertions(+)

diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index 131ed1fc6b2e..d558f0fdfb38 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -13,6 +13,8 @@ / {
 
 	aliases {
 		serial0 = &uart0;
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
 	};
 
 	chosen {
@@ -20,6 +22,54 @@ chosen {
 	};
 };
 
+&gmac0 {
+	phy-handle = <&gmac0_phy0>;
+	phy-mode = "rgmii-id";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gpio106_pins>;
+	rx-internal-delay-ps = <20>;
+	tx-internal-delay-ps = <100>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		gmac0_phy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-id001c.c916";
+			reg = <0>;
+			reset-gpios = <&gpioD 10 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <80000>;
+		};
+	};
+};
+
+&gmac1 {
+	phy-handle = <&gmac1_phy0>;
+	phy-mode = "rgmii-rxid";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gpio111_pins>;
+	rx-internal-delay-ps = <200>;
+	tx-internal-delay-ps = <200>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		gmac1_phy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-id001c.c916";
+			reg = <0>;
+			reset-gpios = <&gpioD 15 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <80000>;
+		};
+	};
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index c3ed93008bca..c6f504f0d096 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -5,6 +5,8 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
+
 / {
 	#address-cells = <2>;
 	#size-cells = <2>;
@@ -295,6 +297,58 @@ uart4: serial@50940000 {
 			status = "disabled";
 		};
 
+		gmac0: ethernet@50400000 {
+			compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20";
+			reg = <0x0 0x50400000 0x0 0x10000>;
+			interrupts = <61>;
+			interrupt-names = "macirq";
+			clocks = <&clk 186>,
+				 <&clk 171>,
+				 <&clk 40>,
+				 <&clk 193>;
+			clock-names = "axi", "cfg", "stmmaceth", "tx";
+			resets = <&reset 95>;
+			reset-names = "stmmaceth";
+			eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x114 0x118 0x11c>;
+			snps,aal;
+			snps,fixed-burst;
+			snps,tso;
+			snps,axi-config = <&stmmac_axi_setup_gmac0>;
+			status = "disabled";
+
+			stmmac_axi_setup_gmac0: stmmac-axi-config {
+				snps,blen = <0 0 0 0 16 8 4>;
+				snps,rd_osr_lmt = <2>;
+				snps,wr_osr_lmt = <2>;
+			};
+		};
+
+		gmac1: ethernet@50410000 {
+			compatible = "eswin,eic7700-qos-eth-clk-inversion", "snps,dwmac-5.20";
+			reg = <0x0 0x50410000 0x0 0x10000>;
+			interrupts = <70>;
+			interrupt-names = "macirq";
+			clocks = <&clk 186>,
+				 <&clk 171>,
+				 <&clk 40>,
+				 <&clk 194>;
+			clock-names = "axi", "cfg", "stmmaceth", "tx";
+			resets = <&reset 94>;
+			reset-names = "stmmaceth";
+			eswin,hsp-sp-csr = <&hsp_sp_csr 0x200 0x208 0x214 0x218 0x21c>;
+			snps,aal;
+			snps,fixed-burst;
+			snps,tso;
+			snps,axi-config = <&stmmac_axi_setup_gmac1>;
+			status = "disabled";
+
+			stmmac_axi_setup_gmac1: stmmac-axi-config {
+				snps,blen = <0 0 0 0 16 8 4>;
+				snps,rd_osr_lmt = <2>;
+				snps,wr_osr_lmt = <2>;
+			};
+		};
+
 		gpio@51600000 {
 			compatible = "snps,dw-apb-gpio";
 			reg = <0x0 0x51600000 0x0 0x80>;
-- 
2.25.1

[PATCH net-next v3 3/3] riscv: dts: eswin: eic7700-hifive-premier-p550: enable Ethernet controller

[lizhi2]

From: Zhi Li <lizhi2@eswincomputing.com>

Enable the on-board Gigabit Ethernet controller on the
HiFive Premier P550 development board.

Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
---
 .../dts/eswin/eic7700-hifive-premier-p550.dts | 50 +++++++++++++++++
 arch/riscv/boot/dts/eswin/eic7700.dtsi        | 54 +++++++++++++++++++
 2 files changed, 104 insertions(+)

diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index 131ed1fc6b2e..d558f0fdfb38 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -13,6 +13,8 @@ / {
 
 	aliases {
 		serial0 = &uart0;
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
 	};
 
 	chosen {
@@ -20,6 +22,54 @@ chosen {
 	};
 };
 
+&gmac0 {
+	phy-handle = <&gmac0_phy0>;
+	phy-mode = "rgmii-id";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gpio106_pins>;
+	rx-internal-delay-ps = <20>;
+	tx-internal-delay-ps = <100>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		gmac0_phy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-id001c.c916";
+			reg = <0>;
+			reset-gpios = <&gpioD 10 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <80000>;
+		};
+	};
+};
+
+&gmac1 {
+	phy-handle = <&gmac1_phy0>;
+	phy-mode = "rgmii-rxid";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gpio111_pins>;
+	rx-internal-delay-ps = <200>;
+	tx-internal-delay-ps = <200>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		gmac1_phy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-id001c.c916";
+			reg = <0>;
+			reset-gpios = <&gpioD 15 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <80000>;
+		};
+	};
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index c3ed93008bca..c6f504f0d096 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -5,6 +5,8 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
+
 / {
 	#address-cells = <2>;
 	#size-cells = <2>;
@@ -295,6 +297,58 @@ uart4: serial@50940000 {
 			status = "disabled";
 		};
 
+		gmac0: ethernet@50400000 {
+			compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20";
+			reg = <0x0 0x50400000 0x0 0x10000>;
+			interrupts = <61>;
+			interrupt-names = "macirq";
+			clocks = <&clk 186>,
+				 <&clk 171>,
+				 <&clk 40>,
+				 <&clk 193>;
+			clock-names = "axi", "cfg", "stmmaceth", "tx";
+			resets = <&reset 95>;
+			reset-names = "stmmaceth";
+			eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x114 0x118 0x11c>;
+			snps,aal;
+			snps,fixed-burst;
+			snps,tso;
+			snps,axi-config = <&stmmac_axi_setup_gmac0>;
+			status = "disabled";
+
+			stmmac_axi_setup_gmac0: stmmac-axi-config {
+				snps,blen = <0 0 0 0 16 8 4>;
+				snps,rd_osr_lmt = <2>;
+				snps,wr_osr_lmt = <2>;
+			};
+		};
+
+		gmac1: ethernet@50410000 {
+			compatible = "eswin,eic7700-qos-eth-clk-inversion", "snps,dwmac-5.20";
+			reg = <0x0 0x50410000 0x0 0x10000>;
+			interrupts = <70>;
+			interrupt-names = "macirq";
+			clocks = <&clk 186>,
+				 <&clk 171>,
+				 <&clk 40>,
+				 <&clk 194>;
+			clock-names = "axi", "cfg", "stmmaceth", "tx";
+			resets = <&reset 94>;
+			reset-names = "stmmaceth";
+			eswin,hsp-sp-csr = <&hsp_sp_csr 0x200 0x208 0x214 0x218 0x21c>;
+			snps,aal;
+			snps,fixed-burst;
+			snps,tso;
+			snps,axi-config = <&stmmac_axi_setup_gmac1>;
+			status = "disabled";
+
+			stmmac_axi_setup_gmac1: stmmac-axi-config {
+				snps,blen = <0 0 0 0 16 8 4>;
+				snps,rd_osr_lmt = <2>;
+				snps,wr_osr_lmt = <2>;
+			};
+		};
+
 		gpio@51600000 {
 			compatible = "snps,dw-apb-gpio";
 			reg = <0x0 0x51600000 0x0 0x80>;
-- 
2.25.1


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Re: [PATCH net-next v3 3/3] riscv: dts: eswin: eic7700-hifive-premier-p550: enable Ethernet controller

[Yao Zi]

On Tue, Mar 03, 2026 at 02:17:32PM +0800, lizhi2@eswincomputing.com wrote:
> From: Zhi Li <lizhi2@eswincomputing.com>
> 
> Enable the on-board Gigabit Ethernet controller on the
> HiFive Premier P550 development board.
> 
> Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
> ---
>  .../dts/eswin/eic7700-hifive-premier-p550.dts | 50 +++++++++++++++++
>  arch/riscv/boot/dts/eswin/eic7700.dtsi        | 54 +++++++++++++++++++
>  2 files changed, 104 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> index 131ed1fc6b2e..d558f0fdfb38 100644
> --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts

...

> @@ -20,6 +22,54 @@ chosen {
>  	};
>  };
>  
> +&gmac0 {
> +	phy-handle = <&gmac0_phy0>;
> +	phy-mode = "rgmii-id";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&gpio106_pins>;
> +	rx-internal-delay-ps = <20>;
> +	tx-internal-delay-ps = <100>;
> +	status = "okay";
> +
> +	mdio {
> +		compatible = "snps,dwmac-mdio";

Since it's implemented in the DWMAC IP, I think the mdio bus is
SoC-specific and should be put into the SoC devicetree instead.

Regards,
Yao Zi

> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		gmac0_phy0: ethernet-phy@0 {
> +			compatible = "ethernet-phy-id001c.c916";
> +			reg = <0>;
> +			reset-gpios = <&gpioD 10 GPIO_ACTIVE_LOW>;
> +			reset-assert-us = <10000>;
> +			reset-deassert-us = <80000>;
> +		};
> +	};
> +};

Re: [PATCH net-next v3 3/3] riscv: dts: eswin: eic7700-hifive-premier-p550: enable Ethernet controller

[Yao Zi]

On Tue, Mar 03, 2026 at 02:17:32PM +0800, lizhi2@eswincomputing.com wrote:
> From: Zhi Li <lizhi2@eswincomputing.com>
> 
> Enable the on-board Gigabit Ethernet controller on the
> HiFive Premier P550 development board.
> 
> Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
> ---
>  .../dts/eswin/eic7700-hifive-premier-p550.dts | 50 +++++++++++++++++
>  arch/riscv/boot/dts/eswin/eic7700.dtsi        | 54 +++++++++++++++++++
>  2 files changed, 104 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> index 131ed1fc6b2e..d558f0fdfb38 100644
> --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts

...

> @@ -20,6 +22,54 @@ chosen {
>  	};
>  };
>  
> +&gmac0 {
> +	phy-handle = <&gmac0_phy0>;
> +	phy-mode = "rgmii-id";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&gpio106_pins>;
> +	rx-internal-delay-ps = <20>;
> +	tx-internal-delay-ps = <100>;
> +	status = "okay";
> +
> +	mdio {
> +		compatible = "snps,dwmac-mdio";

Since it's implemented in the DWMAC IP, I think the mdio bus is
SoC-specific and should be put into the SoC devicetree instead.

Regards,
Yao Zi

> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		gmac0_phy0: ethernet-phy@0 {
> +			compatible = "ethernet-phy-id001c.c916";
> +			reg = <0>;
> +			reset-gpios = <&gpioD 10 GPIO_ACTIVE_LOW>;
> +			reset-assert-us = <10000>;
> +			reset-deassert-us = <80000>;
> +		};
> +	};
> +};

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Re: Re: [PATCH net-next v3 3/3] riscv: dts: eswin: eic7700-hifive-premier-p550: enable Ethernet controller

[李志]

> -----原始邮件-----
> 发件人: "Yao Zi" <me@ziyao.cc>
> 发送时间:2026-03-03 18:32:38 (星期二)
> 收件人: lizhi2@eswincomputing.com, devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, wens@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
> 抄送: ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com
> 主题: Re: [PATCH net-next v3 3/3] riscv: dts: eswin: eic7700-hifive-premier-p550: enable Ethernet controller
> 
> On Tue, Mar 03, 2026 at 02:17:32PM +0800, lizhi2@eswincomputing.com wrote:
> > From: Zhi Li <lizhi2@eswincomputing.com>
> > 
> > Enable the on-board Gigabit Ethernet controller on the
> > HiFive Premier P550 development board.
> > 
> > Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
> > ---
> >  .../dts/eswin/eic7700-hifive-premier-p550.dts | 50 +++++++++++++++++
> >  arch/riscv/boot/dts/eswin/eic7700.dtsi        | 54 +++++++++++++++++++
> >  2 files changed, 104 insertions(+)
> > 
> > diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > index 131ed1fc6b2e..d558f0fdfb38 100644
> > --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> 
> ...
> 
> > @@ -20,6 +22,54 @@ chosen {
> >  	};
> >  };
> >  
> > +&gmac0 {
> > +	phy-handle = <&gmac0_phy0>;
> > +	phy-mode = "rgmii-id";
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&gpio106_pins>;
> > +	rx-internal-delay-ps = <20>;
> > +	tx-internal-delay-ps = <100>;
> > +	status = "okay";
> > +
> > +	mdio {
> > +		compatible = "snps,dwmac-mdio";
> 
> Since it's implemented in the DWMAC IP, I think the mdio bus is
> SoC-specific and should be put into the SoC devicetree instead.
> 

Hi Yao Zi,

Thanks for the review.

You're right that the MDIO bus is implemented as part of the DWMAC IP and
is therefore SoC-specific. It makes more sense to describe the MDIO
controller in the SoC dtsi.

I'll move the MDIO node to eic7700.dtsi and keep only the PHY node in the
board dts in the next revision.

Thanks,
Zhi Li

Re: Re: [PATCH net-next v3 3/3] riscv: dts: eswin: eic7700-hifive-premier-p550: enable Ethernet controller

[李志]

> -----原始邮件-----
> 发件人: "Yao Zi" <me@ziyao.cc>
> 发送时间:2026-03-03 18:32:38 (星期二)
> 收件人: lizhi2@eswincomputing.com, devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, wens@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
> 抄送: ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com
> 主题: Re: [PATCH net-next v3 3/3] riscv: dts: eswin: eic7700-hifive-premier-p550: enable Ethernet controller
> 
> On Tue, Mar 03, 2026 at 02:17:32PM +0800, lizhi2@eswincomputing.com wrote:
> > From: Zhi Li <lizhi2@eswincomputing.com>
> > 
> > Enable the on-board Gigabit Ethernet controller on the
> > HiFive Premier P550 development board.
> > 
> > Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
> > ---
> >  .../dts/eswin/eic7700-hifive-premier-p550.dts | 50 +++++++++++++++++
> >  arch/riscv/boot/dts/eswin/eic7700.dtsi        | 54 +++++++++++++++++++
> >  2 files changed, 104 insertions(+)
> > 
> > diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > index 131ed1fc6b2e..d558f0fdfb38 100644
> > --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> 
> ...
> 
> > @@ -20,6 +22,54 @@ chosen {
> >  	};
> >  };
> >  
> > +&gmac0 {
> > +	phy-handle = <&gmac0_phy0>;
> > +	phy-mode = "rgmii-id";
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&gpio106_pins>;
> > +	rx-internal-delay-ps = <20>;
> > +	tx-internal-delay-ps = <100>;
> > +	status = "okay";
> > +
> > +	mdio {
> > +		compatible = "snps,dwmac-mdio";
> 
> Since it's implemented in the DWMAC IP, I think the mdio bus is
> SoC-specific and should be put into the SoC devicetree instead.
> 

Hi Yao Zi,

Thanks for the review.

You're right that the MDIO bus is implemented as part of the DWMAC IP and
is therefore SoC-specific. It makes more sense to describe the MDIO
controller in the SoC dtsi.

I'll move the MDIO node to eic7700.dtsi and keep only the PHY node in the
board dts in the next revision.

Thanks,
Zhi Li
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