Re: [PATCH 09/65] hw/intc/arm_gicv5: Implement IRS ID regs

[Jonathan Cameron via <qemu-arm@nongnu.org>]

On Mon, 23 Feb 2026 17:01:16 +0000
Peter Maydell <peter.maydell@linaro.org> wrote:

> Implement the IRS frame ID registers IRS_IDR[0-7], IRS_IIDR and
> IRS_AIDR.  These are all 32-bit registers.
> 
> We make these fields in the GIC state struct rather than just
> hardcoding them in the register read function so that we can later
> code "do this only if X is implemented" as a test on the ID register
> value.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  hw/intc/arm_gicv5.c                | 112 +++++++++++++++++++++++++++++
>  include/hw/intc/arm_gicv5_common.h |  39 ++++++++++
>  2 files changed, 151 insertions(+)
> 
> diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c
> index db754e7681..f34bb81966 100644
> --- a/hw/intc/arm_gicv5.c
> +++ b/hw/intc/arm_gicv5.c
> @@ -268,6 +268,62 @@ REG64(IRS_SWERR_SYNDROMER1, 0x3d0)
>  static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,
>                           uint64_t *data, MemTxAttrs attrs)
>  {
> +    GICv5Common *cs = ARM_GICV5_COMMON(s);
> +    uint32_t v = 0;
> +
> +    switch (offset) {
> +    case A_IRS_IDR0:
> +        v = cs->irs_idr0;
> +        /* INT_DOM reports the domain this register is for */
> +        v = FIELD_DP32(v, IRS_IDR0, INT_DOM, domain);
> +        if (domain != GICV5_ID_REALM) {
> +            /* MEC field RES0 except for the Realm domain */
> +            v &= ~R_IRS_IDR0_MEC_MASK;
> +        }
> +        if (domain == GICV5_ID_EL3) {
> +            /* VIRT is RES0 for EL3 domain */
> +            v &= ~R_IRS_IDR0_VIRT_MASK;
> +        }

There are some more complex RES0 conditions that kind of build
off these, like VIRT_ONE_N is RES0 if VIRT is 0, including
I think if VIRT is RES0 as a result of the above.  That particular
condition is perhaps worth encoding in here as you can see we may
have it implemented for everything other than EL3.

This is similar to what you do for the whole of IDR3.

> +        return true;
> +
> +    case A_IRS_IDR1:
> +        *data = cs->irs_idr1;
> +        return true;
> +
> +    case A_IRS_IDR2:
> +        *data = cs->irs_idr2;
> +        return true;
> +
> +    case A_IRS_IDR3:
> +        /* In EL3 IDR0.VIRT is 0 so this is RES0 */
> +        *data = domain == GICV5_ID_EL3 ? 0 : cs->irs_idr3;

The spec has that condition on a field by field bases. I wonder
if it would be clearer to mask out each field rather than set
whole thing to 0.

> +        return true;
> +
> +    case A_IRS_IDR4:
> +        /* In EL3 IDR0.VIRT is 0 so this is RES0 */
> +        *data = domain == GICV5_ID_EL3 ? 0 : cs->irs_idr4;
Similar for this one.  Most of register is currently res0 and
we don't know if those bits will be used later for stuff that
isn't dependent on IRS_IDR0.VIRT being 1.

> +        return true;

...

>  }
>  
> @@ -443,6 +499,60 @@ static void gicv5_reset_hold(Object *obj, ResetType type)
>      }
>  }
>  
> +static void gicv5_set_idregs(GICv5Common *cs)
> +{
> +    /* Set the ID register value fields */
> +    uint32_t v;
> +
> +    /*
> +     * We don't support any of the optional parts of the spec currently,
Doesn't matter much but 'currently' does add anything to this sentence so
could just drop it.

> +     * so most of the fields in IRS_IDR0 are zero.
> +     */
> +    v = 0;


> +}
> +

>  
> diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5_common.h
> index be898abcd5..bcf7cd4239 100644
> --- a/include/hw/intc/arm_gicv5_common.h
> +++ b/include/hw/intc/arm_gicv5_common.h
> @@ -65,6 +65,18 @@ struct GICv5Common {


> +/*
> + * The architecture allows a GICv5 to implement less than the
> + * full width for various ID fields. QEMU's implementation
> + * always supports the full width of these fields. These constants
> + * define our implementation's limits.
> + */
> +
> +/* Number of INTID.ID bits we support */
> +#define QEMU_GICV5_ID_BITS 24
> +/* Min LPI_ID_BITS supported */
> +#define QEMU_GICV5_MIN_LPI_ID_BITS 14
> +/* IAFFID bits supported */
> +#define QEMU_GICV5_IAFFID_BITS 16
> +/* Number of priority bits supported in the IRS */
> +#define QEMU_GICV5_PRI_BITS 5
> +
> +/*
> + * There are no TRMs currently published for hardware
> + * implementations of GICv5 that we might identify ourselves
> + * as. Instead, we borrow the Arm Implementer code and
> + * pick an arbitrary product ID (ASCII "Q")

Rather short wrap.


> + */
> +#define QEMU_GICV5_IMPLEMENTER 0x43b
> +#define QEMU_GICV5_PRODUCTID 0x51
> +#define QEMU_GICV5_REVISION 0
> +#define QEMU_GICV5_VARIANT 0
> +
>  /**
>   * gicv5_common_init_irqs_and_mmio: Create IRQs and MMIO regions for the GICv5
>   * @s: GIC object