[PATCH v2 0/3] target/arm: ISV=0 data abort emulation library

[Lucas Amaral <lucaaamaral@gmail.com>]

When a guest triggers a data abort with ISV=0 (e.g. STP, LDP, SIMD/FP
load/store, writeback addressing, atomics, exclusives), the ESR syndrome
does not carry the access size or target register, so the hypervisor
cannot emulate MMIO without decoding the faulting instruction.

v1 handled this inside HVF with a hand-written decoder.  Based on review
feedback from Mohamed Mediouni and Peter Maydell, v2 restructures the
implementation as:

  - A shared emulation library in target/arm/emulate/ with a decodetree
    decoder (a64-ldst.decode), usable by any hypervisor backend.

  - A callback-based interface (struct arm_emul_ops) that abstracts
    register and memory access, keeping the library hypervisor-agnostic.

  - HVF and WHPX backends wired as the first two consumers.

Instruction classes handled (DDI 0487):
  - Load/store pair: STP, LDP, STNP, LDNP, STGP, LDPSW (C3.3.14-16)
  - SIMD/FP load/store pair and single (C3.3.10, C3.3.14-16)
  - All immediate addressing: unscaled, post/pre-index, unsigned offset
  - Register offset addressing with extend (C3.3.9)
  - Exclusives: STXR, LDXR, STXP, LDXP (C3.3.6)
  - Atomics: LDADD, LDCLR, LDEOR, LDSET, LDSMAX/MIN, LDUMAX/MIN, SWP
  - Compare-and-swap: CAS, CASP (C3.3.1)
  - LDRAA/LDRAB with FEAT_PAuth (C6.2.121)
  - PRFM, DC maintenance (as NOPs)

Intentionally omitted (not observed in ISV=0 MMIO traps during testing):
  - AdvSIMD structure loads/stores (LD1/ST1 etc.)
  - MTE load/stores (FEAT_MTE)
  - 128-bit atomics (FEAT_LSE128)
  - MOPS (FEAT_MOPS)

KVM NISV handling is a natural follow-up -- it requires similar
arm_emul_ops callbacks using KVM vcpu ioctls.

v1 -> v2:
  - Moved from HVF-specific inline decoder to shared library
    in target/arm/emulate/ (Mohamed Mediouni)
  - Added decodetree decoder for structured instruction parsing
    (Peter Maydell)
  - Made hypervisor-agnostic; wired HVF and WHPX (Peter Maydell)
  - Added CASP register-pair validation (odd/r31 -> UNHANDLED)
  - Added unit tests (19 test cases)
  - Split into 3 patches for reviewability

Lucas Amaral (3):
  target/arm: add AArch64 ISV=0 instruction emulation library
  tests: add unit tests for ISV=0 emulation library
  target/arm: wire ISV=0 emulation into HVF and WHPX

 target/arm/emulate/a64-ldst.decode | 293 ++++++++++++
 target/arm/emulate/arm_emulate.c   | 738 +++++++++++++++++++++++++++++
 target/arm/emulate/arm_emulate.h   |  55 +++
 target/arm/emulate/meson.build     |  16 +
 target/arm/hvf/hvf.c               |  94 +++-
 target/arm/meson.build             |   1 +
 target/arm/whpx/whpx-all.c         |  86 +++-
 tests/unit/meson.build             |   1 +
 tests/unit/test-arm-emulate.c      | 540 +++++++++++++++++++++
 9 files changed, 1820 insertions(+), 4 deletions(-)
 create mode 100644 target/arm/emulate/a64-ldst.decode
 create mode 100644 target/arm/emulate/arm_emulate.c
 create mode 100644 target/arm/emulate/arm_emulate.h
 create mode 100644 target/arm/emulate/meson.build
 create mode 100644 tests/unit/test-arm-emulate.c

-- 
2.52.0