[PATCH v3 0/6] target/arm: ISV=0 data abort emulation library

[Lucas Amaral <lucaaamaral@gmail.com>]

Add a shared emulation library for AArch64 load/store instructions that
cause ISV=0 data aborts under hardware virtualization, and wire it into
HVF (macOS) and WHPX (Windows).

When the Instruction Syndrome Valid bit is clear, the hypervisor cannot
determine the faulting instruction's target register or access size from
the syndrome alone.  This previously hit an assert(isv) and killed the
VM.  The library fetches and decodes the faulting instruction using a
decodetree-generated decoder, then emulates it directly against the vCPU
register file and memory.

As suggested in v1 review, the library uses its own a64-ldst.decode
rather than sharing target/arm/tcg/a64.decode.  Beyond the practical
complexity noted in review, the two have incompatible purposes: TCG's
trans_* functions are a compiler — they emit IR ops into a translation
block for later execution.  This library's trans_* functions are an
interpreter — they execute directly against the vCPU register file and
memory.  The decodetree-generated dispatcher calls trans_* by name, so
both cannot coexist in the same translation unit.  Decode patterns are
kept consistent with TCG's where possible.

This series wires the library into HVF (macOS) and WHPX (Windows).  KVM
on ARM already handles ISV=0 data aborts in-kernel via
kvm_arm_handle_dabt_nisv(), but could use this library as a userspace
fallback in the future.

Changes since v2:
  - Split monolithic patch into 6 incremental patches: framework, then
    one patch per coherent instruction group (Peter)
  - Removed per-backend callback ops; library uses CPUArchState directly
    with cpu_memory_rw_debug() for memory access (Mohamed)
  - Removed mock unit tests (Mohamed; kvm-unit-tests is the right
    vehicle for decoder validation)
  - Added architectural justification for separate decode file

Lucas Amaral (6):
  target/arm/emulate: add ISV=0 emulation library with load/store
    immediate
  target/arm/emulate: add load/store register offset
  target/arm/emulate: add load/store pair
  target/arm/emulate: add load/store exclusive
  target/arm/emulate: add atomic, compare-and-swap, and PAC load
  target/arm/hvf,whpx: wire ISV=0 emulation for data aborts

 target/arm/emulate/a64-ldst.decode | 293 +++++++++++
 target/arm/emulate/arm_emulate.c   | 747 +++++++++++++++++++++++++++++
 target/arm/emulate/arm_emulate.h   |  30 ++
 target/arm/emulate/meson.build     |   6 +
 target/arm/hvf/hvf.c               |  41 +-
 target/arm/meson.build             |   1 +
 target/arm/whpx/whpx-all.c         |  39 +-
 7 files changed, 1153 insertions(+), 4 deletions(-)
 create mode 100644 target/arm/emulate/a64-ldst.decode
 create mode 100644 target/arm/emulate/arm_emulate.c
 create mode 100644 target/arm/emulate/arm_emulate.h
 create mode 100644 target/arm/emulate/meson.build

-- 
2.52.0