From: Mohamed Mediouni <mohamed@unpredictable.fr>
To: qemu-devel@nongnu.org
Cc: "Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Yanan Wang" <wangyanan55@huawei.com>,
"Zhao Liu" <zhao1.liu@intel.com>,
qemu-arm@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
"Roman Bolshakov" <rbolshakov@ddn.com>,
"Alexander Graf" <agraf@csgraf.de>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Eduardo Habkost" <eduardo@habkost.net>,
"Phil Dennis-Jordan" <phil@philjordan.eu>,
"Mohamed Mediouni" <mohamed@unpredictable.fr>
Subject: [PATCH v20 15/15] hvf: arm: enable vGIC by default for virt-11.1 and later
Date: Mon, 16 Mar 2026 14:06:42 +0100 [thread overview]
Message-ID: <20260316130642.13246-16-mohamed@unpredictable.fr> (raw)
In-Reply-To: <20260316130642.13246-1-mohamed@unpredictable.fr>
Save states are incompatible between kernel-irqchip=on and off on HVF due to opaque vGIC state.
Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
---
accel/hvf/hvf-all.c | 11 +++++++++++
hw/arm/virt.c | 22 +++++++++++++++++++++-
include/hw/arm/virt.h | 2 ++
include/hw/core/boards.h | 1 +
include/system/hvf_int.h | 1 +
5 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c
index 48c653630f..4e5a8c58a8 100644
--- a/accel/hvf/hvf-all.c
+++ b/accel/hvf/hvf-all.c
@@ -25,6 +25,7 @@
bool hvf_allowed;
bool hvf_kernel_irqchip;
bool hvf_nested_virt;
+bool hvf_kernel_irqchip_override;
void hvf_nested_virt_enable(bool nested_virt) {
hvf_nested_virt = nested_virt;
@@ -203,6 +204,13 @@ static int hvf_accel_init(AccelState *as, MachineState *ms)
}
}
+ if (mc->get_kernel_irqchip_default) {
+ bool kernel_irqchip_default = mc->get_kernel_irqchip_default(ms);
+ if (!hvf_kernel_irqchip_override) {
+ hvf_kernel_irqchip = kernel_irqchip_default;
+ }
+ }
+
ret = hvf_arch_vm_create(ms, (uint32_t)pa_range);
if (ret == HV_DENIED) {
error_report("Could not access HVF. Is the executable signed"
@@ -229,6 +237,8 @@ static void hvf_set_kernel_irqchip(Object *obj, Visitor *v,
Error **errp)
{
OnOffSplit mode;
+
+ hvf_kernel_irqchip_override = true;
if (!visit_type_OnOffSplit(v, name, &mode, errp)) {
return;
}
@@ -268,6 +278,7 @@ static void hvf_accel_class_init(ObjectClass *oc, const void *data)
ac->init_machine = hvf_accel_init;
ac->allowed = &hvf_allowed;
ac->gdbstub_supported_sstep_flags = hvf_gdbstub_sstep_flags;
+ hvf_kernel_irqchip_override = false;
hvf_kernel_irqchip = false;
object_class_property_add(oc, "kernel-irqchip", "on|off|split",
NULL, hvf_set_kernel_irqchip,
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 391ec722c0..ad82a7356e 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3443,6 +3443,16 @@ static int virt_get_physical_address_range(MachineState *ms,
return requested_ipa_size;
}
+static bool get_kernel_irqchip_default(const MachineState *ms) {
+ VirtMachineState *vms = VIRT_MACHINE(ms);
+ VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
+ if (hvf_allowed) {
+ return !vmc->hvf_no_kernel_irqchip_default;
+ } else {
+ return true;
+ }
+}
+
static const char *virt_get_default_cpu_type(const MachineState *ms)
{
return tcg_enabled() ? ARM_CPU_TYPE_NAME("cortex-a15")
@@ -3509,6 +3519,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)
mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
mc->kvm_type = virt_kvm_type;
mc->get_physical_address_range = virt_get_physical_address_range;
+ mc->get_kernel_irqchip_default = get_kernel_irqchip_default;
assert(!mc->get_hotplug_handler);
mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
hc->pre_plug = virt_machine_device_pre_plug_cb;
@@ -3740,10 +3751,19 @@ static void machvirt_machine_init(void)
}
type_init(machvirt_machine_init);
+static void virt_machine_11_1_options(MachineClass *mc)
+{
+}
+DEFINE_VIRT_MACHINE_AS_LATEST(11, 1)
+
static void virt_machine_11_0_options(MachineClass *mc)
{
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+ virt_machine_11_1_options(mc);
+
+ vmc->hvf_no_kernel_irqchip_default = true;
}
-DEFINE_VIRT_MACHINE_AS_LATEST(11, 0)
+DEFINE_VIRT_MACHINE(11, 0)
static void virt_machine_10_2_options(MachineClass *mc)
{
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index dba8ac7f2f..d2575e14a0 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -135,6 +135,8 @@ struct VirtMachineClass {
bool no_tcg_lpa2;
bool no_ns_el2_virt_timer_irq;
bool no_nested_smmu;
+ /* HVF specific: support for kernel-irqchip=on introduced in QEMU 11.1 */
+ bool hvf_no_kernel_irqchip_default;
};
struct VirtMachineState {
diff --git a/include/hw/core/boards.h b/include/hw/core/boards.h
index f85f31bd90..ad896ed0b7 100644
--- a/include/hw/core/boards.h
+++ b/include/hw/core/boards.h
@@ -279,6 +279,7 @@ struct MachineClass {
int (*kvm_type)(MachineState *machine, const char *arg);
int (*get_physical_address_range)(MachineState *machine,
int default_ipa_size, int max_ipa_size);
+ bool (*get_kernel_irqchip_default) (const MachineState *machine);
BlockInterfaceType block_default_type;
int units_per_default_bus;
diff --git a/include/system/hvf_int.h b/include/system/hvf_int.h
index 2621164cb2..ad7d375109 100644
--- a/include/system/hvf_int.h
+++ b/include/system/hvf_int.h
@@ -112,4 +112,5 @@ bool hvf_arch_cpu_realize(CPUState *cpu, Error **errp);
uint32_t hvf_arch_get_default_ipa_bit_size(void);
uint32_t hvf_arch_get_max_ipa_bit_size(void);
+extern bool hvf_kernel_irqchip_override;
#endif
--
2.50.1 (Apple Git-155)
next prev parent reply other threads:[~2026-03-16 13:11 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-16 13:06 [PATCH v20 00/15] HVF: Add support for platform vGIC and nested virtualisation Mohamed Mediouni
2026-03-16 13:06 ` [PATCH v20 01/15] hw/intc: Add hvf vGIC interrupt controller support Mohamed Mediouni
2026-04-24 6:38 ` Manos Pitsidianakis
2026-03-16 13:06 ` [PATCH v20 02/15] hw/intc: arm_gicv3_hvf: save/restore Apple GIC state Mohamed Mediouni
2026-04-24 6:56 ` Manos Pitsidianakis
2026-04-24 7:29 ` Philippe Mathieu-Daudé
2026-03-16 13:06 ` [PATCH v20 03/15] accel, hw/arm, include/system/hvf: infrastructure changes for HVF vGIC Mohamed Mediouni
2026-04-23 16:10 ` Philippe Mathieu-Daudé
2026-04-23 17:01 ` Mohamed Mediouni
2026-03-16 13:06 ` [PATCH v20 04/15] target/arm: hvf: instantiate GIC early Mohamed Mediouni
2026-03-16 13:06 ` [PATCH v20 05/15] hw/arm, target/arm: nested virtualisation on HVF Mohamed Mediouni
2026-04-24 7:07 ` Manos Pitsidianakis
2026-03-16 13:06 ` [PATCH v20 06/15] hvf: only call hvf_sync_vtimer() when running without the platform vGIC Mohamed Mediouni
2026-03-16 13:06 ` [PATCH v20 07/15] hvf: gate ARM_FEATURE_PMU register emulation when using the Apple vGIC Mohamed Mediouni
2026-04-24 7:15 ` Manos Pitsidianakis
2026-03-16 13:06 ` [PATCH v20 08/15] hvf: arm: allow exposing minimal PMU when running with nested virt on Mohamed Mediouni
2026-04-23 16:03 ` Philippe Mathieu-Daudé
2026-03-16 13:06 ` [PATCH v20 09/15] target/arm: hvf: add asserts for code paths not leveraged when using the vGIC Mohamed Mediouni
2026-03-16 13:06 ` [PATCH v20 10/15] hvf: sync registers used at EL2 Mohamed Mediouni
2026-03-16 13:06 ` [PATCH v20 11/15] target/arm: hvf: pass through CNTHCTL_EL2 and MDCCINT_EL1 Mohamed Mediouni
2026-03-16 13:06 ` [PATCH v20 12/15] hvf: arm: disable SME when nested virt is active Mohamed Mediouni
2026-03-16 13:06 ` [PATCH v20 13/15] hvf: arm: physical timer emulation Mohamed Mediouni
2026-04-23 16:07 ` Philippe Mathieu-Daudé
2026-03-16 13:06 ` [PATCH v20 14/15] hvf: enable nested virtualisation support Mohamed Mediouni
2026-04-24 7:11 ` Manos Pitsidianakis
2026-03-16 13:06 ` Mohamed Mediouni [this message]
2026-04-24 7:13 ` [PATCH v20 15/15] hvf: arm: enable vGIC by default for virt-11.1 and later Manos Pitsidianakis
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