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From: Magnus Kulke <magnuskulke@linux.microsoft.com>
To: qemu-devel@nongnu.org
Cc: Wei Liu <liuwe@microsoft.com>,
	Paolo Bonzini <pbonzini@redhat.com>, Wei Liu <wei.liu@kernel.org>,
	Magnus Kulke <magnuskulke@linux.microsoft.com>,
	Magnus Kulke <magnuskulke@microsoft.com>,
	Zhao Liu <zhao1.liu@intel.com>
Subject: [PATCH v3 4/9] target/i386/mshv: change cpuid mask to UINT32_MAX
Date: Mon, 23 Mar 2026 12:57:06 +0100	[thread overview]
Message-ID: <20260323115711.353793-5-magnuskulke@linux.microsoft.com> (raw)
In-Reply-To: <20260323115711.353793-1-magnuskulke@linux.microsoft.com>

The current implementation would only override the feature bits that are
enabled, however we also want to consider disabled features, hence all
bits are set on the masks in the hypercall argument.

Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>
Acked-by: Wei Liu <wei.liu@kernel.org>
---
 target/i386/mshv/mshv-cpu.c | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c
index 4183727a86..e42b5a614d 100644
--- a/target/i386/mshv/mshv-cpu.c
+++ b/target/i386/mshv/mshv-cpu.c
@@ -538,22 +538,17 @@ static int register_intercept_result_cpuid_entry(const CPUState *cpu,
         .input.always_override = always_override,
         .input.padding = 0,
         /*
-         * With regard to masks - these are to specify bits to be overwritten
-         * The current CpuidEntry structure wouldn't allow to carry the masks
-         * in addition to the actual register values. For this reason, the
-         * masks are set to the exact values of the corresponding register bits
-         * to be registered for an overwrite. To view resulting values the
-         * hypervisor would return, HvCallGetVpCpuidValues hypercall can be
-         * used.
+         * Masks specify which bits to override. Set to 0xFFFFFFFF to
+         * override all bits with the values from the QEMU CPU model.
          */
         .result.eax = entry->eax,
-        .result.eax_mask = entry->eax,
+        .result.eax_mask = 0xFFFFFFFF,
         .result.ebx = entry->ebx,
-        .result.ebx_mask = entry->ebx,
+        .result.ebx_mask = 0xFFFFFFFF,
         .result.ecx = entry->ecx,
-        .result.ecx_mask = entry->ecx,
+        .result.ecx_mask = 0xFFFFFFFF,
         .result.edx = entry->edx,
-        .result.edx_mask = entry->edx,
+        .result.edx_mask = 0xFFFFFFFF,
     };
     union hv_register_intercept_result_parameters parameters = {
         .cpuid = cpuid_params,
-- 
2.34.1



  parent reply	other threads:[~2026-03-23 11:58 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-23 11:57 [PATCH v3 0/9] Support QEMU cpu models in MSHV accelerator Magnus Kulke
2026-03-23 11:57 ` [PATCH v3 1/9] accel/mshv: use mshv_create_partition_v2 payload Magnus Kulke
2026-03-27  4:16   ` Anirudh Rayabharam
2026-03-23 11:57 ` [PATCH v3 2/9] target/i386/mshv: fix cpuid propagation bug Magnus Kulke
2026-03-27  4:15   ` Anirudh Rayabharam
2026-03-23 11:57 ` [PATCH v3 3/9] target/i386/mshv: fix various cpuid traversal bugs Magnus Kulke
2026-03-23 11:57 ` Magnus Kulke [this message]
2026-03-23 11:57 ` [PATCH v3 5/9] target/i386/mshv: set cpu model name on -cpu host Magnus Kulke
2026-03-23 11:57 ` [PATCH v3 6/9] target/i386: query mshv accel for supported cpuids Magnus Kulke
2026-03-23 11:57 ` [PATCH v3 7/9] target/i386/mshv: populate xsave area offsets Magnus Kulke
2026-03-27  4:37   ` Anirudh Rayabharam
2026-03-23 11:57 ` [PATCH v3 8/9] target/i386/mshv: filter out CET bits in cpuid Magnus Kulke
2026-03-27  4:41   ` Anirudh Rayabharam
2026-03-23 11:57 ` [PATCH v3 9/9] accel/mshv: disable la57 (5lvl paging) Magnus Kulke
2026-03-27  4:23   ` Anirudh Rayabharam
2026-03-27 16:08   ` Paolo Bonzini
2026-03-27 16:40     ` Magnus Kulke
2026-03-27 16:54     ` Magnus Kulke

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