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From: Conor Dooley <conor@kernel.org>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Hui Min Mina Chou <minachou@andestech.com>,
	pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
	alex@ghiti.fr, geert+renesas@glider.be,
	prabhakar.mahadev-lad.rj@bp.renesas.com, magnus.damm@gmail.com,
	ben717@andestech.com, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, jonathan.cameron@huawei.com,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	tim609@andestech.com, alex749@andestech.com, az70021@gmail.com
Subject: Re: [PATCH 5/7] dt-bindings: cache: ax45mp-cache: rename ax45mp-cache to llcache
Date: Mon, 30 Mar 2026 16:29:33 +0100	[thread overview]
Message-ID: <20260330-snagged-whiff-e56fc19963ee@spud> (raw)
In-Reply-To: <c2a135eb-c8fa-47d6-b774-430ccc4fbda4@kernel.org>

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On Mon, Mar 30, 2026 at 03:00:41PM +0200, Krzysztof Kozlowski wrote:
> On 30/03/2026 12:27, Hui Min Mina Chou wrote:
> > The AX45MP-specific cache binding is renamed to a generic Last Level
> > Cache (LLC) schema, as the driver now supports more Andes CPU cores
> > beyond just AX45MP.
> > 
> > Updated compatible strings:
> >   andestech,qilai-ax45mp-cache    -> andestech,qilai-llcache
> >   renesas,r9a07g043f-ax45mp-cache -> renesas,r9a07g043f-llcache
> >   andestech,ax45mp-cache          -> andestech,llcache
> 
> Why? No explanations and that is clear ABI break.

Ye, I am not going to accept any compatible string renames for this
hardware. The break is too significant, since the devices *need* this to
function.

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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Hui Min Mina Chou <minachou@andestech.com>,
	pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
	alex@ghiti.fr, geert+renesas@glider.be,
	prabhakar.mahadev-lad.rj@bp.renesas.com, magnus.damm@gmail.com,
	ben717@andestech.com, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, jonathan.cameron@huawei.com,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	tim609@andestech.com, alex749@andestech.com, az70021@gmail.com
Subject: Re: [PATCH 5/7] dt-bindings: cache: ax45mp-cache: rename ax45mp-cache to llcache
Date: Mon, 30 Mar 2026 16:29:33 +0100	[thread overview]
Message-ID: <20260330-snagged-whiff-e56fc19963ee@spud> (raw)
In-Reply-To: <c2a135eb-c8fa-47d6-b774-430ccc4fbda4@kernel.org>


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On Mon, Mar 30, 2026 at 03:00:41PM +0200, Krzysztof Kozlowski wrote:
> On 30/03/2026 12:27, Hui Min Mina Chou wrote:
> > The AX45MP-specific cache binding is renamed to a generic Last Level
> > Cache (LLC) schema, as the driver now supports more Andes CPU cores
> > beyond just AX45MP.
> > 
> > Updated compatible strings:
> >   andestech,qilai-ax45mp-cache    -> andestech,qilai-llcache
> >   renesas,r9a07g043f-ax45mp-cache -> renesas,r9a07g043f-llcache
> >   andestech,ax45mp-cache          -> andestech,llcache
> 
> Why? No explanations and that is clear ABI break.

Ye, I am not going to accept any compatible string renames for this
hardware. The break is too significant, since the devices *need* this to
function.

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  reply	other threads:[~2026-03-30 15:29 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-30 10:27 [PATCH 0/7] refactor Andes cache driver for generic platform support Hui Min Mina Chou
2026-03-30 10:27 ` Hui Min Mina Chou
2026-03-30 10:27 ` [PATCH 1/7] cache: ax45mp_cache: refactor cache driver for generic Andes " Hui Min Mina Chou
2026-03-30 10:27   ` Hui Min Mina Chou
2026-03-30 13:01   ` Krzysztof Kozlowski
2026-03-30 13:01     ` Krzysztof Kozlowski
2026-03-30 15:54   ` Conor Dooley
2026-03-30 15:54     ` Conor Dooley
2026-04-01  2:30     ` Mina Chou
2026-04-01  2:30       ` Mina Chou
2026-04-01  9:25       ` Conor Dooley
2026-04-01  9:25         ` Conor Dooley
2026-03-30 10:27 ` [PATCH 2/7] cache: andes_llcache: refactor initialization and cache operations Hui Min Mina Chou
2026-03-30 10:27   ` Hui Min Mina Chou
2026-03-30 13:02   ` Krzysztof Kozlowski
2026-03-30 13:02     ` Krzysztof Kozlowski
2026-03-30 15:23     ` Conor Dooley
2026-03-30 15:23       ` Conor Dooley
2026-03-30 16:05   ` Conor Dooley
2026-03-30 16:05     ` Conor Dooley
2026-03-31  8:31   ` Krzysztof Kozlowski
2026-03-31  8:31     ` Krzysztof Kozlowski
2026-03-30 10:27 ` [PATCH 3/7] cache: andes_llcache: improve performance of LLC operation Hui Min Mina Chou
2026-03-30 10:27   ` Hui Min Mina Chou
2026-03-30 16:04   ` Conor Dooley
2026-03-30 16:04     ` Conor Dooley
2026-03-30 10:27 ` [PATCH 4/7] cache: andes_llcache: centralize cache ops and use native WBINVAL Hui Min Mina Chou
2026-03-30 10:27   ` Hui Min Mina Chou
2026-03-30 10:27 ` [PATCH 5/7] dt-bindings: cache: ax45mp-cache: rename ax45mp-cache to llcache Hui Min Mina Chou
2026-03-30 10:27   ` Hui Min Mina Chou
2026-03-30 12:51   ` Rob Herring (Arm)
2026-03-30 12:51     ` Rob Herring (Arm)
2026-03-30 13:00   ` Krzysztof Kozlowski
2026-03-30 13:00     ` Krzysztof Kozlowski
2026-03-30 15:29     ` Conor Dooley [this message]
2026-03-30 15:29       ` Conor Dooley
2026-03-30 15:28   ` Conor Dooley
2026-03-30 15:28     ` Conor Dooley
2026-03-30 10:27 ` [PATCH 6/7] dts: riscv: update cache compatible strings to LLC Hui Min Mina Chou
2026-03-30 10:27   ` Hui Min Mina Chou
2026-03-30 13:03   ` Krzysztof Kozlowski
2026-03-30 13:03     ` Krzysztof Kozlowski
2026-03-30 10:27 ` [PATCH 7/7] MAINTAINERS: Add maintainers for Andes cache driver Hui Min Mina Chou
2026-03-30 10:27   ` Hui Min Mina Chou

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