Re: [PATCH 6/7] dts: riscv: update cache compatible strings to LLC

From: Krzysztof Kozlowski <krzk@kernel.org>
To: Hui Min Mina Chou <minachou@andestech.com>,
	pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
	alex@ghiti.fr, geert+renesas@glider.be,
	prabhakar.mahadev-lad.rj@bp.renesas.com, magnus.damm@gmail.com,
	ben717@andestech.com, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, jonathan.cameron@huawei.com,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Cc: tim609@andestech.com, alex749@andestech.com, az70021@gmail.com
Subject: Re: [PATCH 6/7] dts: riscv: update cache compatible strings to LLC
Date: Mon, 30 Mar 2026 15:03:06 +0200	[thread overview]
Message-ID: <bef394b6-00a6-4cab-be39-437a5d39bde5@kernel.org> (raw)
In-Reply-To: <20260330102724.1012470-7-minachou@andestech.com>

On 30/03/2026 12:27, Hui Min Mina Chou wrote:
> Update the cache driver compatible strings from ax45mp-cache to llcache

Driver? DTS is for hardware.

> for both Qilai and RZ/Five platforms.
> This follows the Andes cache driver refactoring to use more generic

Nope, driver changes cannot be the reason to change DTS.

> Last Level Cache (LLC) naming.
> 
> Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
> ---
>  arch/riscv/boot/dts/andes/qilai.dtsi        | 4 ++--
>  arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/andes/qilai.dtsi
> index de3de32f8c39..a7436cbf6f69 100644
> --- a/arch/riscv/boot/dts/andes/qilai.dtsi
> +++ b/arch/riscv/boot/dts/andes/qilai.dtsi
> @@ -137,8 +137,8 @@ plmt: timer@100000 {
>  		};
>  
>  		l2_cache: cache-controller@200000 {
> -			compatible = "andestech,qilai-ax45mp-cache",
> -				     "andestech,ax45mp-cache", "cache";
> +			compatible = "andestech,qilai-llcache",
> +				     "andestech,llcache", "cache";

NAK, actual impact on users.

Best regards,
Krzysztof