From: Jakub Kicinski <kuba@kernel.org>
To: "Nitka, Grzegorz" <grzegorz.nitka@intel.com>
Cc: "Vecera, Ivan" <ivecera@redhat.com>,
"vadim.fedorenko@linux.dev" <vadim.fedorenko@linux.dev>,
"jiri@resnulli.us" <jiri@resnulli.us>,
"edumazet@google.com" <edumazet@google.com>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"richardcochran@gmail.com" <richardcochran@gmail.com>,
"donald.hunter@gmail.com" <donald.hunter@gmail.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Kubalewski, Arkadiusz" <arkadiusz.kubalewski@intel.com>,
"Prathosh.Satish@microchip.com" <Prathosh.Satish@microchip.com>,
"andrew+netdev@lunn.ch" <andrew+netdev@lunn.ch>,
"intel-wired-lan@lists.osuosl.org"
<intel-wired-lan@lists.osuosl.org>,
"horms@kernel.org" <horms@kernel.org>,
"Kitszel, Przemyslaw" <przemyslaw.kitszel@intel.com>,
"Nguyen, Anthony L" <anthony.l.nguyen@intel.com>,
"pabeni@redhat.com" <pabeni@redhat.com>,
"davem@davemloft.net" <davem@davemloft.net>
Subject: Re: [Intel-wired-lan] [PATCH v5 net-next 0/8] dpll/ice: Add TXC DPLL type and full TX reference clock control for E825
Date: Sun, 12 Apr 2026 07:50:53 -0700 [thread overview]
Message-ID: <20260412075053.23660721@kernel.org> (raw)
In-Reply-To: <IA1PR11MB62195E2AF6FE5B102B2EECD392272@IA1PR11MB6219.namprd11.prod.outlook.com>
On Sun, 12 Apr 2026 13:50:23 +0000 Nitka, Grzegorz wrote:
> > > Proposed solution just seems to be clean and fully reflects current
> > > connection topology.
> >
> > Do you have the link to the old proposal that was adding stuff to
> > rtnetlink? I remember some discussion long-ish ago, maybe I was wrong.
>
> This is the patch from the discussion I put the link in the cover letter:
> https://lore.kernel.org/netdev/20250828164345.116097-1-arkadiusz.kubalewski@intel.com/
Let's go back to something like that. But leave the OC info out of
the XO, just ext-ref, dpll, xo? We can add the xo types later if really
needed. Sorry for the flip flop.
WARNING: multiple messages have this Message-ID (diff)
From: Jakub Kicinski <kuba@kernel.org>
To: "Nitka, Grzegorz" <grzegorz.nitka@intel.com>
Cc: "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"intel-wired-lan@lists.osuosl.org"
<intel-wired-lan@lists.osuosl.org>,
"Oros, Petr" <poros@redhat.com>,
"richardcochran@gmail.com" <richardcochran@gmail.com>,
"andrew+netdev@lunn.ch" <andrew+netdev@lunn.ch>,
"Kitszel, Przemyslaw" <przemyslaw.kitszel@intel.com>,
"Nguyen, Anthony L" <anthony.l.nguyen@intel.com>,
"Prathosh.Satish@microchip.com" <Prathosh.Satish@microchip.com>,
"Vecera, Ivan" <ivecera@redhat.com>,
"jiri@resnulli.us" <jiri@resnulli.us>,
"Kubalewski, Arkadiusz" <arkadiusz.kubalewski@intel.com>,
"vadim.fedorenko@linux.dev" <vadim.fedorenko@linux.dev>,
"donald.hunter@gmail.com" <donald.hunter@gmail.com>,
"horms@kernel.org" <horms@kernel.org>,
"pabeni@redhat.com" <pabeni@redhat.com>,
"davem@davemloft.net" <davem@davemloft.net>,
"edumazet@google.com" <edumazet@google.com>
Subject: Re: [PATCH v5 net-next 0/8] dpll/ice: Add TXC DPLL type and full TX reference clock control for E825
Date: Sun, 12 Apr 2026 07:50:53 -0700 [thread overview]
Message-ID: <20260412075053.23660721@kernel.org> (raw)
In-Reply-To: <IA1PR11MB62195E2AF6FE5B102B2EECD392272@IA1PR11MB6219.namprd11.prod.outlook.com>
On Sun, 12 Apr 2026 13:50:23 +0000 Nitka, Grzegorz wrote:
> > > Proposed solution just seems to be clean and fully reflects current
> > > connection topology.
> >
> > Do you have the link to the old proposal that was adding stuff to
> > rtnetlink? I remember some discussion long-ish ago, maybe I was wrong.
>
> This is the patch from the discussion I put the link in the cover letter:
> https://lore.kernel.org/netdev/20250828164345.116097-1-arkadiusz.kubalewski@intel.com/
Let's go back to something like that. But leave the OC info out of
the XO, just ext-ref, dpll, xo? We can add the xo types later if really
needed. Sorry for the flip flop.
next prev parent reply other threads:[~2026-04-12 14:50 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-02 23:06 [Intel-wired-lan] [PATCH v5 net-next 0/8] dpll/ice: Add TXC DPLL type and full TX reference clock control for E825 Grzegorz Nitka
2026-04-02 23:06 ` Grzegorz Nitka
2026-04-02 23:06 ` [Intel-wired-lan] [PATCH v5 net-next 1/8] dpll: add new DPLL type for transmit clock (TXC) usage Grzegorz Nitka
2026-04-02 23:06 ` Grzegorz Nitka
2026-04-02 23:06 ` [Intel-wired-lan] [PATCH v5 net-next 2/8] dpll: allow registering FW-identified pin with a different DPLL Grzegorz Nitka
2026-04-02 23:06 ` Grzegorz Nitka
2026-04-02 23:06 ` [Intel-wired-lan] [PATCH v5 net-next 3/8] dpll: extend pin notifier and netlink events with notification source ID Grzegorz Nitka
2026-04-02 23:06 ` Grzegorz Nitka
2026-04-03 11:53 ` [Intel-wired-lan] " Jiri Pirko
2026-04-03 11:53 ` Jiri Pirko
2026-04-02 23:06 ` [Intel-wired-lan] [PATCH v5 net-next 4/8] dpll: zl3073x: allow SyncE_Ref pin state change Grzegorz Nitka
2026-04-02 23:06 ` Grzegorz Nitka
2026-04-08 9:44 ` [Intel-wired-lan] " Ivan Vecera
2026-04-08 9:44 ` Ivan Vecera
2026-04-02 23:06 ` [Intel-wired-lan] [PATCH v5 net-next 5/8] ice: introduce TXC DPLL device and TX ref clock pin framework for E825 Grzegorz Nitka
2026-04-02 23:06 ` Grzegorz Nitka
2026-04-02 23:06 ` [Intel-wired-lan] [PATCH v5 net-next 6/8] ice: implement CPI support for E825C Grzegorz Nitka
2026-04-02 23:06 ` Grzegorz Nitka
2026-04-02 23:06 ` [Intel-wired-lan] [PATCH v5 net-next 7/8] ice: add Tx reference clock index handling to AN restart command Grzegorz Nitka
2026-04-02 23:06 ` Grzegorz Nitka
2026-04-02 23:06 ` [Intel-wired-lan] [PATCH v5 net-next 8/8] ice: implement E825 TX ref clock control and TXC hardware sync status Grzegorz Nitka
2026-04-02 23:06 ` Grzegorz Nitka
2026-04-07 2:23 ` [Intel-wired-lan] [PATCH v5 net-next 0/8] dpll/ice: Add TXC DPLL type and full TX reference clock control for E825 Jakub Kicinski
2026-04-07 2:23 ` Jakub Kicinski
2026-04-09 11:21 ` [Intel-wired-lan] " Nitka, Grzegorz
2026-04-09 11:21 ` Nitka, Grzegorz
2026-04-10 1:10 ` [Intel-wired-lan] " Jakub Kicinski
2026-04-10 1:10 ` Jakub Kicinski
2026-04-10 14:23 ` [Intel-wired-lan] " Nitka, Grzegorz
2026-04-10 14:23 ` Nitka, Grzegorz
2026-04-10 20:38 ` [Intel-wired-lan] " Jakub Kicinski
2026-04-10 20:38 ` Jakub Kicinski
2026-04-12 13:50 ` [Intel-wired-lan] " Nitka, Grzegorz
2026-04-12 13:50 ` Nitka, Grzegorz
2026-04-12 14:50 ` Jakub Kicinski [this message]
2026-04-12 14:50 ` Jakub Kicinski
2026-04-13 8:19 ` [Intel-wired-lan] " Kubalewski, Arkadiusz
2026-04-13 8:19 ` Kubalewski, Arkadiusz
2026-04-13 17:40 ` [Intel-wired-lan] " Jakub Kicinski
2026-04-13 17:40 ` Jakub Kicinski
2026-04-14 21:58 ` [Intel-wired-lan] " Jakub Kicinski
2026-04-14 21:58 ` Jakub Kicinski
2026-04-15 13:23 ` [Intel-wired-lan] " Kubalewski, Arkadiusz
2026-04-15 13:23 ` Kubalewski, Arkadiusz
2026-04-16 15:27 ` [Intel-wired-lan] " Jakub Kicinski
2026-04-16 15:27 ` Jakub Kicinski
2026-04-16 18:26 ` [Intel-wired-lan] " Kubalewski, Arkadiusz
2026-04-16 18:26 ` Kubalewski, Arkadiusz
2026-04-17 1:04 ` Jakub Kicinski
2026-04-17 12:22 ` Kubalewski, Arkadiusz
2026-04-17 12:22 ` Kubalewski, Arkadiusz
2026-04-18 19:26 ` Jakub Kicinski
2026-04-20 14:52 ` Kubalewski, Arkadiusz
2026-04-20 14:52 ` Kubalewski, Arkadiusz
2026-04-30 9:53 ` Nitka, Grzegorz
2026-04-30 9:53 ` Nitka, Grzegorz
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