From: Junjie Cao <junjie.cao@intel.com>
To: qemu-devel@nongnu.org
Cc: junjie.cao@intel.com, mst@redhat.com, jasowang@redhat.com,
yi.l.liu@intel.com, clement.mathieu--drif@bull.com,
philmd@linaro.org, zhenzhong.duan@intel.com
Subject: [PATCH v2 1/2] intel_iommu: widen impl.min_access_size to 8 to fix MMIO abort
Date: Sat, 25 Apr 2026 04:18:41 +0800 [thread overview]
Message-ID: <20260424201842.176953-2-junjie.cao@intel.com> (raw)
In-Reply-To: <20260424201842.176953-1-junjie.cao@intel.com>
Raise .impl.min_access_size from 4 to 8 in vtd_mem_ops so the memory
subsystem always widens guest accesses to 8 bytes before calling the
handler. This eliminates all 25 assert(size == 4) sites that crashed
QEMU on an 8-byte access to a 32-bit-only register.
With size always 8, the if/else branches for 64-bit register pairs
collapse. A zero-extended 4-byte write to the low half is safe:
wmask protects read-only upper bits, and trigger functions re-read
the register file and guard on their action bits.
The entry bounds check is relaxed to `addr >= DMAR_REG_SIZE` since
the widened size no longer reflects the guest access width; the
framework guarantees addr stays within the MemoryRegion. Default
branches fall back to vtd_get/set_long() when addr + 8 would exceed
the register file.
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Junjie Cao <junjie.cao@intel.com>
---
hw/i386/intel_iommu.c | 121 ++++++++----------------------------------
1 file changed, 23 insertions(+), 98 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index f395fa248c..4b25907778 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3697,7 +3697,7 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
trace_vtd_reg_read(addr, size);
- if (addr + size > DMAR_REG_SIZE) {
+ if (addr >= DMAR_REG_SIZE) {
error_report_once("%s: MMIO over range: addr=0x%" PRIx64
" size=0x%x", __func__, addr, size);
return (uint64_t)-1;
@@ -3707,13 +3707,9 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
/* Root Table Address Register, 64-bit */
case DMAR_RTADDR_REG:
val = vtd_get_quad_raw(s, DMAR_RTADDR_REG);
- if (size == 4) {
- val = val & ((1ULL << 32) - 1);
- }
break;
case DMAR_RTADDR_REG_HI:
- assert(size == 4);
val = vtd_get_quad_raw(s, DMAR_RTADDR_REG) >> 32;
break;
@@ -3722,26 +3718,21 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
val = s->iq |
(vtd_get_quad(s, DMAR_IQA_REG) &
(VTD_IQA_QS | VTD_IQA_DW_MASK));
- if (size == 4) {
- val = val & ((1ULL << 32) - 1);
- }
break;
case DMAR_IQA_REG_HI:
- assert(size == 4);
val = s->iq >> 32;
break;
case DMAR_PEUADDR_REG:
- assert(size == 4);
val = vtd_get_long_raw(s, DMAR_PEUADDR_REG);
break;
default:
- if (size == 4) {
- val = vtd_get_long(s, addr);
- } else {
+ if (addr + 8 <= DMAR_REG_SIZE) {
val = vtd_get_quad(s, addr);
+ } else {
+ val = vtd_get_long(s, addr);
}
}
@@ -3755,7 +3746,7 @@ static void vtd_mem_write(void *opaque, hwaddr addr,
trace_vtd_reg_write(addr, size, val);
- if (addr + size > DMAR_REG_SIZE) {
+ if (addr >= DMAR_REG_SIZE) {
error_report_once("%s: MMIO over range: addr=0x%" PRIx64
" size=0x%x", __func__, addr, size);
return;
@@ -3770,238 +3761,172 @@ static void vtd_mem_write(void *opaque, hwaddr addr,
/* Context Command Register, 64-bit */
case DMAR_CCMD_REG:
- if (size == 4) {
- vtd_set_long(s, addr, val);
- } else {
- vtd_set_quad(s, addr, val);
- vtd_handle_ccmd_write(s);
- }
+ vtd_set_quad(s, addr, val);
+ vtd_handle_ccmd_write(s);
break;
case DMAR_CCMD_REG_HI:
- assert(size == 4);
vtd_set_long(s, addr, val);
vtd_handle_ccmd_write(s);
break;
/* IOTLB Invalidation Register, 64-bit */
case DMAR_IOTLB_REG:
- if (size == 4) {
- vtd_set_long(s, addr, val);
- } else {
- vtd_set_quad(s, addr, val);
- vtd_handle_iotlb_write(s);
- }
+ vtd_set_quad(s, addr, val);
+ vtd_handle_iotlb_write(s);
break;
case DMAR_IOTLB_REG_HI:
- assert(size == 4);
vtd_set_long(s, addr, val);
vtd_handle_iotlb_write(s);
break;
case DMAR_PEUADDR_REG:
- assert(size == 4);
vtd_set_long(s, addr, val);
break;
/* Invalidate Address Register, 64-bit */
case DMAR_IVA_REG:
- if (size == 4) {
- vtd_set_long(s, addr, val);
- } else {
- vtd_set_quad(s, addr, val);
- }
+ vtd_set_quad(s, addr, val);
break;
case DMAR_IVA_REG_HI:
- assert(size == 4);
vtd_set_long(s, addr, val);
break;
/* Fault Status Register, 32-bit */
case DMAR_FSTS_REG:
- assert(size == 4);
vtd_set_long(s, addr, val);
vtd_handle_fsts_write(s);
break;
/* Fault Event Control Register, 32-bit */
case DMAR_FECTL_REG:
- assert(size == 4);
vtd_set_long(s, addr, val);
vtd_handle_fectl_write(s);
break;
/* Fault Event Data Register, 32-bit */
case DMAR_FEDATA_REG:
- assert(size == 4);
vtd_set_long(s, addr, val);
break;
/* Fault Event Address Register, 32-bit */
case DMAR_FEADDR_REG:
- if (size == 4) {
- vtd_set_long(s, addr, val);
- } else {
- /*
- * While the register is 32-bit only, some guests (Xen...) write to
- * it with 64-bit.
- */
- vtd_set_quad(s, addr, val);
- }
+ vtd_set_quad(s, addr, val);
break;
/* Fault Event Upper Address Register, 32-bit */
case DMAR_FEUADDR_REG:
- assert(size == 4);
vtd_set_long(s, addr, val);
break;
/* Protected Memory Enable Register, 32-bit */
case DMAR_PMEN_REG:
- assert(size == 4);
vtd_set_long(s, addr, val);
break;
/* Root Table Address Register, 64-bit */
case DMAR_RTADDR_REG:
- if (size == 4) {
- vtd_set_long(s, addr, val);
- } else {
- vtd_set_quad(s, addr, val);
- }
+ vtd_set_quad(s, addr, val);
break;
case DMAR_RTADDR_REG_HI:
- assert(size == 4);
vtd_set_long(s, addr, val);
break;
/* Invalidation Queue Tail Register, 64-bit */
case DMAR_IQT_REG:
- if (size == 4) {
- vtd_set_long(s, addr, val);
- } else {
- vtd_set_quad(s, addr, val);
- }
+ vtd_set_quad(s, addr, val);
vtd_handle_iqt_write(s);
break;
case DMAR_IQT_REG_HI:
- assert(size == 4);
vtd_set_long(s, addr, val);
/* 19:63 of IQT_REG is RsvdZ, do nothing here */
break;
/* Invalidation Queue Address Register, 64-bit */
case DMAR_IQA_REG:
- if (size == 4) {
- vtd_set_long(s, addr, val);
- } else {
- vtd_set_quad(s, addr, val);
- }
+ vtd_set_quad(s, addr, val);
vtd_update_iq_dw(s);
break;
case DMAR_IQA_REG_HI:
- assert(size == 4);
vtd_set_long(s, addr, val);
break;
/* Invalidation Completion Status Register, 32-bit */
case DMAR_ICS_REG:
- assert(size == 4);
vtd_set_long(s, addr, val);
vtd_handle_ics_write(s);
break;
/* Invalidation Event Control Register, 32-bit */
case DMAR_IECTL_REG:
- assert(size == 4);
vtd_set_long(s, addr, val);
vtd_handle_iectl_write(s);
break;
/* Invalidation Event Data Register, 32-bit */
case DMAR_IEDATA_REG:
- assert(size == 4);
vtd_set_long(s, addr, val);
break;
/* Invalidation Event Address Register, 32-bit */
case DMAR_IEADDR_REG:
- assert(size == 4);
vtd_set_long(s, addr, val);
break;
/* Invalidation Event Upper Address Register, 32-bit */
case DMAR_IEUADDR_REG:
- assert(size == 4);
vtd_set_long(s, addr, val);
break;
/* Fault Recording Registers, 128-bit */
case DMAR_FRCD_REG_0_0:
- if (size == 4) {
- vtd_set_long(s, addr, val);
- } else {
- vtd_set_quad(s, addr, val);
- }
+ vtd_set_quad(s, addr, val);
break;
case DMAR_FRCD_REG_0_1:
- assert(size == 4);
vtd_set_long(s, addr, val);
break;
case DMAR_FRCD_REG_0_2:
- if (size == 4) {
- vtd_set_long(s, addr, val);
- } else {
- vtd_set_quad(s, addr, val);
- /* May clear bit 127 (Fault), update PPF */
- vtd_update_fsts_ppf(s);
- }
+ vtd_set_quad(s, addr, val);
+ /* May clear bit 127 (Fault), update PPF */
+ vtd_update_fsts_ppf(s);
break;
case DMAR_FRCD_REG_0_3:
- assert(size == 4);
vtd_set_long(s, addr, val);
/* May clear bit 127 (Fault), update PPF */
vtd_update_fsts_ppf(s);
break;
case DMAR_IRTA_REG:
- if (size == 4) {
- vtd_set_long(s, addr, val);
- } else {
- vtd_set_quad(s, addr, val);
- }
+ vtd_set_quad(s, addr, val);
break;
case DMAR_IRTA_REG_HI:
- assert(size == 4);
vtd_set_long(s, addr, val);
break;
case DMAR_PRS_REG:
- assert(size == 4);
vtd_set_long(s, addr, val);
vtd_handle_prs_write(s);
break;
case DMAR_PECTL_REG:
- assert(size == 4);
vtd_set_long(s, addr, val);
vtd_handle_pectl_write(s);
break;
default:
- if (size == 4) {
- vtd_set_long(s, addr, val);
- } else {
+ if (addr + 8 <= DMAR_REG_SIZE) {
vtd_set_quad(s, addr, val);
+ } else {
+ vtd_set_long(s, addr, val);
}
}
}
@@ -4184,7 +4109,7 @@ static const MemoryRegionOps vtd_mem_ops = {
.write = vtd_mem_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
- .min_access_size = 4,
+ .min_access_size = 8,
.max_access_size = 8,
},
.valid = {
--
2.43.0
next prev parent reply other threads:[~2026-04-24 12:17 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-24 20:18 [PATCH v2 0/2] intel_iommu: fix guest-triggerable assert in MMIO handlers Junjie Cao
2026-04-24 20:18 ` Junjie Cao [this message]
2026-04-24 13:58 ` [PATCH v2 1/2] intel_iommu: widen impl.min_access_size to 8 to fix MMIO abort Philippe Mathieu-Daudé
2026-04-27 1:24 ` Junjie Cao
2026-04-27 5:23 ` Duan, Zhenzhong
2026-04-30 0:16 ` Junjie Cao
2026-04-30 8:31 ` Duan, Zhenzhong
2026-05-06 3:19 ` [PATCH v3 0/2] intel_iommu: fix guest-triggerable assert in MMIO handlers Junjie Cao
2026-05-06 3:19 ` [PATCH v3 1/2] intel_iommu: fix guest-triggerable abort on oversized MMIO access Junjie Cao
2026-05-08 9:36 ` Yi Liu
2026-05-11 5:41 ` Duan, Zhenzhong
2026-05-14 13:42 ` Junjie Cao
2026-05-14 6:59 ` Yi Liu
2026-05-06 3:19 ` [PATCH v3 2/2] tests/qtest: add 8-byte MMIO access sweep for intel-iommu Junjie Cao
2026-04-24 20:18 ` [PATCH v2 " Junjie Cao
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