From: Junjie Cao <junjie.cao@intel.com>
To: qemu-devel@nongnu.org
Cc: junjie.cao@intel.com, zhenzhong.duan@intel.com,
philmd@linaro.org, mst@redhat.com, jasowang@redhat.com,
yi.l.liu@intel.com, clement.mathieu--drif@bull.com,
marcel.apfelbaum@gmail.com, pbonzini@redhat.com,
richard.henderson@linaro.org, farosas@suse.de,
lvivier@redhat.com
Subject: [PATCH v3 2/2] tests/qtest: add 8-byte MMIO access sweep for intel-iommu
Date: Wed, 6 May 2026 11:19:42 +0800 [thread overview]
Message-ID: <20260506031942.251335-3-junjie.cao@intel.com> (raw)
In-Reply-To: <DS4PPF93A1BBECDC498B677FE8B259BCEAD92352@DS4PPF93A1BBECD.namprd11.prod.outlook.com>
Sweep every 4-byte-aligned offset in the VT-d MMIO register space
with 8-byte reads and writes to verify that no register handler
aborts on an oversized access.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Junjie Cao <junjie.cao@intel.com>
---
tests/qtest/intel-iommu-test.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/tests/qtest/intel-iommu-test.c b/tests/qtest/intel-iommu-test.c
index e5cc6acaf0..b1763ed294 100644
--- a/tests/qtest/intel-iommu-test.c
+++ b/tests/qtest/intel-iommu-test.c
@@ -17,11 +17,39 @@
#define ECAP_STAGE_1_FIXED1 (VTD_ECAP_QI | VTD_ECAP_IR | VTD_ECAP_IRO | \
VTD_ECAP_MHMV | VTD_ECAP_SMTS | VTD_ECAP_FSTS)
+static inline uint32_t vtd_reg_readl(QTestState *s, uint64_t offset)
+{
+ return qtest_readl(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset);
+}
+
static inline uint64_t vtd_reg_readq(QTestState *s, uint64_t offset)
{
return qtest_readq(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset);
}
+static inline void vtd_reg_writeq(QTestState *s, uint64_t offset,
+ uint64_t value)
+{
+ qtest_writeq(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset, value);
+}
+
+static void test_intel_iommu_8byte_access(void)
+{
+ QTestState *s;
+ uint64_t off;
+
+ s = qtest_init("-M q35 -device intel-iommu");
+
+ for (off = 0; off < DMAR_REG_SIZE; off += 4) {
+ vtd_reg_readq(s, off);
+ vtd_reg_writeq(s, off, 0);
+ }
+
+ g_assert_cmpuint(vtd_reg_readl(s, DMAR_VER_REG), !=, 0);
+
+ qtest_quit(s);
+}
+
static void test_intel_iommu_stage_1(void)
{
uint8_t init_csr[DMAR_REG_SIZE]; /* register values */
@@ -58,6 +86,8 @@ static void test_intel_iommu_stage_1(void)
int main(int argc, char **argv)
{
g_test_init(&argc, &argv, NULL);
+ qtest_add_func("/q35/intel-iommu/8byte-access",
+ test_intel_iommu_8byte_access);
qtest_add_func("/q35/intel-iommu/stage-1", test_intel_iommu_stage_1);
return g_test_run();
--
2.43.0
next prev parent reply other threads:[~2026-05-06 3:20 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-24 20:18 [PATCH v2 0/2] intel_iommu: fix guest-triggerable assert in MMIO handlers Junjie Cao
2026-04-24 20:18 ` [PATCH v2 1/2] intel_iommu: widen impl.min_access_size to 8 to fix MMIO abort Junjie Cao
2026-04-24 13:58 ` Philippe Mathieu-Daudé
2026-04-27 1:24 ` Junjie Cao
2026-04-27 5:23 ` Duan, Zhenzhong
2026-04-30 0:16 ` Junjie Cao
2026-04-30 8:31 ` Duan, Zhenzhong
2026-05-06 3:19 ` [PATCH v3 0/2] intel_iommu: fix guest-triggerable assert in MMIO handlers Junjie Cao
2026-05-06 3:19 ` [PATCH v3 1/2] intel_iommu: fix guest-triggerable abort on oversized MMIO access Junjie Cao
2026-05-08 9:36 ` Yi Liu
2026-05-11 5:41 ` Duan, Zhenzhong
2026-05-14 13:42 ` Junjie Cao
2026-05-14 6:59 ` Yi Liu
2026-05-06 3:19 ` Junjie Cao [this message]
2026-04-24 20:18 ` [PATCH v2 2/2] tests/qtest: add 8-byte MMIO access sweep for intel-iommu Junjie Cao
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