Re: [PATCH v2 1/2] intel_iommu: widen impl.min_access_size to 8 to fix MMIO abort

[Junjie Cao <junjie.cao@intel.com>]

Hi Philippe,

Thanks for the review and the good question.

Looking at access_with_adjusted_size(), the _HI offsets (0x24, 0x2c, ...)
and standalone 32-bit registers like DMAR_PEUADDR_REG (0xec) are
4-byte-aligned but not 8-byte-aligned.  An 8-byte guest access to them
is indeed rejected by memory_region_access_valid (0xec & 7 != 0).  But a
4-byte access passes (0xec & 3 == 0), and the framework then widens size
to 8 while keeping the original addr -- so the handler is still reached
at these offsets.

For example, a guest 4-byte write to DMAR_PEUADDR_REG (0xec):

  1. memory_region_access_valid: size=4, 0xec & 3 == 0 -> pass
  2. access_with_adjusted_size: access_size = MAX(MIN(4,8),8) = 8
  3. write_accessor calls vtd_mem_write(opaque, 0xec, val_zext, 8)
  4. switch(addr) -> case DMAR_PEUADDR_REG -> vtd_set_long(s, addr, val)

So I believe these branches are still needed.  Please let me know if
I've missed something, or if you'd like any changes for v3.

Many thanks,
Junjie